Unified method to detect transistor Stuck-Open Faults & Transition Delay Faults
[ETS'06-N.Devtaprasanna,A.Gunda,P.Krishnamurthy,S.M.Reddy,I.Pomeranz]

Binod Kumar

Outline

Introduction to transition delay fault(TDF) model

Introduction to transistor Stuck-Open Defects(SOP) model

Relationship between TDF and SOP fault model

SOP enhanced TDF(SOE-TDF) test generation

Results based on SOE-TDF test generation.

Introduction to TDF model

TDF model represents gross delay defects at each gate terminal in the circuit.

At each gate pin, two TDFs, a slow-to-rise (str) and a slow-to-fall (stf) fault, are included in the fault list.

In order to test a TDF, a pair of test patterns isapplied to the circuit under test.

Introduction to TDF model

Corresponding to the three gate terminals, there are six TDFs.

The gate output has a logic value of 0for the fault free case and 1 if the fault is present.

Introduction to transistor Stuck-Open Defects(SOP) model

The SOP fault model assumes that each transistor in the circuit can be permanently faulty and it cannot conduct any current.

SOP faults are the extreme case of weakly conducting transistors that deliver less than the designed current for charging and discharging gate output nodes which in turn increases the gate delays.

Similar to the TDF model, a two-pattern test is required to test a SOP fault.

Introduction to transistor Stuck-Open Defects(SOP) model

For a SOP fault in the NMOS (PMOS) network, the first pattern sets the output of the faulty gate to 1 (0).

The second pattern activates the fault by trying to discharge (charge) the gate output by enabling a unique path from the output to the ground (power supply) through the faulty transistor. If a fault is present, the output remains at 1 (0) otherwise it changes to 0 (1).

Introduction to transistor Stuck-Open Defects(SOP) model

The gate has four transistors and hence four possible SOP faults.

Testing of Stuck-open Fault

The first pattern sets the o/p to logic value of 1 by assigning the inputs (a, b) = (0, 0). The second pattern (a, b) = (0, 1) enables a unique path from the output to the ground through the target transistor N2. If the SOP fault is present, then the output will be in a high impedance state retaining logic value 1 set in the previous cycle. In the absence of the fault output will be 0.

TDF and SOP fault tests for 2-input NOR gate

SOP fault coverage of TDF and SOE-TDF test patterns

[24]:N. Devtaprasanna, A. Gunda, P. Krishnamurthy, S. M. Reddy, I. Pomeranz, Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions, Proc. ATS, 2005, pp. 202-207.

TDF Coverage of TDF and SOE-TDF test patterns

[24]:N. Devtaprasanna, A. Gunda, P. Krishnamurthy, S. M. Reddy, I. Pomeranz, Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions, Proc. ATS, 2005, pp. 202-207.

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