precision timed machine (pret)
DESCRIPTION
Y. X. PC 1. PC 1. PC 1. PC 1. IR. t0. t1. t2. t3. t4. t5. t6. t7. t8. t9. t10. t11. t12. t13. t14. F. D. X. M. W. F. D. D. D. D. X. M. W. F. F. F. F. D. D. D. D. X. M. W. F. F. F. F. D. D. D. D. - PowerPoint PPT PresentationTRANSCRIPT
Precision Timed Machine (PRET)
http://chess.eecs.berkeley.edu/
February 21, 2008
Center for Hybrid and Embedded Software Systems
Precision Timed Machine (PRET)
Isaac LiuBen Lickly
MissionThe goal of the PRET project is to develop new abstractions
for computer systems that emphasize correctness of timing on the
same level as performance and traditional functional correctness.We
feel that all abstraction layers, from the high level programming
specifications to the low level architecture, must be augmented in
order to support these aims.Hardware ArchitectureIn our research,
we have pursued a bottom-up approach. Starting with the underlying
architecture (in our case an open source SPARC core), we have
modified and added constructs to improve the timing predictability
at the architectural and instruction-set-architecture level
PipeliningStalls, branch predictions, caches introduce
unpredictability
Interleaved multithreadingBy using interleaving threads through our
piprline, we are able to remove the data hazard and dependencies in
the pipeline, creating a timing predictable pipeline.
Processor modelBefore making extensive architectural modifications
to our SPARC core, we built a SystemC model of our processor:
SystemC transaction-level model more abstract than than register
transfer level (such as VHDL)Faster and easier modeling and
explorationBut, could not abstract away details of timing of the
system!
ISA AugmentationFinding the best way in which an instruction set
can be extended to support timing is an ongoing area of research.
One approach that has been implemented involves adding deadline
instructions to the ISA, which allow a program to specify how long
certain blocks of code should take.
SPARC ModificationsFor our research, we chose to modify an open
source VHDL implementation of the SPARC version 8 architecture
processor created by Gaisler Research Labs called the LEON3. It
contains a simple 7 stage pipeline with no branch prediction and
adjustable peripherals. It also included compiler tool chains and
support for convenient debug and testing.
Center for Hybrid and Embedded Software Systems
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