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Force Computers GmbHAll Rights Reserved

This document shall not be duplicated, nor its contents usedfor any purpose, unless express permission has been granted.

Copyright by Force Computers

PPC/PowerCore-6603/4Reference Guide

P/N 204421 Edition 4.0August 2001

World Wide Web: www.forcecomputers.com 24-hour access to on-line manuals, driver updates, and application notes is provided via SMART, our SolutionsPLUS customer support program

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Headquarters

The Americas Europe Asia

Force Computers Inc.5799 Fontanoso WaySan Jose, CA 95138-1015U.S.A.

Tel.: +1 (408) 369-6000Fax: +1 (408) 371-3382Email: [email protected]

Force Computers GmbHProf.-Messerschmitt-Str. 1D-85579 Neubiberg/MünchenGermany

Tel.: +49 (89) 608 14-0 Fax: +49 (89) 609 77 93Email: [email protected]

Force Computers Japan KKShiba Daimon MF Building 4F2-1-16 Shiba DaimonMinato-ku, Tokyo 105-0012 Japan

Tel.: +81 (03) 3437 3948Fax: +81 (03) 3437 3968Email: [email protected]

NOTE

The information in this document has been carefully checked and is believed to be entirely reliable. Force Computers makes no warranty of any kind with regard to the material in this document, and assumes no responsibility for any errors which may appear in this document. Force Computers reserves the right to make changes without notice to this, or any of its products, to improve reliability, performance, or design.

Force Computers assumes no responsibility for the use of any circuitry other than circuitry which is part of a product of Force Computers GmbH. Force Computers does not convey to the purchaser of the product described herein any license under the patent rights of Force Computers GmbH nor the rights of others. All product names mentioned herein are the trademarks or registered trademarks of their respective companies.

Copyright 2000 by Force Computers. All rights reserved. This document shall not be reproduced, transmitted, or stored in a retrieval system, nor its contents used for any purpose, without the prior written consent of Force Computers GmbH.

Contents

Table of Contents

0

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14

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Using This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

Safety Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv

Sicherheitshinweise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Product Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Installation Prerequisites and Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1.2 Terminal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.3 Location Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.4 Upgrading PPC/PowerCore-6603/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Automatic Power Up – Voltage Sensor and Watchdog Timer . . . . . . . . . . . . . . . . . . 1

2.3 Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 PPC/PowerCore-6603/4 Parameters and Timers – CIO . . . . . . . . . . . . . . . . . . . . . . .

2.6 Serial I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.7 IDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.8 PMC Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.8.1 PMC Voltage Keys. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.8.2 Connector Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.8.3 ISA Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.9 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PPC/PowerCore-6603/4 Page iii

Contents

19

. 20

. 22

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.

. 39

44

. .

. .

. 51

2.10 VMEbus Interface – Universe II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 VMEbus P2 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12 Testing the CPU Board Using PowerBoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13 PPC/SSIO-6603/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.13.1 Location Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.13.2 Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.13.3 Serial I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.13.4 SCSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.13.5 Ethernet AUI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.13.6 VMEbus P2 Connector Pinout of the Base Board . . . . . . . . . . . . . . . . . . . . . . . 30

2.14 IOBP-SSIO/232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.1 PPC/PowerCore-6603/4 Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 PPC/PowerCore-6603/4 Interrupt Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 PowerPC CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.3.1 PowerPC 603e and PowerPC 603ev . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.3.2 PowerPC 604e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.4 L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.5 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.5.1 Watchdog Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.6 System Memory (EDO RAM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.1 Memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.6.2 EDO RAM Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.6.3 EDO RAM Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.6.4 EDO RAM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.6.5 Cache Coherency and Snooping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.6.6 EDO RAM Access from the PowerPC CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.6.7 EDO RAM Access via the VMEbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.6.8 EDO RAM Access from the Ethernet Controller. . . . . . . . . . . . . . . . . . . . . . . . 56

3.6.9 EDO RAM Access from PMC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.6.10 EDO RAM Access from the PCI-to-ISA Bridge . . . . . . . . . . . . . . . . . . . . . . . . 56

Page iv PPC/PowerCore-6603/4

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77

3.7 Boot Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.7.1 Boot Flash Address Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.7.2 Boot Flash Size and Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.7.3 Boot Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.7.4 Programming the Boot Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.8 User Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.8.1 User Flash Address Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.8.2 User Flash Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.8.3 User Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.8.4 Programming the User Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.9 PowerPC-to-PCI Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.10 VMEbus Interface – Universe II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10.1 VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.10.2 Exception Signals SYSFAIL, SYSRESET, and ACFAIL . . . . . . . . . . . . . . . . . 66

3.10.3 VMEbus Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.10.4 VMEbus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.10.5 DMA-Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.11 VMEbus Slot-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 70

3.11.1 Slot-1 Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.11.2 The SYSCLK Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.11.3 VMEbus Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.12 VMEbus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.12.1 VMEbus Arbitration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.12.2 VMEbus Requester. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.12.3 VMEbus Release Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.13 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.13.1 Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.13.2 Ethernet Interface Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.14 PCI-to-ISA Bridge and IDE Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.14.1 PCI-to-ISA Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.14.2 IDE Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.14.3 Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

PPC/PowerCore-6603/4 Page v

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81

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ely

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. 92

93

. 95

96

104

05

06

07

3.15 Real-Time Clock / Non-Volatile RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.16 PPC/PowerCore-6603/4 Parameters and Timers – CIO . . . . . . . . . . . . . . . . . . . . . . .

3.16.1 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.16.2 Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.16.3 CIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.16.4 CIO Port A Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.16.5 CIO Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.16.6 CIO Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.17 Serial I/O Port – SCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.18 PMC Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.18.1 Busmode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4 PowerBoot (= PowerBoot Instruction Set) . . . . . . . . . . . . . . . . . . . . . . . paginated separat

5 PowerBoot for PPC/PowerCore-6603/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 PPC/PowerCore-6603/4 Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 PMCPCI – Mapping PMC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 RESET – Restarting the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 SETBOOT – Editing Auto Boot Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 USERLED – Setting User LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 VMEMST – Opening an A32/D32 Master Window. . . . . . . . . . . . . . . . . . . . . . . . . . 1

5.7 VMESLV – Opening an A32/D32 Slave Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

5.8 VMESYS – Enabling VMEbus System Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Product Error Report

Page vi PPC/PowerCore-6603/4

Tables and Figures

List of Tables and Figures

Page Tab./Fig.

. 5. 6

7. 8. 9. 10. 1b. 11b. 12. 13. 2

b. 14. 3. 4. 5b. 1. 6. 7. 8b. 16b. 17b. 18. 19. 9ab. 20b. 21b. 22b. 23b. 24b. 25

b. 26b. 27. 28. 29b. 30

History of Manual Publication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi Tab. 1Fonts, Notations and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii Tab. 2Specification of the PPC/PowerCore-6603/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Tab. 3Nomenclature of the PPC/PowerCore-6603/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Tab. 4Excerpt from the data sheet’s ordering information. . . . . . . . . . . . . . . . . . . . . . . . . 3 TabTypical Power Requirements of the CPU Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TabQualified Memory Module Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Tab.Max. Power Consumption Values of the Memory Modules . . . . . . . . . . . . . . . . . . 7 TabMaximum Permissible Power Consumption of PMC Modules . . . . . . . . . . . . . . . . 7 TabEnvironmental Requirements of PPC/PowerCore-6603/4 . . . . . . . . . . . . . . . . . . . . 8 TabLocation Diagram of the PPC/PowerCore-6603/4 (schematic) . . . . . . . . . . . . . . . . 9 FigSwitch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TaFront Panel Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TaPinout of the Front-Panel Serial I/O Port for RS-232 . . . . . . . . . . . . . . . . . . . . . . 15 TabPN15 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Fig8-pin RJ45 Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ta3- or 5-row P2 Connector Pinout, Row A and C . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Fig5-Row P2 Connector Pinout, Row Z and D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 FigLocation diagram of the PPC/SSIO-6603/4 (schematic) . . . . . . . . . . . . . . . . . . . . 26 FigSwitch settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ta5SCSI termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Fig3- or 5-row P2 connector pinout of the base board, row A and C . . . . . . . . . . . . . 30 FigIOBP-SSIO/232 (schematic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FigSerial connectors pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TaEthernet connector pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TaSCSI connector pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TaWide SCSI connector pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TabPPC/PowerCore-6603/4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FigBuses, busmodes, and connected devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TBus frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TaPPC/PowerCore-6603/4 memory map seen from the CPU . . . . . . . . . . . . . . . . . . 40 TaPPC/PowerCore-6603/4 memory map seen from the PCI . . . . . . . . . . . . . . . . . . . 41 TaPPC/PowerCore-6603/4 I/O map seen from the PCI . . . . . . . . . . . . . . . . . . . . . . . 42 TaPPC/PowerCore-6603/4 configuration base addresses . . . . . . . . . . . . . . . . . . . . . 42 TaPPC/PowerCore-6603/4 ISA bus ports seen from the CPU. . . . . . . . . . . . . . . . . . 43 TaPPC/PowerCore-6603/4 PCI I/O devices seen from the CPU . . . . . . . . . . . . . . . . 43 TaDefault PPC/PowerCore-6603/4 interrupt map . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 TabPMC interrupt routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 TabCache devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Ta

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Tables and Figures

31. 32. 33

34. 35b. 36b. 37b. 38. 39. 40. 41b. 42

b. 43b. 44. 45. 46. 47

b. 48. 10. 49. 50. 51. 52. 53b. 54b. 55

b. 56

Page Tab./Fig.DRAM and cache configuration register, bits [7…6] . . . . . . . . . . . . . . . . . . . . . . 49 Tab.CIO Port C data register, bit [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 TabCIO port B data register, bit [0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 TabDRAM and cache configuration register, bits [5…0] . . . . . . . . . . . . . . . . . . . . . . 53 Tab.EDO RAM capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 TabDefault EDO RAM access address ranges from the PowerPC CPU . . . . . . . . . . . 55 TaBoot flash address range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 TaBoot flash address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 TaBoot flash factory options, device types, and default configuration . . . . . . . . . . . 58 TabCIO port A data register, bits [7] and [5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 TabCIO port A data register, bits [7] and [3…0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 TabUser flash address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TaUser flash factory options and device types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 TaCAR and CDR address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TaVMEbus master transfer cycles def. for data bus width D32. . . . . . . . . . . . . . . . . 68 TabVMEbus master transfer cycles defined for data bus width D16. . . . . . . . . . . . . . 69 TabSlot-1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 TabGeneral purpose register of the Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . 76 TaPCI-to-ISA bridge interrupt structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 FigAddress space of the RTC/NVRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 TabCIO port A data register, bit [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 TabCIO port B data register, bits [7…6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 TabCIO port C data register, bits [1…0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 TabCIO port B data register, bits [5…3] and [2…1] . . . . . . . . . . . . . . . . . . . . . . . . . . 85 TabPPC/PowerCore-6603/4 address map seen from the CPU. . . . . . . . . . . . . . . . . . . 92 TaPCI addressing spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 TaPCI I/O addressing spaces of the SCSI controllers . . . . . . . . . . . . . . . . . . . . . . . 101 Ta

Page viii PPC/PowerCore-6603/4

Using This Manual

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Using This Manual

This section does not provide information on the product but on commonfeatures of the manual itself:

• Its structure,

• Special layout conventions,

• And related documents.

Technical Reference Manual

The Technical Reference Manual additionally includes the PowerBootInstruction Set.

Audience of the Technical Reference Manual

The Reference Guide is intended for hard- and software developers stalling and integrating the PPC/PowerCore-6603/4 into their system

Overview of the Manual Set

The Reference Guide provides a comprehensive hardware and softwguide to your CPU board.

Note: Please take a moment to examine the “Table of Contents” ofthe Reference Guide to see how this documentation is structured.This will be of value to you when looking for information in thefuture.

PPC/PowerCore-6603/4 Page ix

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Reference Guide The Technical Reference Manual includes:

• a brief overview of the product, the specifications, and the orderinformation: see section 1 “Introduction” on page 1.

• the installation instructions for powering up the board: see sectio“Installation” on page 5. It includes the default configuratio(switches and the like), initialization, and connector pinouts.

The installation instructions also appear as the product’s installaguide – a separate manual delivered together with each shipped uct.

• a detailed hardware description: see section 3 “Hardware” page 35.

• a description of the board specific PowerBoot commands: section 5 “PowerBoot for PPC/PowerCore-6603/4” on page 91.

Data Sheets The following data sheets are relevant for components of the PPC/PCore 6603/4 and can be found on the respective company´s website

• PCI-to-ISA Bridge – Intel PIIX 82371FB (http://developer.intel.com

• CIO Counter/Timer – Zilog CIO Z8536 (http://www.zilog.com)

• Real-Time Clock and NVRAM – SGS-ThomsoRTC/NVRAM M48T58(http://www.st.com)

• Serial I/O Port – Texas Instruments TL16C550C (http://www.ti.com

• Ethernet Controller – DIGITAL LAN 21140A (http://www.digi-tal.com)

• Ethernet Interface Adapter – Level one LXT901 (http://www.level1.com)

• PCI-to-VME bridge – Tundra Universe II (http://www.tundra.com)

• PowerPC-to-PCI Bridge – Motorola MPC106 Grackle (http://www.motorola.com)

PowerBoot Instruction Set

The PowerBoot Instruction Set describes only those PowerBoot commands which are independent of the CPU board. The board specific PerBoot commands are described in the Reference Guide (see section 5“PowerBoot for PPC/PowerCore-6603/4” on page 91). The PowerBoot Instruction Set is packaged separately and alwayshipped together with the Reference Guide.

☞ Insert the PowerBoot Instruction Set now: see section 4“PowerBoot (= PowerBoot Instruction Set)”.

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Publication History of the Manual

Table 1 History of Manual Publication

Edition Date Description

1 December 1996 First print

2 February 1997 Ordering information updated. Memory module description updat-ed. Description of the PCI-to-ISA bridge corrected. Power supplyvalues corrected. SETBOOT description revised. NVRAM/RTC ad-dress added.

3.0 May 1998 Installation Prerequisites and Requirements corrected, com-pleted, and restructured. Safety note extended. Battery safetynote revised. Manual description revised. Location diagramcorrected. Timer description corrected. PN15 connector pi-nout updated. PPC/SSIO-6603/4 description added. PMC slotsdescription revised. Upgrading description revised.Descrip-tion of boot flash devices updated. VMESLV and SETBOOTdescription revised and corrected. Description of PowerPC604e with 300-MHz nominal processor frequency added. NewSSIO name inserted: PPC/SSIO-6603/4. Boot flash descrip-tion updated and corrected. Editorial changes.

4.0 August 2001 Installation Prerequisites and Requirements extended and cor-rected. Ordering information updated. Document Type changed to “Reference Guide”Safety Notes revisedData sheets section removedRegister default settings addedEditorial ChangesAdded chapter Sicherheitshinweise

PPC/PowerCore-6603/4 Page xi

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Fonts, Notations and Conventions

Register Conventions

Force Computers assumes that the software developer initializes the reg-ister bits which are not described with default settings.

Table 2 Fonts, Notations and Conventions

Notation Description

0000.000016 Typical notation for hexadecimal numbers (digits are0 through F), e.g. used for addresses and offsets.Note the dot marking the 4th (to its right) and 5th (toits left) digit.

00008 Same for octal numbers (digits are 0 through 7)

00002 Same for binary numbers (digits are 0 and 1)

Program Typical character format used for names, values, andthe like that should be used typing literally the sameword. Also used for on-screen-output.

Variable Typical character format for words that represent apart of a command, a programming statement, or thelike and that will be replaced by an applicable valuewhen actually applied.

# A # symbol at the end of a PCI, ISA, or IDE signalname indicates that the signal is active when it is atlow voltage. The absence of the # symbol indicatesthat the signal is active at high voltage.

* A * symbol at the end of a VMEbus signal name indi-cates that the signal is active when it is at low voltage.The absence of the * symbol indicates that the signalis active at high voltage.

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Icons for Ease of Use: Safety Notes and Tips & Tricks

There are 3 levels of safety notes used in this manual which are describedin short in the following subsections by displaying a typical layout exam-ple.

Be sure, to always read and follow the safety notes of a section first –fore acting as documented in the other parts of the section.

Danger Dangerous situation: injuries to people or severe damage to objects pble.

Caution Possibly dangerous situation: no injuries to people but damage to obpossible.

Note: No danger encountered. Only application hints and time-saving tips & tricks or information on typical errors when using theinformation mentioned below this safety hint.

PPC/PowerCore-6603/4 Page xiii

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Page xiv PPC/PowerCore-6603/4

Safety Notes

Safety Notes

This section provides safety precautions to follow when installing, op-erating, and maintaining the PPC/PowerCore-6603/4. For your pro-tection, follow all warnings and instructions found in the followingtext.

General notes

This Reference Guide provides the necessary information to installand handle the PPC/PowerCore-6603/4. As the product is complexand its usage manifold, we do not guarantee that the given informa-tion is complete. In case you need additional information, ask yourForce Computers representative.

The PPC/PowerCore-6603/4 has been designed to meet the standardindustrial safety requirements. It must not be used except in its spe-cific area of office telecommunication industry and industrial con-trol.

Only personnel trained by Force Computers or qualified persons inelectronics or electrical engineering are authorized to install, unin-stall or maintain the PPC/PowerCore-6603/4. The information givenin this manual is meant to complete the knowledge of a specialist andmust not be taken as replacement for qualified personnel.

Make sure that contacts and cables of the board cannot be touchedwhile the board is operating.

Installation Electrostatic discharge and incorrect board installation and uninstal-lation can damage circuits or shorten their life. Therefore:

• Before installing the board, check:

– see table 6 “Typical Power Requirements of the CPU Board”on page 5.

– table 10 “Environmental Requirements of PPC/PowerCore-6603/4” on page 8.

• Before touching integrated circuits, ensure that you are workingin an electrostatic-free environment.

• When plugging the board or removing it, do not press on thefront panel but use the handles. Otherwise, the front panel can bedamaged.

PPC/PowerCore-6603/4 Page xv

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• Before installing or uninstalling the board, read section 2 “Instal-lation” on page 5.

• Before installing or uninstalling an additional device or module,read the documentation shipped with the device or the module.

• Before installing or uninstalling the board in a VME rack:

– Check all installed boards for steps that you have to takebefore turning off the power.

– Take those steps.

– Finally turn off the power.

• PMC slot 1 has 64 user I/O signals, PMC slot 2 has 32 user I/Osignals. The 32 user I/O signals of PMC slot 2 are connected with32 user I/O signals of PMC slot 1. Both, the 64 user I/O signals oPMC slot 1 and the 32 user I/O signals of PMC slot 2, are routedto the 64 user I/O pins of the VMEbus P2 connector (see figure 3“3- or 5-row P2 Connector Pinout, Row A and C” on page 20).This is compliant with the “Draft Standard for a Common Mez-zanine Card Family: CMC”, P1386/Draft 2.0.

• Do not plug in 2 PMC cards both driving the same I/O lines (seePMC cards’ manuals). Otherwise the PMC cards may be dam-aged.

Operation • While operating the board ensure that the power and environ-mental requirements as given in table 6 “Typical Power Require-ments of the CPU Board” on page 5 and table 10 “EnvironmentalRequirements of PPC/PowerCore-6603/4” on page 8 are met.

• Ensure that the board is connected to the VMEbus via both theP1 and the P2 connectors and that the power is available on bothVMEbus connectors.

• If more than one system controller is active in the VMEbus sys-tem, the board or other VMEbus participants can be damaged.

• When operating the board in areas of strong electromagneticradiation ensure that the board is bolted on the VME rack andshielded by closed housing.

• To ensure proper operation of the PPC/PowerCore-6603/4 board,remove the jumper for IACKIN-IACKOUT- and BGIN-BGOUT-bypass on the backplane. This is not necessary on activbackplanes.

Page xvi PPC/PowerCore-6603/4

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EMC • If boards are integrated into open systems, always cover emptyslots.

• The front panel of the PPC/PowerCore-6603/4 provides 2 cutoutsfor the front panels of the PMC modules. If the PPC/PowerCore-6603/4 is shipped without the related devices or modulesinstalled, the front-panel cutouts are covered by blind panels toensure proper EMC shielding.

• Always operate a PPC/PowerCore-6603/4 always with the blindpanels for the PPC/PowerCore-6603/4 front panel installed orwith the respective devices or modules installed.

• If the PPC/PowerCore-6603/4 is upgraded, ensure that the blindpanels are stored in a safe place to be used again when uninstaling the upgrades.

Boot Flash • Before erasing or programming the boot flash ensure that you donot destroy Force Computers’ firmware and make a copy of thecontents of the boot flash.

• The boot flash size is a factory option. To identify the boot flashsize for which the board is configured, read bit 5 of the CIO portA data register (see table 40 “CIO port A data register, bits [7]and [5]” on page 58 and the PowerBoot Instruction Set). If youinstall a boot flash device that has a different size than the bootflash for which the board has been configured, do not reprogramthe boot flash device on-board. Otherwise the devices could bdamaged.

Expanding • Check the total power consumption of all components installed(see the technical specification of the respective components). Fothe total power consumption of the PPC/PowerCore-6603/4, setable 6 “Typical Power Requirements of the CPU Board” onpage 5.

• Ensure that any individual output current of any source stayswithin its acceptable limits (see the technical specification of therespective source).

• Only replace components or system parts with those recom-mended by Force Computers. In case you use components othethan those recommended by Force Computers, you are fullyresponsible for the impact on EMI and the eventually changedfunctionality of the product.

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Save your environment

Always dispose used batteries and/or old boards according to yourcountry’s legislation.

Battery change

The board is designed to be maintenance-free. However, note that Lithium battery is installed on the board. The battery provides adata retention of 7 years summing up all periods of actual batteryuse. Therefore, Force Computers assumes that there is usually nneed to exchange the lithium battery except for example in the caseof long-term spare part handling.

If a Lithium battery on the board has to be exchanged, observe thefollowing safety notes:

• Exchange the battery before 7 years of actual battery use haveelapsed.

• Always use the same type of Lithium battery as is alreadyinstalled.

• Exchanging the battery always results in data loss of the devicewhich use the battery as power backup. Therefore, back upaffected data before exchanging the battery.

• When installing the new battery ensure that the marked dot ontop of the battery covers the dot marked on the chip.

• Incorrect exchange of Lithium batteries can result in a hazardousexplosion.

RJ-45 connector

If an RJ-45 connector is available on the board, take into accountthat the RJ-45 connector type is used for telephone connectors anfor twisted pair Ethernet (TPE) connectors. Note that mismatchingthese 2 connectors may destroy your telephone as well as youPPC/PowerCore-6603/4. Therefore:

• Make sure that TPE connectors near your working area areclearly marked as network connectors.

• Make sure that TPE bushing of the system is connected only tosafety extra low voltage (SELV) circuits.

• Verify that the length of the electric cable connected to a TPEbushing does not exceed 1 kilometer outside the building.

• If in doubt, ask your system administrator.

Page xviii PPC/PowerCore-6603/4

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Sicherheitshinweise

Dieser Abschnitt enthält Sicherheitshinweise, welche bei der Installation, demBetrieb und der Wartung des PPC/PowerCore-6603/4 zu beachten sind. BeacSie zu Ihrem Schutz alle folgenden Warnhinweise und Anleitungen.

Dieses Installationshandbuch enthält alle notwendigen Informationen zur Instation und zum Betrieb des PPC/PowerCore-6603/4. Da es sich um ein kompleProdukt mit einer aufwendigen Bedienung handelt, kann keine Garantie dafür nommen werden, dass die enthaltenen Informationen vollständig sind. Für weInformationen wenden Sie sich bitte an Ihren Vertreter der Firma Force Compu

Das PPC/PowerCore-6603/4 erfüllt die gültigen industriellen Sicherheitsan-forderungen. Dieses Produkt darf ausschließlich für Anwendungen innerhalb der Telekommunikationsindustrie und der industriellen Steuerung verwendet werden.

Lediglich von Force Computers eingewiesene oder im Bereich Elektrotechnikoder Elektronik qualifizierte Personen sind zur Installation, zum Betrieb und zur Wartung dieses Produktes befugt. Die in dieser Dokumentation enthalt-enen Informationen sollen lediglich als Hilfestellung für entsprechend qualifi-ziertes Fachpersonal dienen. Keinesfalls können sie dieses ersetzen.

Installation

Elektrostatische Entladung und unsachgemäße Installation und Ausbau des Boards kann Schaltkreise beschädigen oder ihre Lebensdauer verkürzen. Deswegen sind folgende Punkte vor der Installation zu überprüfen:

• Lesen Sie vor Einbau oder Ausbau des Boards Tabelle 1 “Typical Power Requirements of the CPU Board auf Seite 9 und Tabelle 5 “Environmental Requirements of PPC/PowerCore-6603/4” auf Seite 12.

• Bevor Sie integrierte Schaltkreise berühren, vergewissern Sie sich, dass Siin einem ESD-geschützten Bereich arbeiten.

• Drücken Sie beim Einbau oder Ausbau des Boards nicht auf das Front Panel, sondern benutzen Sie die Griffe.

• Lesen Sie vor dem Einbau oder Ausbau des Boards den Abschnitt “Instal-lation” auf Seite 1.

• Lesen Sie vor dem Einbau oder Ausbau von zusätzlichen Geräten oder Modulen das jeweilige Benutzerhandbuch.

PPC/PowerCore-6603/4 xix

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• Überprüfen Sie folgendes vor dem Einbau des Boards in ein VME Rack oder seinen Ausbau:

– Überprüfen Sie alle installierten Boards nach Schritten, die vor dem Abschalten unternommen werden müssen.

– Unternehmen Sie diese Schritte.

– Schalten Sie schließlich den Strom ab.

• Der PMC Steckplatz 1 hat 64 User I/O Signale, der PMC Steckplatz 2 hat 32 User I/O Signale. Die 32 User I/O Signale von PMC Steckplatz 2 sind mit 32 User I/O Signalen des PMC Steckplatz 1 verbunden. Sowohl die 64 User I/O Signale des PMC Steckplatz 1 als auch die 32 User I/O Signaledes PMC Steckplatz 2 werden zu den 64 User I/O Pins des VMEbus P2 Steckers geleitet (siehe Graphik 3 “3- or 5-row P2 Connector Pinout, Row A and C” auf Seite 20). Dies entspricht dem “Draft Standard for a Com-mon Mezzanine Card Family: CMC”, P1386/Draft 2.0.

• Stecken Sie keine zwei PMC-Karten ein, die dieselben I/O Leitungen belegen (siehe Benutzerhandbuch der PMC-Karten). Andernfalls können die PMC-Karten beschädigt werden.

Betrieb

Das Front Panel des CPU Boards hat zwei Aussparungen für die Front Panelder PMC Module. Falls das CPU Board ohne die entsprechenden installiertenBauteile oder Module geliefert wird, werden die Aussparungen am Front Panel durch Blenden abgedeckt, um EMV-Schutz zu gewährleisten. Betreiben Sie das CPU Board immer mit den installierten Blenden für das Front Panel des CPU Boards oder mit den entsprechenden installi-erten Bauteilen oder Modulen.

Vergewissern Sie sich beim Aufrüsten des CPU Boards, dass die Blenden gelagert werden, damit sie wiederverwendet werden können, wenn das Upgrade entfert wird.

Ist in dem System mehr als ein System Controller aktiv, können das Board und andere Karten oder Boards beschädigt werden.

Wenn das Board in Gebieten mit starker elektromagnetischer Strahlung betrieben wird, stellen Sie sicher, dass das Board auf dem VME Rack ver-schraubt ist und mit einem Gehäuse geschützt ist.

Entfernen Sie den Jumper für den IACKIN-IACKOUT und BGIN-BGOUT Bypass auf der Backplane für einen korrekten Betrieb des CPU Boards. Dies ist bei aktiven Backplanes nicht nötig.

xx PPC/PowerCore-6603/4

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EMV

Werden Boards in offene Systeme eingebaut, müssen freie Steckplätze mit einer Blende abgeschirmt werden.

Das Front Panel des CPU Boards hat zwei Aussparungen für die Front Panelder PMC Module. Falls das CPU Board ohne die entsprechenden installiertenBauteile oder Module geliefert wird, werden die Aussparungen am Front Panel durch Blenden abgedeckt, um EMV-Schutz zu gewährleisten.

Betreiben Sie das CPU Board immer mit den installierten Blenden für das Front Panel des CPU Boards oder mit den entsprechenden installierten Bau-teilen oder Modulen.

Vergewissern Sie sich beim Aufrüsten des CPU Boards, dass die Blenden gelagert werden, damit sie wiederverwendet werden können, wenn das Upgrade entfernt wird.

Boot Flash

Vergewissern Sie sich vor dem Löschen oder Programmieren des Boot Flashsdass Sie die Firmware von Force Computers nicht zerstören, und machen Sieeine Kopie des Boot Flash-Inhalts.

Die Grösse des Boot Flash ist optional. Um die Boot Flash Grösse, für die dasBoard konfiguriert wurde, zu identifizieren, lesen Sie Bit 5 des CIO Port A Data Registers (siehe Tabelle 40 “CIO port A data register, bits [7] and [5]” auf Seite 58 und das PowerBoot Instruction Set). Wenn Sie ein Boot Flash mit einer anderen Grösse als derjenigen installieren, für die Ihr Board konfiguri-ert wurde, repgrogrammieren Sie das Boot Flash Bauteil auf dem Board nicht. Andernfalls könnte das Bauteil beschädigt werden.

Erweiterung

Beachten Sie den Gesamtstromverbrauch aller installierter Komponenten (siehe technische Daten der entsprechenden Komponente).

Vergewissern Sie sich, daß jeder individuelle Ausgangsstrom jedes Stromverbrauchers innerhalb der zulässigen Grenzwerte liegt (siehe technische Datendes entsprechenden Verbrauchers).

Benutzen Sie bei der Erweiterung ausschließlich von Force Computers emp-fohlene Komponenten und Systemteile. Ansonsten sind Sie für die Auswirkungen auf EMV und die möglicherweise geänderte Funktionalität des Produktesverantwortlich.

PPC/PowerCore-6603/4 xxi

-

Umweltschutz

Alte Batterien und/oder Boards oder Systeme müssen stets gemäß der in Ihrem Land gültigen Gesetzgebung entsorgt werden.

Batterie

Das Board wurde für einen wartungsfreien Gebrauch entwickelt. Es befindet sich jedoch eine Lithiumbatterie auf dem Board. Die Batterie bietet einen Dat-enspeicher von bis zu sieben Jahren tatsächlicher Betriebsdauer. Daher gehtForce Computers davon aus, dass die Batterie im allgemeinen nicht gewech-selt werden muss, ausser im Falle einer Langzeitlagerung von Ersatzteilen. Muss eine Lithium Batterie auf dem Board ausgetauscht werden, müssen diefolgenden Sicherheitshinweise beachtet werden:

• Tauschen Sie die Batterie aus, bevor die sieben Jahre tatsächlicher Betriebsdauer verstrichen sind.

• Es darf nur der Batterietyp verwendet werden, der auch bereits ein-gesetzt ist.

• Ein Batteriewechsel ist immer mit einem Datenverlust bei den Bauteilen verbunden, die die Batterie als Notstromversorgung verwenden. Sichern Sie daher vor dem Austausch die betroffenen Daten.

• Vergewissern Sie sich beim Einbau einer neuen Batterie, dass die Marki-erung auf der Batterie den Punkt auf dem Chip bedeckt.

• Fehlerhafter Austausch von Lithium Batterien kann zu lebensgefährlichen Explosionen führen.

RJ-45 Stecker

RJ-45 Stecker werden sowohl für Telefonanschlüsse als auch für Twisted-pair-Ethernet (TPE) verwendet. Die Verwechslung solcher Anschlüsse kann sowohl das Telefonsystem als auch das Board zerstören. Daher:

• TPE-Anschlüsse in der Nähe Ihres Arbeitsplatzes müssen deutlich als Netzwerkanschlüsse gekennzeichnet sein.

• An TPE-Buchsen dürfen nur SELV-Kreise angeschlossen werden (Sicher-heitskleinspannungsstromkreise).

• Die Länge der an einer TPE-Buchse angeschlossenen Leitung darf nicht mehr als 100 Meter betragen.

•

xxii PPC/PowerCore-6603/4

Introduction

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1 Introduction

PPC/PowerCore-6603/4 is a high performance single-board computerproviding a Universe VMEbus interface. It is based on

• the PowerPC 603e, PowerPC 603ev, or PowerPC 604e respectiv

• two PMC slots,

• and on the VMEbus.

Memory PPC/PowerCore-6603/4 provides 16-Mbyte EDO RAM on-board. secondary (L2) cache has a size of up to 1 Mbyte. The boot flash prova maximum capacity of 1 Mbyte and the on-board user flash has a mmum capacity of 8 Mbyte. Additional memory can be installed by usinmemory module.

Interfaces PPC/PowerCore-6603/4 includes VMEbus interface, PCI bus interfIDE interfaces, Ethernet interface, and a serial I/O port to provide single-board computer functionality. The serial I/O channel is availablthe front panel via a 9-pin Micro D-Sub connector.

CPU speed Depending on the used CPU the PowerPC CPU runs with a minimuquency of 120 MHz and provides cache snooping support in ordemaintain cache coherency.

Real-time clock A real-time clock with on-board battery backup is also available.

PPC/PowerCore-6603/4 Page 1

Specification Introduction

on

ore-

1.1 Specification

PPC/PowerCore-6603/4 is available in several memory and speed op-tions. Consult your local sales representative to confirm availability ofspecific combinations.

Table 3 Specification of the PPC/PowerCore-6603/4

Processor PowerPC 603e, PowerPC 603ev, or PowerPC 604e

Shared main memory 16-Mbyte EDO RAM with ECC

PMC slots 2 for 32-bit PMC modulesI/Os for both PMC modules on VME P2

PCI-to-VME bridge Universe

Ethernet interface Ethernet controller 10Base-T on front panel

2 IDE interfaces PCI-to-ISA bridge I/O on 5-row VME P2 (factory option)

Serial I/O RS-232 compatibleI/O on front panel and 5-row VME P2 (factory option)

Counters/timers Four 16-bit, programmable

Boot flash Up to 1 Mbyte (1 Mbyte default) On-board programmableHardware write protection

User flash Up to 8 Mbyte (0 or 4 Mbyte default)On-board programmableHardware write protection

RTC/SRAM/battery Real-time clock and NVRAM

Additional features Reset and abort key, status LEDs, serial PROM for board configura-tion, voltage sensors, watchdog timer

Firmware PowerBoot

Power consumption see section 2.1 “Installation Prerequisites and Requirements” page 5

Environm. conditions see table 10 “Environmental Requirements of PPC/PowerC6603/4” on page 8

Standards compliance ANSI/VITA 1-1994IEEE P1386.1/Draft 2.0

Page 2 PPC/PowerCore-6603/4

Introduction Product Nomenclature

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1.2 Product Nomenclature

1.3 Ordering Information

The following table is an excerpt from the PPC/PowerCore-6603/4 datasheet. Please ask your local Force Computers representative for the cur-rent PPC/PowerCore-6603/4 data sheet.

Table 4 Nomenclature of the PPC/PowerCore-6603/4

PPC/PowerCore-6xxx/yy-ccc-Llll-z

xxx PowerPC processor type, e.g. 603e

yy DRAM capacity in Mbyte, e.g. 16

ccc Processor clock frequency in MHz, e.g. 120

Llll L2 cache capacity in Kbyte, e.g. L512

z User flash capacity in Mbyte, e.g. 4

Table 5 Excerpt from the data sheet’s ordering information

Product name Description

PPC/PowerCore-…

...6603e/16-120-L0-0 PowerPC 603e, 16-Mbyte DRAM, 120-MHz nominal processor fquency, no L2 cache, and no user flash

...6603e/16-120-L0-4 PowerPC 603e, 16-Mbyte DRAM, 120-MHz nominal processor fquency, no L2 cache, and 4-Mbyte user flash

...6603ev/16-166-L512-0 PowerPC 603ev, 16-Mbyte DRAM, 166-MHz nominal processor quency, 512-Kbyte L2 cache, and no user flash

...6603ev/16-166-L512-4 PowerPC 603ev, 16-Mbyte DRAM, 166-MHz nominal processor quency, 512-Kbyte L2 cache, and 4-Mbyte user flash

...6604e/16-200-L512-0 PowerPC 604e, 16-Mbyte DRAM, 200-MHz nominal processor quency, 512-Kbyte L2 cache, and no user flash

...6604e/16-200-L512-4 PowerPC 604e, 16-Mbyte DRAM, 200-MHz nominal processor quency, 512-Kbyte L2 cache, and 4-Mbyte user flash

…6604e/16-300-L512-4 PowerPC 604e, 16-Mbyte DRAM, 300-MHz nominal processor quency, 512-Kbyte L2 cache, and 4-Mbyte user flash


Ordering Information Introduction

y

in-

PPC/PowerCore-…

...MEM/xx xx indicates the memory module capacity in Mbyte. This memormodule cannot be upgraded by an upper memory module.

...MEM/xxL xx indicates the memory module capacity in Mbyte. L means lowermemory module, i.e. this memory module type can be upgraded by stalling an upper memory module on top of it.

...MEM/xxU xx indicates the memory module capacity in Mbyte. U means uppermemory module.

Accessories PPC/PowerCore-…

…TM Technical Reference Manual for PPC/PowerCore-6603/4 includingPowerBoot Instruction Set.

Table 5 Excerpt from the data sheet’s ordering information (cont.)

Product name Description


Installation Installation Prerequisites and Requirements

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s of

2 Installation

This chapter provides important information for the installation. Beforeinstalling the PPC/PowerCore-6603/4, read section “Safety Notes”page xv.

2.1 Installation Prerequisites and Requirements

Note: Before powering up, check this section for installationprerequisites and requirements, check the consistency of the currentswitch setting (see section 2.3 “Switch Settings” on page 11), ancheck the consistency of the current switch settings on thePPC/SSIO-6603/4 if a PPC/SSIO-6603/4 is installed (sesection 2.13.2 “Switch Settings” on page 27).

2.1.1 Requirements

The installation requires only

• a power supply,

• a fan unit providing an airflow meeting the thermal requirementsthe PPC/PowerCore-6603/4,

• and a VMEbus backplane with P1 and P2 connectors.

Power requirements

PPC/PowerCore-6603/4 provides a limited current at the PMC suppins. The maximum current depends on:

• the CPU type and frequency

• and the installed memory module(s). Typical power requirementthe CPU board are given in the following table:

Table 6 Typical Power Requirements of the CPU Board

CPU board without PMC module or memory module +5V

Power consumption

PPC/PowerCore-6603e/16-120-L0-0 2.6 A 13 W

PPC/PowerCore-6603ev/16-166-L512-0 2.9 A 14.5 W

PPC/PowerCore-6604e/16-200-L512-0 4.3 A 21.5 W


Installation Prerequisites and Requirements Installation

ional

on-

od-

con-

wer

e(s)d-

– Memory Modules

The available system memory may be increased by one or two additmemory module(s).

Caution PPC/PowerCore-6603/4 may be equipped only with EDO DRAMmemory modules qualified by Force Computers. Otherwise theboard or connected components may be damaged.

Out of the comprehensive list of possible configurations the memory cfigurations shown in the following table have been qualified.

The upgrading instructions are shipped together with the memory mules: see the respective Memory Module Installation Guide.

When installing a memory module, you have to consider the power sumption. In this case add

• the power consumption of the CPU board (see table 6 “Typical PoRequirements of the CPU Board” on page 5)

• and the max. power consumption drawn by the memory modul(see table 8 “Max. Power Consumption Values of the Memory Moules”).

PPC/PowerCore-6604e/16-300-L512-4 3.1 A 15.5 W

Table 6 Typical Power Requirements of the CPU Board (cont.)

CPU board without PMC module or memory module +5V

Power consumption

Table 7 Qualified Memory Module Configurations

Total memory module capacity [MByte] PPC/PowerCore-MEM/…

16 16

32 32

64 64L

128 128L

256 128L + 128U



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iner topm ise-

– PMC The values given in the following table are valid for PPC/PowerCo6603/4 without any additional memory module(s).If memory modules are installed, the power consumption value of PMC modules is reduced by the power consumption value of the instamemory module(s).

RS-232 serial interface

The RS-232 serial interface must meet the following values:

– +12 V: 0.1 A (typical)

– –12 V: 0.1 A (typical)

Thermal requirements

The operating temperature is 0°C to +55°C (humidity 5% to 95% non-condensing at +40°C), when operating the PPC/PowerCore-6603/4 systems providing a minimum forced airflow of 300 LFM (linear feet pminute). The airflow is required at the heat sink of the CPU and at theside of the CPU board. The typical operating temperature of the syste0°C to +40°C. The following table summarizes the environmental rquirements of the PPC/PowerCore-6603/4.

Table 8 Max. Power Consumption Values of the Memory Modules

PPC/PowerCore-MEM/… 3.3 V Power consumption

16 0.05 A 0.2 W

32

64L 0.1 A 0.4 W

128L

128L + 128U 0.2 A 0.7 W

Table 9 Maximum Permissible Power Consumption of PMC Modules

CPU board/ frequency

Total maximum power consumption of all PMC modules

if only 3.3 V are used [W]

if 3.3 V and 5 V are used

max. at 3.3 V [W]

max. totalled across 3.3 V and 5 V [W]

603e/120 13.4 13.4 15.0

603ev/166 15.0 15.0 15.0

604e/200 13.0 13.0 13.0

604e/300 15.0 15.0 15.0


Installation Prerequisites and Requirements Installation

he-ntpe it the

2.1.2 Terminal Connection

For the initial power-up, a terminal can be connected to the 9-pinMicroD-Sub connector of the serial port, which is located at the frontpanel (see section 2.6 “Serial I/O Port” on page 15).

2.1.3 Location Overview

The figure 1 “Location Diagram of the PPC/PowerCore-6603/4 (scmatic)” on page 9 highlights the position of the importaPPC/PowerCore-6603/4 components. Depending on the board tymight be that your board does not include all components named inlocation diagram.

Table 10 Environmental Requirements of PPC/PowerCore-6603/4

Operating Non-operating

Temperature 0°C to +55°C –40°C to +85°C

Forced air flow 300 LFM (linear feet per minute) –

Temp. change +/– 0.5°C/min +/– 1°C/min

Rel. humidity 5% to 95% noncondensing at +40°C

5% to 95% noncondensing at +40°C

Altitude –300 m to +3.000 m –300 m to +13.000 m



Figure 1 Location Diagram of the PPC/PowerCore-6603/4 (schematic)

4 LEDs

SERIAL

ABORT

P2 connector P1 connector

E B

Front panelR

U

RESET

PCI-to-VME bridge(Universe II)

SW7

10Base-TPMC 1 PMC 2

RTC/NVRAMbatteryPowerPC-

to-PCIbridge PowerPC

2SerialI/O

L2 cache

Ethernetcontroller

EDO RAM

PCI-to-ISA bridge

PMC slot 1

EDO RAM

SW5

SW6

2 1 4 3

P2 connectorP2 connector P1 connector

User flash User flash

Memorymoduleconnectors

P4

P3

1

Bottom

Top

flash

Boot

PN15 connector (fact. opt.)

PMC slot 2

J36

J40


Automatic Power Up – Voltage Sensor and Watchdog Timer Installation

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2.1.4 Upgrading PPC/PowerCore-6603/4

Memory module To increase the capacity of the available system memory, a memory mod-ule can be installed on PPC/PowerCore-6603/4. If the memory moduledirectly installed on the base board is equipped with memory moduleconnectors, the capacity can additionally be increased by installing a sec-ond (upper) memory module on the first (lower) one. For more informa-tion on the memory module,

• see section 2.1 “Installation Prerequisites and Requirements”page 5

• and the PPC/PowerCore-MEM Installation Guide.

PMC module PPC/PowerCore-6603/4 provides 2 PMC slots. The PMC slots caused to install PMC modules based on the PCI bus architecture. For detailed information on the PMC modules,

• see section 2.1 “Installation Prerequisites and Requirements”page 5

• and section 2.8 “PMC Slots” on page 16.

2.2 Automatic Power Up – Voltage Sensor and Watchdog Timer

Voltage sensors If the voltage levels drop below the voltage values given in the VMEbusspecification or below the processor core low-voltage level respectively,the voltage sensors generate automatically a reset of the CPU board andproceed with a normal booting procedure.

Watchdog timer Per factory default the watchdog timer is disabled. If the watchdog timeris enabled, it generates a non-maskable interrupt (NMI) followed by a re-set when it is not retriggered by the software. The watchdog timer can beenabled by SW5-1 (see “SW5-1” on page 11).


Installation Switch Settings

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2.3 Switch Settings

The following table lists the functions and the default settings of allswitches shown in figure 1 “Location Diagram of the PPC/PowerCo6603/4 (schematic)” on page 9. The switches are located on the boside of the board. For switching it is not required to remove any modu

Note: Before powering up the board check the current switchsettings for consistency.

Note: SW7-1, SW7-2, and SW7-3 will only be read on a power up.

Note: Do not switch during operation.

Table 11 Switch Settings

Name and default setting Description

SW5-1OFF

Watchdog timer OFF = Timer disabledON = Timer enabled

SW5-2OFF

Watchdog time (±±±±8ms)OFF = NMI: 39 ms, RESET: 134 msON = NMI: 363 ms, RESET: 1.66 s

SW5-3OFF

VMEbus SYSRESET inputOFF = SYSRESET generates power up

resetON = SYSRESET does not generate

power up reset

SW5-4OFF

Reserved

ON

1234


Switch Settings Installation

SW6-1OFF

RESET key OFF = RESET key enabledON = RESET key disabled

SW6-2OFF

ABORT key OFF = ABORT key enabledON = ABORT key disabled

SW6-3OFF

User flash write protectionOFF = writing enabledON = write-protected

SW6-4OFF

Boot flash write protectionOFF = write-protectedON = writing enabled

SW7-1OFF

VMEbus slot 1 auto-detectionOFF = enabledON = disabled (also called manual mode)

SW7-2OFF

System controller (only available if SW7-1 = ON)OFF = disabledON = enabled

SW7-3OFF

Power up detection levelOFF = conforms to ANSI/VITA 1-1994ON = below ANSI/VITA 1-1994 (Thishas the advantage that sudden voltagesags do not generate a reset.)

SW7-4OFF

VMEbus SYSRESET outputOFF = enabledON = disabled

Table 11 Switch Settings (cont.)


ON

1234

ON

1234


Installation Front Panel

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2.4 Front Panel

The features of the front panel are described in the following sections.For a location diagram see figure 1 “Location Diagram of the PPC/PerCore-6603/4 (schematic)” on page 9.

Table 12 Front Panel Features

Device Description

RESET Mechanical reset key: When enabled and toggledinstantaneously affects the CPU board by generatingreset. Depending on SW7-4 the reset generatesVMEbus SYSRESET (see “SW7-4” on page 12).A reset of all on-board I/O devices and the CPU iperformed when the reset key is pushed to the actiposition. RESET is held active until the key is back inthe inactive position, however at least 200 ms arguaranteed by a local timer. Power fail (below approximately 4.7 V) and power up – both lasting aminimum 200 ms to 300 ms – also force a reset tstart the CPU board.For information on enabling the key, see “SW6-1” onpage 12.

ABORT Mechanical abort key: When enabled and toggled instantaneously affects the CPU board by generatinan interrupt request (NMI) via the PCI-to-ISA bridge.This allows to implement an abort of the current program, to trigger a self-test or to start a maintenancprogram.For information on enabling the key, see “SW6-2” onpage 12.

LED R RUN/RESET LED indicating the board status:

• green: normal operation

• red: reset is active

LED B VMEbus master and SYSFAIL LED:

• green: when the CPU board accesses the VMEbas VMEbus master

• red: when the CPU board drives SYSFAIL on theVMEbus

• off: otherwise


PPC/PowerCore-6603/4 Parameters and Timers – CIO Installation

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2.5 PPC/PowerCore-6603/4 Parameters and Timers – CIO

Configurable parameters

Via the CIO device several parameters can be configured or read, respec-tively: programming voltage VPP, user flash device select, user flash pageselect, VMEbus SYSRESET out, watchdog trigger, user LED control,ID-ROM (serial EEPROM), PCI busmode signals, and the three 16-bittimers.

Timers Three 16-bit timers with a resolution of approximately 500 ns are avail-able.

LED E Ethernet LED:

• green: transmit data

• red: receive data

• off: no traffic

LED U User LED: Software programmable by the CIOcounter/timer and parallel I/O unit. Bits 0 and 1 oport C are used. Possible status: green, red, or off.

10Base-TETHERNET

An 8-pin RJ45 connector for 10Base-T Ethernet interface.

SERIALPORT

A 9-pin MicroD-Sub connector for serial interface(see section 2.6 “Serial I/O Port” on page 15).

Device: CIO

Frequency 4.125 MHz or 3.75 MHz

Accessible from PowerPC processor

Access base address ISA: 0000.030016PCI: 0000.030016CPU: FE00.030016

Port width 8 bit

Interrupt request Priority level 3 (software reprogrammable, IRQ8#)

Table 12 Front Panel Features (cont.)

Device Description


Installation Serial I/O Port

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inout

2.6 Serial I/O Port

Connector availability

The RS-232 serial I/O port is available via a 9-pin MicroD-Sub connectorat the front panel. The serial port with 4 lines is also available on the5-row VMEbus P2 connector (factory option) (see section 2.11 “VMEbP2 Connector Pinout” on page 20).

Pinout For the front-panel pinout of the serial lines, see below. For the P2 psee section 2.11 “VMEbus P2 Connector Pinout” on page 20.

Port setup • RS-232 asynchronous communication

• 9600 baud, 8 data bits, 1 stop bit, no parity

• No handshake protocol used by default.

Device: Serial I/O port

Frequency 1.8432 MHz


Access base address ISA: 0000.03F816PCI: 0000.03F816CPU: FE00.03F816

Port width 8 bit

Interrupt request Priority level 12 (software repro-grammable, IRQ4)

Table 13 Pinout of the Front-Panel Serial I/O Port for RS-232

Pin Signal

1 DCD (Data Carrier Detect, input)

2 RXD (Receive Data, input)

3 TXD (Transmit Data, output)

4 DTR (Data Terminal Ready, output)

5 GND (Ground)

6 DSR (Data Set Ready, input)

7 RTS (Request to Send, output)

8 CTS (Clear to Send, input)

9 GND (Ground)

1

5

6

9

9-pin MicroD-Sub


IDE Installation

“In-

2.7 IDE

The PCI-to-ISA bridge provides two fast IDE interfaces which are routedto the 5-row VMEbus P2 connector (factory option).

The PCI bus interface is 32-bit wide and able to transfer data via the in-ternal DMA controller.

The PCI-to-ISA bridge integrates a high performance interface betweenPCI and IDE. This interface is capable of accelerating PIO data transfersand to act as PCI bus master on behalf of an IDE DMA slave device.First, the slave device declares that it wants to be served by the PCI-to-ISA bridge master by requesting DMA.

2.8 PMC Slots

PPC/PowerCore-6603/4 provides 2 PMC slots for installing PMC mod-ules compliant with IEEE P1386 ("Draft Standard Physical and Environ-mental Layers for PCI Mezzanine Cards: PMC"). The PCI bus, a highspeed local bus compliant with Rev. 2.1., connects different high speedI/O cards with PPC/PowerCore-6603/4. Both PMC slots support 32-bitdata bus width with a maximum frequency of 33 MHz.

Power of the PMC modules

For information on the power of the PMC modules, see section 2.1 stallation Prerequisites and Requirements” on page 5.

Device: PCI-to-ISA bridge

Frequency PCI bus frequency of 33 MHz or30 MHz


Access base address not defined

Port width 32 bit

Interrupt request Priority level 9 (IRQ14) Priority level 10 (IRQ15) 1)

1. In the PCI-to-ISA bridge MIRQ0 has to be routed to IRQ15 via therespective operating system.


Installation PMC Slots

2.8.1 PMC Voltage Keys

The PCI bus uses a 5-V voltage to signal bus levels. The voltage keysprevent 3.3V PMC cards from being plugged into the PMC slots.

2.8.2 Connector Configuration

The 32-bit PCI bus requires 2 PMC connectors. The 3rd PMC connectorconnects additional user I/O signals of PMC slot 1 and PMC slot 2 withthe VMEbus P2 connector rows A and C.

PMC slot 1 connectors

• for the PCI bus: J11 and J12

• for 64 user I/O signals: J14

PMC slot 2 connectors

• for the PCI bus: J21 and J22

• for 32 user I/O signals: J24

Caution PMC slot 1 has 64 user I/O signals, PMC slot 2 has 32 user I/O sig-nals. The 32 user I/O signals of PMC slot 2 are connected with 32user I/O signals of PMC slot 1. Both, the 64 user I/O signals of PMCslot 1 and the 32 user I/O signals of PMC slot 2, are routed to the 64user I/O pins of the VMEbus P2 connector (see figure 3 “3- or 5-rowP2 Connector Pinout, Row A and C” on page 20). This is compliantwith the “Draft Standard for a Common Mezzanine Card Family:CMC”, P1386/Draft 2.0. Do not plug in 2 PMC cards both driving the same I/O lines (seePMC cards’ manuals). Otherwise the PMC cards may be damaged.

2.8.3 ISA Connector

The connector PN15 is a factory option and makes a set of ISA bus sig-nals available including 7-wire AUI signals.

The following figure shows the signals available on the ISA connector.


Ethernet Interface Installation

Figure 2 PN15 Connector Pinout

2.9 Ethernet Interface

The Ethernet 10Base-T interface is available at the front panel via an8-pin RJ45 connector.

Device: Ethernet controller

Frequency PCI bus frequency: 33 MHz or30 MHz


Access base address PCI: 0080.000016CPU: FE80.000016

Port width 32 bit

Interrupt request Priority level 5 (INTA#, IRQ10)

SYSCLKGNDSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9

SA10N.C.

IOCHRDYAEN

TCZEROWS#

IOR#IOW#

MRIDENT

GNDRCLK

RXDRXENCLSN

N.C.N.C.

GNDUSB-P0-MUSB-P0-P

SD0SD1SD2SD3SD4SD5SD6SD7BALEDACK0#DREQ0DACK1#DREQ1DACK2#DREQ2N.C.IRQ1IRQ3IRQ4IRQ5IRQ6IRQ7IRQ12+12VTCLKTXDTXENGNDUSB-CLKGNDUSB-P1-MUSB-P1-P

1 2

9 10

19 20

29 30

39 40

49 50

59 60

63 64


Installation VMEbus Interface – Universe II

Note: If a PPC/SSIO-6603/4 is installed, the 10Base-T Ethernetinterface and the Ethernet LED on the front panel of thePPC/PowerCore-6603/4 base board are disabled.

The PCI bus interface is 32-bit wide and able to transfer data via the on-chip DMA with programmable PCI burst size.The following table shows the pinout of the factory default Ethernet con-nector.

2.10 VMEbus Interface – Universe II

Universe II is a PCI-to-VME interface which is compliant withANSI/VITA 1-1994 and able to transfer data via the programmable DMA

Table 14 8-pin RJ45 Connector

Pin Signal

1 TXP

2 TXM

3 RXP

4 N.C.

5 N.C.

6 RXM

7 N.C.

8 N.C.

Device: Universe II

Frequency PCI bus frequency: 33 MHz or30 MHz

Accessible from PowerPC processor and VMEbusmasters

Access base address PCI: 0081.000016CPU: FE81.000016

PCI bus width 32 bit

Interrupt request Priority level 6 (INTB#, IRQ11)

1

8


VMEbus P2 Connector Pinout Installation

Aector

ndop-

controller with linked list support. Furthermore, it provides full VMEbussystem controller functionality and a PCI bus interface of up to 33 MHz.

2.11 VMEbus P2 Connector Pinout

The following two figures show the signals available on the VMEbus P2.The signals shown in figure 3 “3- or 5-row P2 Connector Pinout, Rowand C” on page 20 are available at a 3-row and at a 5-row P2 conn(see section 2.8.2 “Connector Configuration” on page 17). The signals shown in figure 4 “5-Row P2 Connector Pinout, Row Z aD” on page 21 are available only at a 5-row P2 connector (factory tion).

Figure 3 3- or 5-row P2 Connector Pinout, Row A and C

= IO PMC1 – 2= IO PMC1 – 4= IO PMC1 – 6= IO PMC1 – 8

= IO PMC1 – 10= IO PMC1 – 12= IO PMC1 – 14= IO PMC1 – 16= IO PMC1 – 18= IO PMC1 – 20= IO PMC1 – 22= IO PMC1 – 24= IO PMC1 – 26= IO PMC1 – 28= IO PMC1 – 30= IO PMC1 – 32

IO PMC1 – 34IO PMC1 – 36IO PMC1 – 38IO PMC1 – 40IO PMC1 – 42IO PMC1 – 44IO PMC1 – 46IO PMC1 – 48IO PMC1 – 50IO PMC1 – 52IO PMC1 – 54IO PMC1 – 56IO PMC1 – 58IO PMC1 – 60IO PMC1 – 62IO PMC1 – 64

CAIO PMC1 – 1 = IO PMC1 – 3 = IO PMC1 – 5 = IO PMC1 – 7 = IO PMC1 – 9 = IO PMC1 – 11 = IO PMC1 – 13 = IO PMC1 – 15 = IO PMC1 – 17 = IO PMC1 – 19 = IO PMC1 – 21 = IO PMC1 – 23 = IO PMC1 – 25 = IO PMC1 – 27 = IO PMC1 – 29 = IO PMC1 – 31 = IO PMC1 – 33IO PMC1 – 35IO PMC1 – 37IO PMC1 – 39IO PMC1 – 41IO PMC1 – 43IO PMC1 – 45IO PMC1 – 47IO PMC1 – 49IO PMC1 – 51IO PMC1 – 53IO PMC1 – 55IO PMC1 – 57IO PMC1 – 59IO PMC1 – 61IO PMC1 – 63

1

5

10

15

20

25

30

32




Installation VMEbus P2 Connector Pinout

Figure 4 5-Row P2 Connector Pinout, Row Z and D

RESETGND

Serial TXDGND

Serial RXDGND

Serial RTSGND

Serial CTSGND

ReservedGND

ReservedGND

ReservedGNDN.C.

GNDDDRQ 1

GNDDDAK 1 #

GNDMIRQGND

CS3S#GND

CS1S#GND

CS1P#GND

CS1P#GND

DZN.C.N.C.IDE Data 7IDE Data 8IDE Data 6IDE Data 9IDE Data 5IDE Data 10IDE Data 4IDE Data 11IDE Data 3IDE Data 12IDE Data 2IDE Data 13IDE Data 1IDE Data 14IDE Data 0IDE Data 15DDRQ 0DIOW#DIOR#IORDYIDEBALEDDAK 0 #IRQ 14IOCS16IDE DA 1IDE DA 0IDE DA 2N.C.GNDN.C.

1

5

10

15

20

25

30

32


Testing the CPU Board Using PowerBoot Installation

2.12 Testing the CPU Board Using PowerBoot

PowerBoot is firmware providing some basic test and debug commands.It is stored in the on-board boot PROM.

Booting up PowerBoot

PowerBoot automatically starts during power up or reset. After the suc-cessful pass of the self-initialization routine, the following message or asimilar one will appear on the screen:Init serial at address: 0xFE0003F8Init CIO at address: 0xFE000300Init Ethernet Controller at address: 0xFE800000Init UNIVERSE VMEbus device at address: 0xFE810000PowerCore is -NOT- VMEbus System Controller (SYSCON=0)Found CPU603ev, PVR=00070201, CPU clock: 166MHz, Bus clock: 66MHzDRAM EDO mode enabled, DRAM ECC mode disabledOnboard DRAM : 16MB, 0x00000000..0x00FFFFFFInit DRAM Module 1: noneInit DRAM Module 2: noneInit DTLB/ITLB for block translation, enable MMUInit L1-IcacheInit L1-DcacheInit L2-Cache, found 2 Banks, 512 kByte cacheInit exception vectors starting at address: 0x00000100Read NVRAM...identify boardEthernet: 00:80:42:0E:02:1DPMC1/2: no auto mapping setup

<<PowerBoot Software V1.02 for PowerPC>>

PowerBoot> _

System controller

If the board is configured as system controller, the user LED at the frontpanel turns green.

Starting a test after booting

To test the CPU board for correct operation enter probepci.Probepci does not provide a full-featured power-on self-test. Howev-


Installation Testing the CPU Board Using PowerBoot

er, it tests some I/O devices and scans the PCI bus for participants. De-pending on the board configuration, the following message will appear:

PowerBoot> probepci Probing PCIbus at 0x80000000Device ID = 0x0002; Vendor ID = 0x1057; Status = 0x2080; Command = 0x0006; Base Class= 0x06; Sub Class = 0x00; Prg. Inter= 0x00; Rev. ID = 0x20; BIST = 0x00; Header Typ= 0x00; Latency Ti= 0x00; Cache Line=0x08;base addr0= 0x00000000; Max Lat = 0x00; Min Gnt = 0x00; IRQ Pin = 0x00; IRQ Line = 0x00; Found PCI device: Motorola MPC106 PowerPC PCI bridge

Probing PCIbus at 0x8000C000Device ID = 0x0000; Vendor ID = 0x10E3; Status = 0x0200; Command = 0x0007; Base Class= 0x06; Sub Class = 0x80; Prg. Inter= 0x00; Rev. ID = 0x00; BIST = 0x00; Header Typ= 0x80; Latency Ti= 0xF8; Cache Line= 0x00; base addr0= 0x00810001; Max Lat = 0x00; Min Gnt = 0x03; IRQ Pin = 0x01; IRQ Line = 0x00; Found PCI device: Tundra UNIVERSE VMEbus interface

Probing PCIbus at 0x8000D000Device ID = 0x122E; Vendor ID = 0x8086; Status = 0x0280; Command = 0x0007; Base Class= 0x06; Sub Class = 0x01; Prg. Inter= 0x00; Rev. ID = 0x02; BIST = 0x00; Header Typ= 0x80; Latency Ti= 0x00; Cache Line= 0x00; base addr0= 0x00000000; Max Lat = 0x00; Min Gnt = 0x00; IRQ Pin = 0x00; IRQ Line = 0x00; Found PCI device: 82371FB PCI ISA (PIIX) function 0

Probing PCIbus at 0x8000D100Device ID = 0x1230; Vendor ID = 0x8086; Status = 0x0280; Command = 0x0000; Base Class= 0x01; Sub Class = 0x01; Prg. Inter= 0x80; Rev. ID = 0x02; BIST = 0x00; Header Typ= 0x00; Latency Ti= 0x00; Cache Line= 0x00; base addr0= 0x00000000; Max Lat = 0x00; Min Gnt = 0x00; IRQ Pin = 0x00; IRQ Line = 0x00; Found PCI device: 82371FB IDE (PIIX) function 1

Probing PCIbus at 0x8000D800Device ID = 0x0009; Vendor ID = 0x1011; Status = 0x0280; Command = 0x0007; Base Class= 0x02; Sub Class = 0x00; Prg. Inter= 0x00; Rev. ID = 0x12; BIST = 0x00; Header Typ= 0x00; Latency Ti= 0x7F; Cache Line= 0x00; base addr0= 0x00800001; Max Lat = 0x00; Min Gnt = 0x00; IRQ Pin = 0x01; IRQ Line = 0x88; Found PCI device: DEC Chip 21140A Fast Ethernet LAN

Probing PCIbus at 0x8000F800PowerBoot>


Testing the CPU Board Using PowerBoot Installation


PPC/SSIO-6603/4

sites

the

t

2.13 PPC/SSIO-6603/4

This section describes how to install the PPC/PowerCore-6603/4 into aVMEbus system. The PPC/SSIO-6603/4 is maintenance free. For generalsafety notes and installation prerequisites and requirements, see section 1“Safety Notes” on page 1 and see section 2.1 “Installation Prerequiand Requirements” on page 5.

Interfaces of the PPC/SSIO-6603/4

The PPC/SSIO-6603/4 provides the following interfaces available viaVME P2 connector of the PPC/PowerCore-6603/4 base board:

• 4 serial interfaces,

• a SCSI interface,

• and an AUI Ethernet interface.

Note: Before powering up the base board check the consistency ofthe current switch settings on the PPC/SSIO-6603/4, seesection 2.13.2 “Switch Settings” on page 27. With an installedPPC/SSIO-6603/4 the 10Base-T Ethernet interface and the EtherneLED on the front panel of the PPC/PowerCore-6603/4 base board aredisabled.

Power consumption

The PPC/SSIO-6603/4 requires 450 mA at 5 V. If a device is connectedto the Ethernet interface, the required current can rise up to 1 A.

Accessory kit For accessing the interfaces of the PPC/SSIO-6603/4 via standard I/Oconnectors the PPC/PowerCore-6xxx-SSIO/232-AccKit is required. Theaccessory kit contains the IOBP-SSIO/232 rear I/O board with cables andis available as a separate price list item from Force Computers.


PPC/SSIO-6603/4

onpo-

2.13.1 Location Overview

The figure 5 “Location diagram of the PPC/SSIO-6603/4 (schematic)”page 26 highlights the position of important PPC/SSIO-6603/4 comnents.

Figure 5 Location diagram of the PPC/SSIO-6603/4 (schematic)

Ext

ende

d IS

A c

on.

PC

Ibus

con

nect

or

I/O

con

nect

orP

CIb

us c

onne

ctor

SCSI controller

SerialI/O

EthernetAUI

SerialI/O

SerialI/O

SerialI/O

SW 4

Bottom

Top


PPC/SSIO-6603/4

ca-Forthe

2.13.2 Switch Settings

The following table lists the functions and the default settings of allswitches of the PPC/SSIO-6603/4, for their location see figure 5 “Lotion diagram of the PPC/SSIO-6603/4 (schematic)” on page 26. switching it is not required to remove the PPC/SSIO-6603/4 from base board. Do not switch during operation.

Table 15 Switch settings


SW4-1OFF

SCSI termination(Data bits: D0…D7)OFF = Termination enabledON = Termination disabled

SW4-2OFF

Wide SCSI termination(Data bits: D8…D15)OFF = Termination enabledON = Termination disabled

SW4-3OFF

Reserved

SW4-4OFF

Reserved

ON

1234


PPC/SSIO-6603/4

row

Texas

2.13.3 Serial I/O Ports

The RS-232 serial I/O ports are available via P2 connector of the baseboard. For the base board’s P2 connector pinout, see figure 7 “3- or 5-P2 connector pinout of the base board, row A and C” on page 30.

Default port settings

• RS-232 asynchronous communication

• 9600 baud, 8 data bits, 1 stop bit, no parity

• No handshake protocol used

Data sheet For more information on the serial I/Os, see the data sheets of theInstruments TL16C550C serial I/Os on the following website:http://www.ti.com

Device: Serial I/O

Frequency 1.8432 MHz

Access base address Port 1: ISA:PCI:CPU:

0000.03E8160000.03E816FE00.03E816

Port 2: ISA:PCI:CPU:

0000.02E8160000.02E816FE00.02E816


0000.03D8160000.03D816FE00.03D816


0000.02D8160000.02D816FE00.02D816

Port width 8 bit

Interrupt request Port 1:Port 2:Port 3:Port 4:

IRQ6IRQ6IRQ12IRQ12


PPC/SSIO-6603/4

the

dard)p to

2.13.4 SCSI

SCSI is available via P2 connector of the base board. For the base board’sP2 connector pinout, see figure 7 “3- or 5-row P2 connector pinout ofbase board, row A and C” on page 30.

Features • Ultra SCSI technology (Fast-20: extension of the SCSI-3 stanperforms wide high speed SCSI bus synchronous transfers u40 MB/s and 14-MB/s asynchronous transfers.

• Full SCSI-2 capabilities are provided.

• Full software compatible to SYM53C825.

Note: Enable SCSI termination at both ends of the bus (SCSI device#1 and SCSI device #n), see figure below. All other SCSI devicesmust not be terminated. For information on the respective switchsettings, see table 15 “Switch settings” on page 27.

Figure 6 SCSI termination

Data sheet For more information on the SCSI controller, see the data sheets of theSymbios SYM53C875 SCSI controller on the following website: http://www.symbios.com

Device: SCSI controller

Frequency 40 MHz SCSI clock

Port width 8 or 16 bit (SCSI or Wide SCSI)

Interrupt request INTA

SCSI bus

SCSIdevice #1

SCSIdevice #2

SCSIdevice #3

SCSIdevice #n…


PPC/SSIO-6603/4

row

e theh is

2.13.5 Ethernet AUI Interface

The Ethernet AUI signals are available via the P2 connector of the baseboard. For the base board’s P2 connector pinout, see figure 7 “3- or 5-P2 connector pinout of the base board, row A and C” on page 30.

Data sheet For more information on the Ethernet Serial Interface Adapter, sedata sheets of the AMD Am7992B Ethernet Interface Adapter whicavailable on the following website: http://www.amd.com

2.13.6 VMEbus P2 Connector Pinout of the Base Board

Figure 7 3- or 5-row P2 connector pinout of the base board, row A and C

SCSI_D<0>SCSI_D<1>SCSI_D<2>SCSI_D<3>SCSI_D<4>SCSI_D<5>SCSI_D<6>SCSI_D<7>

SCSI_DP<0>SCSI_ATNSCSI_BSYSCSI_ACKSCSI_RST

SCSI_MSGSCSI_SELSCSI_CD

SCSI_REQSCSI_IO

SRL_PMC_3_TXDSRL_PMC_3_RXDSRL_PMC_3_RTSSRL_PMC_3_CTSSRL_PMC_3_DTRSRL_PMC_3_DCDSRL_PMC_4_TXDSRL_PMC_4_RXDSRL_PMC_4_RTS

ReservedSRL_PMC_4_CTSSRL_PMC_4_DTRSRL_PMC_4_DCD

Reserved

CAETH_COL-ETH_COL+ETH_TRA-ETH_TRA+ETH_REC-ETH_REC+ETH_PowerSCSI_DP<1>SCSI_D<8>SCSI_D<9>SCSI_D<10>SCSI_D<11>SCSI_D<12>SCSI_D<13>SCSI_D<14>SCSI_D<15>SCSI_TermPowerSCSI_WideTermPowerReservedReservedReservedGNDSRL_PMC_1_TXDSRL_PMC_1_RXDSRL_PMC_1_RTSSRL_PMC_1_CTSSRL_PMC_2_TXDSRL_PMC_2_RXDSRL_PMC_2_RTSSRL_PMC_2_CTSSRL_PMC_2_DTRSRL_PMC_2_DCD

1

5

10

15

20

25

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32


IOBP-SSIO/232

)

the

2.14 IOBP-SSIO/232

As a separate price list item Force Computers offers a PPC/PowerCore-6xxx-SSIO/232-AccKit which includes an IOBP-SSIO/232 rear I/Oboard with cables and is specially designed for the PowerCore-6603/4-SSIO. Plug the IOBP-SSIO/232 only into the VMEbus backplane fromits rear to the P2 connector of the base board.

Connectors of the IOBP-SSIO/232

The IOBP-SSIO/232 provides the following connectors:

• 4 RS-232 serial connectors

• 1 SCSI connector

• 1 Wide SCSI shielded connector

• 1 Ethernet AUI connector

• a 50-pin socket for PMC2 signals (only available as factory option

Note: Use only the SCSI or Wide SCSI connector, not both of them.For connecting the serial interface to a modem host, an RS-232 NullModem Adapter is required.

The following schematic location diagram highlights the position of IOBP-SSIO/232 components.

Figure 8 IOBP-SSIO/232 (schematic)

The pinouts of the connectors are shown in the following tables.

P2 connector

PMC2 connectoronly available as factory option

Serial 1 connector (SRL2)




SCSI connector

Wide SCSI connector (WIDE) AUI Ethernet (ETH)


IOBP-SSIO/232

Table 16 Serial connectors pinout

Signal Pin Connector Pin Signal

n.c. 1 2 n.c.

SRL_TXD 3 4 n.c.

SRL_RXD 5 6 n.c.

SRL_RTS 7 8 Reserved

SRL_CTS 9 10 n.c.

n.c. 11 12 n.c.

GND 13 14 SRL_DTR1)

SRL_DCD1) 15 16 n.c.

n.c. 17 18 n.c.

n.c. 19 20 n.c.

n.c. 21 22 Reserved

n.c. 23 24 n.c.

n.c. 25 26 Shield GND

1. SRL_DTR signal and SRL_DCD signal are not available on the Serial 1 connector (SRL2)

25 26

21

Table 17 Ethernet connector pinout


GND 1 2 ETH_COL-

ETH_COL+ 3 4 ETH_TRA-

ETH_TRA+ 5 6 GND

GND 7 8 ETH_REC-

ETH_REC+ 9 10 ETH_Power

GND 11 12 GND

n.c. 13 14 n.c.

GND 15 16 Shield GND

15 16

21


IOBP-SSIO/232

Table 18 SCSI connector pinout


GND 1 2 SCSI_D<0>

GND 3 4 SCSI_D<1>

GND 5 6 SCSI_D<2>

GND 7 8 SCSI_D<3>

GND 9 10 SCSI_D<4>

GND 11 12 SCSI_D<5>

GND 13 14 SCSI_D<6>

GND 15 16 SCSI_D<7>

GND 17 18 SCSI_DP<0>

GND 19 20 GND

GND 21 22 GND

n.c. 23 24 n.c.

n.c. 25 26 SCSI_TermPower

n.c. 27 28 n.c.

GND 29 30 GND

GND 31 32 SCSI_ATN

GND 33 34 GND

GND 35 36 SCSI_BSY

GND 37 38 SCSI_ACK

GND 39 40 SCSI_RST

GND 41 42 SCSI_MSG

GND 43 44 SCSI_SEL

GND 45 46 SCSI_CD

GND 47 48 SCSI_REQ

GND 49 50 SCSI_IO

49 50

21


IOBP-SSIO/232

Table 19 Wide SCSI connector pinout


GND 1 35 SCSI_D<12>

GND 2 36 SCSI_D<13>

n.c. 3 37 SCSI_D<14>

GND 4 38 SCSI_D<15>

GND 5 39 SCSI_DP<1>

GND 6 40 SCSI_D<0>

GND 7 41 SCSI_D<1>

GND 8 42 SCSI_D<2>

GND 9 43 SCSI_D<3>

GND 10 44 SCSI_D<4>

GND 11 45 SCSI_D<5>

GND 12 46 SCSI_D<6>

GND 13 47 SCSI_D<7>

GND 14 48 SCSI_DP<0>

GND 15 49 GND

GND 16 50 n.c.

SCSI_WideTermPower

17 51 SCSI_TermPower

SCSI_WideTermPower

18 52 SCSI_TermPower

n.c. 19 53 n.c.

GND 20 54 GND

GND 21 55 SCSI_ATN

GND 22 56 GND

GND 23 57 SCSI_BSY

GND 24 58 SCSI_ACK

GND 25 59 SCSI_RST

GND 26 60 SCSI_MSG

GND 27 61 SCSI_SEL

GND 28 62 SCSI_CD

GND 29 63 SCSI_REQ

GND 30 64 SCSI_IO

GND 31 65 SCSI_D<8>

GND 32 66 SCSI_D<9>

GND 33 67 SCSI_D<10>

GND 34 68 SCSI_D<11>

1 35

34 68


Hardware

,

–

DO

–

13.2

P2

rt –

ee

O

on

on

user-

3 Hardware

PPC/PowerCore-6603/4 is a high performance single-slot PowerPCbased platform providing a 64-bit VMEbus interface. The VMEbus inter-face device is directly connected to the PCI bus. The board is based on:

• the PowerPC CPU (see section 3.3 “PowerPC CPU” on page 46)

• two PMC slots,

• and on the VMEbus (see section 3.10 “VMEbus InterfaceUniverse II” on page 64).

Described features

PPC/PowerCore-6603/4 provides

• on-board shared EDO RAM (see section 3.6 “System Memory (ERAM)” on page 51)

• boot flash (see section 3.7 “Boot Flash” on page 57)

• user flash (see section 3.8 “User Flash” on page 60)

• VMEbus interface (see section 3.10 “VMEbus Interface Universe II” on page 64)

• Ethernet interface available at the front panel (see section 3.“Ethernet Interface Adapter” on page 76)

• 2 PMC slots with user I/Os available at 3-row or 5-row VMEbus connector (see section 3.18 “PMC Slots” on page 85)

• RS-232 compatible serial I/O port (see section 3.17 “Serial I/O PoSCC” on page 84)

• on-board real-time clock with on-board battery backup (ssection 3.15 “Real-Time Clock / Non-Volatile RAM” on page 80)

• watchdog timer (see section 3.5 “Watchdog Timer” on page 49)

Factory options The following factory options are available:

• capacity of EDO RAM (see section 3.6 “System Memory (EDRAM)” on page 51)

• capacity of additional user flash (see section 3.8 “User Flash”page 60)

• capacity of additional L2 cache (see section 3.4 “L2 Cache” page 48)

• 2 IDE interfaces and RS-232 interface, available at 5-row VMEbP2 connector (see section 3.14 “PCI-to-ISA Bridge and IDE Intfaces” on page 77)


Hardware

ernetl porterve

om

ol-us

-to-

on

DMA controllers The following devices are collectively referred to as DMA controllers ofPPC/PowerCore-6603/4 because they themselves provide an on-chipDMA controller:

• Universe II

• PCI-to-ISA bridge

• Ethernet controller

Front panel The front panel of PPC/PowerCore-6603/4 provides a 10Base-T Ethport (see section 3.13 “Ethernet Interface” on page 75) and one seria(see section 3.17 “Serial I/O Port – SCC” on page 84). These ports sas console port, for download and for data communication.

Interfaces on VMEbus P2 connector

• On the 3-row and 5-row VMEbus P2 connector the I/O signals frthe PMC slots are available.

• On the 5-row VMEbus P2 connector, which is factory option, the flowing additional interfaces are available (see section 2.10 “VMEbInterface – Universe II” on page 19):

– primary and secondary IDE interface (see section 3.14 “PCIISA Bridge and IDE Interfaces” on page 77)

– serial I/O port (see section 3.17 “Serial I/O Port – SCC” page 84)


Hardware

Figure 9 PPC/PowerCore-6603/4 block diagram

PC87306VULSuperIO

VMEbus

Front

panel

PCI bus

RS-232

PMC I/O

PMC I/O

IDE and RS-232

ISA bus

PowerPC bus

PMC user I/O

PowerPC603e/603ev/

604e

L2 cacheup to 1 Mbyte

(factory option)

Boot flashup to

1 Mbyte

User flashup to 8 Mbyte

(factory option)

Main memory

EDO RAM 16 Mbyte

Ethernet controller

CIO

RTC/NVRAM

Serial I/O

PMC slot 2PCI mezzanine card slot

PMC slot 1PCI mezzanine card slot

(factory option: ISA bus extension)

PowerPC-to- PCI bridge

Memory module

(factory option)

Universe II

PCI-to-ISA bridge

Serial EEPROM

IDE

10Base-T


Hardware

Bus overview The following table gives an overview of the different buses, their bus-modes, and the connected devices.

Bus frequencies The frequencies of the buses depend on the CPU type. The following ta-ble shows the frequencies of the different buses:

Table 20 Buses, busmodes, and connected devices

Bus Busmode Connected devices

PPC bus Big endian mode PowerPC CPUL2 cacheEDO RAMBoot flashUser flashPPC-to-PCI bridge

PCI bus Little endian mode Ethernet controllerPMC slots 1 and 2PCI-to-VME bridge (Universe II)PPC-to-PCI bridgePCI-to-ISA bridge

VMEbus Big endian mode ConnectorsPCI-to-VME bridge (Universe II)

ISA bus Little endian mode CIORTC/NVRAMSerial I/ODCCRPCI-to-ISA bridge

Table 21 Bus frequencies

CPU type

Bus frequency [MHz]

ISA PCI PPC

PowerPC 603e 7.5 30 60

PowerPC 603ev 8.25 33 66

PowerPC 604e 8.25 33 66


Hardware PPC/PowerCore-6603/4 Address Map

sses

ory

ace

ation

ical

ysi-

3.1 PPC/PowerCore-6603/4 Address Map

PPC/PowerCore-6603/4 provides a CHRP compliant address map. Thefollowing tables show the address map of PPC/PowerCore-6603/4:

• PPC/PowerCore-6603/4 memory map seen from the CPU (addreon the processor bus),

• PPC/PowerCore-6603/4 memory map seen from the PCI (memspace addresses on the PCI bus),

• PPC/PowerCore-6603/4 I/O map seen from the PCI (I/O spaddresses on the PCI bus),

• PPC/PowerCore-6603/4 configuration base addresses (configuraddresses for the on-board PCI devices),

• PPC/PowerCore-6603/4 ISA bus ports seen from the CPU (physaddresses for the on-board ISA devices),

• PPC/PowerCore-6603/4 PCI I/O devices seen from the CPU (phcal addresses for the on-board PCI I/O devices).

Note: Before erasing or programming the boot flash ensure that youdo not destroy the Force Computers PowerBoot boot image andmake a copy of the boot flash device 1 in socket J40.Always remember the following access rule for any reserved bits inany PPC/PowerCore-6603/4 register: written as 0 read as undefined.All registers must be written or read using the data path widthdocumented for the respective register.Always remember that in descriptions of data path widths byterefers to 8 bit, half-word to 16 bit, word to 32 bit, and long-word to64 bit.


PPC/PowerCore-6603/4 Address Map Hardware

Table 22 PPC/PowerCore-6603/4 memory map seen from the CPU

Address on the PowerPC bus Device

Accessible bus Cache Bus

width[bit]PCI VME L1 L2

0000.000016 … 3FFF.FFFF 16

System memory space consisting of:

• on-board system memory (EDORAM),

• additional memory module

The on-board system memory and thememory module space are contiguous,the end address depends on the memo-ry capacity.

Y Y Y Y [64]

4000.000016 … 7FFF.FFFF 16

Reserved – – – – –

8000.000016… FCFF.FFFF16

PCI memory spaceVME memory

Y Y N N [32]

FD00.0000 16 … FDFF.FFFF16

PCI/ISA memory space0000.000016 … 00FF.FFFF16on PCI (see table 24 “PPC/PowerCore-6603/4I/O map seen from the PCI” onpage 42)

Y Y N N [8]

FE00.000016 … FE7F.FFFF 16

ISA bus ports(see table 26 “PPC/PowerCore-6603/4ISA bus ports seen from the CPU” onpage 43)

Y Y N N [8]

FE80.000016 … FEBF.FFFF16

4-Mbyte PCI I/O space0080.000016 … 00BF.FFFF 16on PCI (see table 24 “PPC/PowerCore-6603/4I/O map seen from the PCI” onpage 42)

Y Y N N [32]

FEC0.000016 … FEDF.FFFF16

Configuration address register of thePowerPC-to-PCI bridge

Y Y N N [32]

FEE0.0000 16 … FEEF.FFFF16

Configuration data register of thePowerPC-to-PCI bridge

N N N N [32]

FEF0.0000 16 … FEFF.FFFF16

PCI interrupt acknowledge N N N N [32]



FF00.000016 … FFDF.FFFF16


FFE0.000016… FFEF.FFFF16

User flash space Y Y Y N [8]

FFF0.0000 16… FFFF.FFFF 16

Boot flash space Y Y Y N [8]

Table 23 PPC/PowerCore-6603/4 memory map seen from the PCI

PCI memory address Device


width[bit]PPC VME L1 L2

0000.0000 16 … 3FFF.FFFF 16

System memory space consisting of:

• on-board system memory (EDORAM),

• additional memory module

The on-board system memory and thememory module space are contiguous,the end address depends on the memo-ry capacity.

Y Y Y Y [64]

4000.000016… 7FFF.FFFF 16


8000.000016 … FCFF.FFFF16

PCI memory spaceVME memory space

Y Y N N [32]

FD00.0000 16 … FDFF.FFFF16

System memory space0000.0000 16 … 00FF.FFFF16 (see table 22 “PPC/PowerCore-6603/4memory map seen from the CPU” onpage 40)

Y Y N N [32]

FE00.000016 … FFDF.FFFF16



User flash space Y Y Y N [8]

FFF0.0000 16… FFFF.FFFF 16

Boot flash space Y Y Y N [8]

Table 22 PPC/PowerCore-6603/4 memory map seen from the CPU (cont.)

Address on the PowerPC bus Device


width[bit]PCI VME L1 L2


PPC/PowerCore-6603/4 Address Map Hardware

Table 24 PPC/PowerCore-6603/4 I/O map seen from the PCI

PCI I/O address Device

Accessiblebus Cache Bus

width[bit]PPC VME L1 L2

0000.000016 … 0000.FFFF 16

ISA I/O space FE00.0000 16 … FE00.FFFF16 onPowerPC CPU (see table 22 “PPC/PowerCore-6603/4memory map seen from the CPU” onpage 40)

Y Y N N [8]

0001.000016 … 007F.FFFF 16


0080.000016… 00BF.FFFF 16

PCI I/O spaceFE80.0000 16 … FEBF.FFFF16 onPowerPC CPU (see table 22 “PPC/PowerCore-6603/4memory map seen from the CPU” onpage 40)

Y Y N N [32]

00C0.000016… FFFF.FFFF 16


Table 25 PPC/PowerCore-6603/4 configuration base addresses

Configuration base address Device

8000.000016 Base address

8000.C00016 Universe II

8000.D00016 PCI-to-ISA bridge ISA

8000.D10016 PCI-to-ISA bridge

8000.D80016 Ethernet controller

8000.E00016 PMC 1

8000.E80016 PMC 2



Note: This address map is a default address map which can bechanged by the user.

Table 26 PPC/PowerCore-6603/4 ISA bus ports seen from the CPU

Address Device

FE00.007316and FE00.007416

1)

NVRAM/RTC address low register

FE00.007516 NVRAM/RTC address high register

FE00.007716 NVRAM/RTC data register

FE00.030016… FE00.0303 16

CIO registers

FE00.0308 16 DRAM and cache configuration register

FE00.03F8 16… FE00.03FF 16

Serial I/O port

FE00.0310 16 Chip select signal (PN15 connector)

1. If you address the NVRAM/RTC via FEOO.007416, theaddress FEOO.007016 will be overwritten (see “PCI-to-ISA Bridge – PIIX 82371FB”, Data Sheets). To avoid this,address the NVRAM/RTC via FE00.007316.

Table 27 PPC/PowerCore-6603/4 PCI I/O devices seen from the CPU

Address Device

FE80.000016… FE80.003F 16

Ethernet controller

FE81.0000 16… FE81.0FFF 16

Universe II VME

user defined PMC 1

user defined PMC 2

FEC0.0000 16… FEDF.FFFF16

PCI configuration address register

FEE0.0000 16… FEEF.FFFF16

PCI configuration data register

FEF0.0000 16… FEFF.FFFF16

PCI interrupt acknowledge register


PPC/PowerCore-6603/4 Interrupt Map Hardware

erial

on

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lerhe

ernal

to-upt

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Ihest

their5pri-

3.2 PPC/PowerCore-6603/4 Interrupt Map

The PCI-to-ISA bridge monitors all PPC/PowerCore-6603/4 interrupt re-quests (IRQs):

Interrupt requests

• interrupt requests of all four PCI bus interrupt levels,

• interrupt requests from on-board ISA bus devices, e.g. from the scontroller,

• optional interrupt requests (see figure 2 “PN15 Connector Pinout”page 18),

• optional interrupt requests from the IDE interfaces,

• and interrupt requests from the VMEbus interface.

ACFAIL* and SYSFAIL*

Additionally, the VMEbus signals ACFAIL* and SYSFAIL* can be programmed in Universe II to assert PCI interrupt requests.

PCI-to-ISA bridge interrupt controller

The PCI-to-ISA bridge provides an ISA compatible interrupt controlthat incorporates the functionality of two interrupt controllers 82C59. Ttwo controllers are cascaded so that 13 chip external and 3 chip intinterrupts are possible.For information on programming the interrupt controller, see “PCI-ISA Bridge – PIIX 82371FB” Data Sheets and section 3.14.3 “InterrController” on page 78.

Flexible interrupt programming

Every interrupt source, including the VMEbus IRQs, can be enableddisabled to interrupt the CPU. The PCI-to-ISA bridge supplies the inrupt vectors for all interrupts except the NMI.

NMI The NMI is routed from the IOCHK interrupt via the PowerPC-to-PCbridge to the MCP signal at the PowerPC CPU. The NMI has the higpriority and is a non-vectored processor exception.

Interrupt priority The following table shows the default mapping of the interrupts and interrupt priority. Interrupt priority level 0 is the highest priority, level 1is the lowest priority. The mapping of the interrupts and the interrupt ority can be set also by the user.


Hardware PPC/PowerCore-6603/4 Interrupt Map

Table 28 Default PPC/PowerCore-6603/4 interrupt map

Function DevicePCI-to-ISA bridge IRQ

Interrupt priority level

Watchdog timer/ abort key/SERR #

Dedicated logic IOCHK (MCP) 0

Timer 1/counter 0 PCI-to-ISA bridge IRQ0 1

User available PN15 connector (factory option) IRQ1 2

Cascade PCI-to-ISA bridge IRQ2 –

INTC # PCI devices IRQ3 11

Serial port Serial port IRQ4 12

INTD # PCI devices IRQ5 13



Timer/parallel port IRQ

CIO IRQ8# 3

Reserved – IRQ9 4

INTA # PCI device: Ethernet controller IRQ10 5

INTB # PCI device: Universe II IRQ11 6


Reserved – IRQ13 8

IDE Primary IDE interface IRQ14 9

IDE Secondary IDE interface IRQ15 10


PowerPC CPU Hardware

ue anden-

The following table shows the interrupt routing of the PMC slots.

3.3 PowerPC CPU

The PowerPC CPU is one of the fundamental components of the PPC/Pow-erCore-6603/4 board. Depending on the variant the board utilizes either aPowerPC 603e, a PowerPC 603ev, or a PowerPC 604e. For detailed infor-mation, refer to the PowerPC User’s Manuals available from Motorola.

3.3.1 PowerPC 603e and PowerPC 603ev

The only difference between the processors PowerPC 603e andPowerPC 603ev is the reduced power supply voltage and the reducedpower consumption of the PowerPC 603ev.

The PowerPC 603e and the PowerPC 603ev are a low-power implemen-tation of the PowerPC family of RISC microprocessors. They provide:

• 32-bit effective addresses,

• integer data types of 8, 16, and 32 bits,

• and floating-point data types of 32 and 64 bits.

Execution units The 603e and the 603ev are superscalar processors which can issretire three instructions per clock. They include the following indepdent execution units:

• integer unit (IU),

• floating-point unit (FPU),

• branch processing unit (BPU),

• load and store unit (LSU),

• and system register unit (SRU).

Table 29 PMC interrupt routing

Interrupt lines

PCI-to-ISA bridge PMC slot 1 PMC slot 2

INTA # INTC # INTB #

INTB # INTD # INTC #

INTC # INTA # INTD #

INTD # INTB # INTA #


Hardware PowerPC CPU

he

tion

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ay

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ISC

our in-ock.

edic-ran-

Because of the ability to execute five instructions in parallel and the useof simple instructions with short execution times, the 603e and the 603evprovide a high instruction and data throughput. Most instructions can beexecuted in one clock cycle. The FPU is pipelined so that a single-preci-sion instruction can be issued every clock cycle.

Additional features

The 603e and the 603ev provide:

• 16-Kbyte, four-way set-associative, physically addressed data cac

• 16-Kbyte, four-way set-associative, physically addressed instruccache

• instruction memory management unit (MMU) including 64-entrtwo-way set-associative ITLB (instruction translation lookasibuffer)

• data memory management unit (MMU) including 64-entry, two-wset-associative DTLB (data translation lookaside buffer)

The TLBs support demand-paged virtual memory address translationvariable-sized block translation. The TLBs and the caches use a leacently used replacement algorithm.

3.3.2 PowerPC 604e

The PowerPC 604e is an implementation of the PowerPC family of Rmicroprocessors. It provides:

• 32-bit effective addresses,

• integer data types of 8, 16, and 32 bits,

• and floating-point data types of 32 and 64 bits.

Execution units The PowerPC 604e is a superscalar processor capable of issuing fstructions simultaneously. Six instructions can start executing per clIt includes the following independent execution units:

• floating-point unit (FPU),

• branch processing unit (BPU),

• load and store unit (LSU),

• and three integer units (IUs):

– two single-cycle integer units (SCIUs),

– one multiple-cycle integer unit (MCIU).

Additional features

The 604e’s rename buffers, reservation stations, dynamic branch prtion, and the completion unit increase the instruction throughput, guatee in-order completion, and ensure a precise exception model.


L2 Cache Hardware

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L2PCIche

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by the

The 604e provides:

• 32-Kbyte data cache

• 32-Kbyte instruction cache

• data memory management unit (MMU) including DTLB (data tranlation lookaside buffer)

• instruction memory management unit (MMU) including ITLB(instruction translation lookaside buffer)

The TLBs support demand-paged virtual memory address translationvariable-sized block translation. The TLBs and the caches use a leacently used replacement algorithm.

3.4 L2 Cache

PPC/PowerCore-6603/4 provides an L2 cache of up to 1 Mbyte. Thecache is controlled by the L2 cache controller of the PowerPC-to-bridge. This L2 cache controller provides a 64-bit data lookaside cainterface. The L2 cache is designed as directly mapped cache. Onlmemory space of the processor bus devices can be cached inL2 cache. Synchronous burst SRAM chips are used as data cache des.

Data sheet For further information on programming the L2 cache controller, se“PowerPC-to-PCI Bridge – MPC106 (Grackle)” Data Sheets.

Cache devices Depending on the L2 cache configuration PPC/PowerCore-6603/4tains different cache tag and data cache devices. The following tablethe included cache devices.

16K * 15 bit static cache tag RAM devices are used to qualify a matcaddress, which means, that the actual address on the PowerPC bucached address. Data of the according address are then supplied cache RAM rather than by the EDO RAM or by the flash memory.

Table 30 Cache devices

L2 cache Cache tag device Data cache device

0 0 0

256 Kbyte 1 * 16K * 15 2 * 32K * 36

512 Kbyte 1 * 16K * 15 4 * 32K * 36

1 Mbyte 2 * 16K * 15 2 * 128K*36


Hardware Watchdog Timer

on

oni-

out

g a

on-

L2 cache size The available size of the L2 cache can be read by the software from theDRAM and cache configuration register bits [7...6].

DCCR [7…6] DCCR [7…6] indicate the L2 cache configuration.

= 002 No L2 cache available

= 012 256-Kbyte L2 cache

= 112 512-Kbyte L2 cache

= 102 1-Mbyte L2 cache

DCCR [5…0] see table 34 “DRAM and cache configuration register, bits [5…0]” page 53

3.5 Watchdog Timer

There is a watchdog timer installed on PPC/PowerCore-6603/4 to mtor the CPU activity. The watchdog timer is able

• to issue an NMI interrupt to the PowerPC CPU after the first timeperiod

• and to generate a reset pulse after a second timeout period.

3.5.1 Watchdog Operation

The watchdog timer monitors the PowerPC CPU activity by awaitintrigger event from the PowerPC CPU within the timeout period.

Trigger event The bit TRWD in the CIO port C data register starts the watchdog and ctrols whether the watchdog timer is triggered.

Table 31 DRAM and cache configuration register, bits [7…6]

FE00.030816

Bit 7 6 5 4 3 2 1 0

Value DCCR [7…6] DCCR [5…0]


Watchdog Timer Hardware

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TRWD TRWD starts the watchdog timer. A positive edge at this pin retriggers thewatchdog.

= 0 watchdog timer is started, if low level is held for more than 8 ms.

0 → 1 watchdog timer is retriggered.

= 1 (default) no change

LED[1…0] see table 52 “CIO port C data register, bits [1…0]” on page 83

Timeout A set of watchdog timeout periods can be selected via SW5-2 table 11 “Switch Settings” on page 11).

Enable the watchdog

The watchdog is enabled by setting SW5-1 to ON (default “OFF”).

Start the watchdog

When the watchdog is started, it cannot be stopped unless a reset oIn case of a reset the watchdog timer is automatically disabled.

Retrigger the watchdog

The watchdog is retriggered, if a positive edge occurs at the TRWD signal.This means that you have to write 0 to TRWD, followed by 1.

Interrupt The watchdog interrupt is the IOCHCK input of the PCI-to-ISA bridwhich is routed to the MCP interrupt input of the PowerPC CPU. Thisterrupt is called NMI.

NMI generation If the retrigger event does not occur within the first watchdog timeouriod, the watchdog timer generates an NMI to the PowerPC CPU.If the retrigger event occurs within the second watchdog timeout peafter generating the NMI, the watchdog timer is restarted.

Table 32 CIO Port C data register, bit [2]

FE00.030016

Bit 7 6 5 4 3 2 1 0

Value used as masking bits for writeaccesses to bit 3…0 (e.g.: if bit 4is 1, bit 0 cannot be written)

re-served

TRWD LED[1…0]


Hardware System Memory (EDO RAM)

on

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ded-

ID_SCL and ID_SDA

see table 51 “CIO port B data register, bits [7…6]” on page 83

BUSMODE [4…2] and BUSMODE [1…0]

ssee table 53 “CIO port B data register, bits [5…3] and [2…1]” page 85

WDNMI WDNMI indicates whether the watchdog timer has generated an NMI. bit WDNMI is cleared when the watchdog timer is retriggered.

= 0 watchdog timer has not generated an NMI.

= 1 (default) watchdog timer has generated an NMI.

Timeout period after NMI – reset

If the retrigger event does not occur within the second watchdog timperiod after generating the NMI, the watchdog timer generates a rpulse, thereby automatically stopping itself. It then must be restarteresetting TRWD in the CIO port C configuration register as already staabove.

3.6 System Memory (EDO RAM)

PPC/PowerCore-6603/4 provides an on-board memory. Additional mory can be implemented by a memory module (contiguous addressee section 3.6.6 “EDO RAM Access from the PowerPC CPU” page 55). For information on the installation of the memory module, reto the PPC/PowerCore-MEM Installation Guide. The on-board memory of PPC/PowerCore-6603/4 is a shared extendata-out RAM (EDO RAM). Snooping is supported.

Table 33 CIO port B data register, bit [0]

FE00.030116

Bit 7 6 5 4 3 2 1 0

Value ID_SCL ID_SDA BUSMODE[4…2] BUSMODE[1…0] WDNMI


System Memory (EDO RAM) Hardware

CCThe er-The (see

read

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tten

CC areirstl beta at9).

willory.

Accessibility The system memory is accessible from:

• PowerPC CPU,

• Universe II DMA controller,

• other VMEbus masters,

• Ethernet DMA controller,

• other PCI DMA controllers on PMC modules,

• or from the PCI-to-ISA bridge DMA controller.

ECC The memory controller of the PowerPC-to-PCI bridge supports an E(error correction code) for the data path from the system memory. ECC detects and corrects all single-bit errors. Double-bit errors andrors within a nibble are only detected but not corrected by the ECC. ECC is enabled per default and can be disabled by the software“PowerPC-to-PCI Bridge – MPC106 (Grackle)” Data Sheets.

System memory read

• If the ECC is disabled, the bytes requested by the master are from the system memory.

• If the ECC is enabled, all 8 long-word, aligned data bytes and ECC byte are read from the system memory, regardless of size (half-word, word, long-word, or cache line) and regardless of ma(PowerPC CPU, DMA controllers, or VMEbus). The 8 bytes and ECC byte are stored in the memory controller.

System memory write

Write cycles are handled differently:

• If the ECC is disabled, the bytes provided by the master are wriinto the system memory.

• If the ECC is enabled, the memory controller can generate the Efor the bytes written by the current master only if at least 8 bytesprovided. Single beat writes to memory from the processor will fbe latched by the memory controller, the aligned 8 byte lanes wilread and the read data will be merged with the processor write dathe location determined by the three lower address bits (A31…A2The ECC byte will be generated, and then the memory controller drive both the merged 8 byte lanes and the ECC byte to the mem



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3.6.1 Memory controller

The memory controller is located in the PowerPC-to-PCI bridge.

Memory configuration

The memory controller registers of the PowerPC-to-PCI bridge are acces-sible via the configuration address register (CAR) and the configurationdata register (CDR). For configuring the memory controller, the CARand the CDR must be set appropriately (see section 3.9 “PowerPC-to-Bridge” on page 62).

3.6.2 EDO RAM Performance

The on-board memory control logic is optimized for fast accesses fthe PowerPC CPU providing the maximum performance with enabECC. Since the PowerPC CPU includes an on-chip data and instrucache many CPU accesses are cache line "burst fills". Within four 8-cycles these burst fills attempt to read 32 consecutive bytes intoPowerPC CPU.

"8-4-4-4" burst transfer

The first read cycle of such a burst usually requires 8 PPC bus clockcles. Due to the optimized design of the memory control logic, each sequent cycle only requires 4 PPC bus clock cycles to complete. Thcommonly called a "8-4-4-4" burst transfer. Overall, the total cache "burst fill" operation requires 20 PPC bus clock cycles to trans32 bytes, providing a memory bandwidth of over 105 Mbyte/s.

Single read and write

Not all CPU accesses are burst transfers. Single read and write trations are also supported at maximum speed. A single read or write a(1, 2, 4, or 8 bytes) requires 7 PPC bus-clock cycles. Distributed achronous refresh is provided every 14µs and an access during a pendinrefresh cycle may be delayed by a maximum of 6 additional clock cyc

3.6.3 EDO RAM Capacity

The capacity of the on-board EDO RAM and an additional memory mule is encoded in the DRAM and cache configuration register.

Table 34 DRAM and cache configuration register, bits [5…0]

FE00.030816

Bit 7 6 5 4 3 2 1 0

Value DCCR [7…6] DCCR [5…0]



on
DCCR [7…6] see table 31 “DRAM and cache configuration register, bits [7…6]” page 49
DCCR [5…0] indicate the capacity of the available EDO RAM located either on-boardor on an additional memory module. All combinations not listed in thefollowing table are reserved.

3.6.4 EDO RAM Organization

The on-board EDO RAM is arranged in one memory bank with nine2M * 8 EDO RAM devices. Up to 2 additional banks can be added. Eachmemory bank is 64-bit wide plus 1 byte for the ECC.

3.6.5 Cache Coherency and Snooping

To maintain cache coherency of the system memory the PowerPC CPUhas the capability of snooping. On a snooped external bus cycle thePowerPC CPU invalidates the cache line that is hit. Snoop hits invalidatethe cache line in all cases (also for alternate master read/write cycles).The L2 interface of the PowerPC-to-PCI bridge also supports snoop cy-cles.

Note: To guarantee the cache coherency of the system memory, thesnooping in the processor interface configuration register of thePowerPC-to-PCI bridge has to be enabled (see “PowerPC-to-PCIBridge – MPC106 (Grackle)”, Data Sheets).

Table 35 EDO RAM capacity

DCCR [5…0] EDO RAM capacity

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 On-board On-module

1 1 1 1 1 1 16 Mbyte –

1 1 0 1 1 1 16 Mbyte 16 Mbyte

1 1 1 0 1 1 16 Mbyte 32 Mbyte

1 1 1 1 0 1 16 Mbyte 64 Mbyte

1 1 1 1 1 0 16 Mbyte 128 Mbyte



esss the

3.6.6 EDO RAM Access from the PowerPC CPU

After initialization the firmware enables the complete EDO RAM at startaddress 0000.000016. The memory address range, which is accessiblevia the PPC bus, can be programmed in the PowerPC-to-PCI bridgememory controller. Depending on the EDO RAM capacity, the end ad-dress is set to the maximum available memory by the firmware.

Memory modules

The EDO RAM accesses are always contiguous, even if the completememory is located on added memory modules.

3.6.7 EDO RAM Access via the VMEbus

Shared EDO RAM access from or to the VMEbus is routed byUniverse II via the PCI bus and the PowerPC-to-PCI bridge. The startand end access addresses can be programmed.

Programmable access address range

The access address of the shared EDO RAM for other VMEbus mastersis programmable via Universe II. Both the start and the end address of theshared RAM are Universe II programmable in 4-Kbyte increments (see“PCI-to-VME bridge – Universe II” Data Sheets). Therefore, the addrrange used by other VMEbus masters is not necessarily the same aone used by the PowerPC CPU for local accesses.

Table 36 Default EDO RAM access address ranges from the PowerPC CPU

Address range Memory capacity

0000.000016…00FF.FFFF16 16 Mbyte

0000.000016…01FF.FFFF16 32 Mbyte

0000.000016… 03FF.FFFF16 64 Mbyte

0000.000016… 04FF.FFFF16 80 Mbyte

0000.000016… 07FF.FFFF16 128 Mbyte

0000.000016… 08FF.FFFF16 144 Mbyte



Write protection The write protection of the programmed memory range depends on theVMEbus address modifier codes: For example, in privileged mode thememory can be read and written, while in non-privileged mode the mem-ory can only be read, or a non-privileged access can be prohibited alto-gether.

VMEbus access cycle

When Universe II detects a VMEbus access cycle to the programmed ad-dress range of the shared EDO RAM it requests bus mastership of thePCI bus via the PCI bus arbiter. After the arbiter has granted the PCI busmastership to Universe II, the VMEbus access cycle is executed and alldata is latched from (read cycles) or stored to (write cycles) the RAM.After this the cycle is terminated and Universe II keeps the PCI bus mas-tership until another PCI bus master requests the bus. Universe II alsocompletes the fully asynchronous VMEbus access cycle.

Locked read- modify-write cycles

Read-modify-write cycles from the VMEbus are indivisible. LockedPCI bus cycles achieve that Universe II retains the local bus mastershipuntil the VMEbus cycle is finished. By this no other local bus master(PowerPC CPU) will access the shared RAM before the VMEbus cycle isterminated.

3.6.8 EDO RAM Access from the Ethernet Controller

The Ethernet controller uses the PCI bus mastership to transfer com-mands, data, and status information to and from the EDO RAM via thePCI bus and the PowerPC-to-PCI bridge.

3.6.9 EDO RAM Access from PMC Modules

The PMC modules may use the PCI bus mastership to transfer com-mands, data, and status information to and from the EDO RAM via thePCI bus and the PowerPC-to-PCI bridge.

3.6.10 EDO RAM Access from the PCI-to-ISA Bridge

The PCI-to-ISA bridge uses the PCI bus mastership to transfer com-mands, data, and status information to and from the EDO RAM via thePCI bus and the PowerPC-to-PCI bridge.


Hardware Boot Flash

3.7 Boot Flash

The flash memory area is located on the PowerPC processor bus so thatthe reset vector table in the boot flash is visible to the CPU after power-on reset. The boot flash has a maximum size of 1 Mbyte and can directlybe accessed by the CPU.

3.7.1 Boot Flash Address Range

The flash memory area is 8-bit wide organized. The PowerPC-to-PCIbridge provides 21 addressing lines to address the board flash memory.Therefore 2 Mbyte of the flash address rangeFF00.000016 ... FFFF.FFFF16 are accessible for 8-bit wide orga-nized flash devices. 1 Mbyte address space is used for the boot flash.

Reset vector The CPU reset vector is located at address FFF0.010016.

3.7.2 Boot Flash Size and Address Map

The accessible address range of the boot flash is determined by the bootflash capacity and therefore the address range depends on the board type.

Table 37 Boot flash address range

Address range Boot flash capacity

FFF0.000016… FFFF.FFFF 16 up to 1 Mbyte

Table 38 Boot flash address map

Boot flash [Kbyte]Total boot flash

Resulting address range 1 (J40) 2 (J36)

256 – 256 Kbyte FFF0.000016 … FFF3.FFFF 16

256 256 512 Kbyte FFF0.0000 16 … FFF7.FFFF 16

512 – 512 Kbyte FFF0.000016 … FFF7.FFFF 16

512 512 1 Mbyte FFF0.0000 16 … FFFF.FFFF 16


Boot Flash Hardware

ash

Caution The boot flash size is a factory option. To identify the boot flash sizefor which the board is configured, read bit 5 of the CIO port A dataregister (see table 40 “CIO port A data register, bits [7] and [5]” onpage 58 and the PowerBoot Instruction Set). If you install a boot flashdevice that has a different size than the boot flash for which theboard has been configured, do not reprogram the boot flash deviceon-board. Otherwise the devices could be damaged.

3.7.3 Boot Flash Devices

The boot flash is implemented by up to 2 user programmableflash devices. Per default 2 flash devices are implemented.

Location J40 and J36 (socketed)

Base address FFF0.000016

Device type factory options

There are 2 device type factory options available:

• flash devices programmable at 12 V

• and flash devices programmable at 5 V.

The following table shows the factory options available for the boot flusing the listed device types (or equivalent).

Table 39 Boot flash factory options, device types, and default configuration

Device type Default

1. 29F040:512K * 85-V flash

x

2. 28F020:256K * 812-V flash

Table 40 CIO port A data register, bits [7] and [5]

FE00.0302

Bit 7 6 5 4 3 2 1 0

Value VPP_CTRL

ISA_IDENT

BOOT_SIZE

re-served

FLSH_SEL [1…0]

FLSH [A21…A20]


Hardware Boot Flash

as

ad-

boot

ult by40

cor-wer-G

VPP_CTRL (W)

VPP_CTRL controls whether the +12V programming voltage VPP for theboot flash and user flash is ON.

= 0 (default) VPP is turned off.

= 1 VPP is turned on.

ISA_IDENT see table 50 “CIO port A data register, bit [6]” on page 82

BOOT_SIZE(R)

BOOT_SIZE indicates the boot flash size for which the CPU board hbeen configured.

= 0

= 1

CPU board configured for 512-Kbyte boot flash (default). The start dress of boot flash 2 is FFF8.000016.CPU board configured for 256-Kbyte boot flash. The start address of flash 2 is FFF4.000016.

FLSH_SEL[1…0](R/W) and FLSH[A21…A20](R/W)

see table 41 “CIO port A data register, bits [7] and [3…0]” on page 60

3.7.4 Programming the Boot Flash

Writing to the boot flash is only enabled if SW6-4 is set to ON (defa“OFF”). The programming voltage for the flash devices is turned onsetting bit 7 of the CIO port A data register appropriately (see table“CIO port A data register, bits [7] and [5]” on page 58).

When writing to the boot flash is enabled, programming is handled rectly by PowerBoot packaged with PPC/PowerCore-6603/4 (see PoBoot Instruction Set “FERASE – Erasing Flash Memories” and “FPRO– Programming Flash Memories”) and by the assembly process.

Caution Before erasing or programming the boot flash ensure that you do notdestroy Force Computers’ firmware and make a copy of the contentsof the boot flash.


User Flash Hardware

ter,ese

PCIory.

ge-

ieveto 4lds

3.8 User Flash

The second Mbyte of the flash memory space is used for the user flash.To achieve more than only one Mbyte user flash, the user flash is onlyvisible bankwise, each bank consisting of 1 Mbyte. Since only 1 Mbyte ispreserved for the user flash bank, switching techniques are provided byfive additional parallel port pins (see table 41 “CIO port A data regisbits [7] and [3…0]” on page 60) to increase the user flash capacity. Thpins extend the PowerPC-to-PCI bridge addressing lines.

3.8.1 User Flash Address Range

The flash memory area is 8-bit wide organized. The PowerPC-to-bridge provides 21 addressing lines to address the board flash memTherefore 2 Mbyte of the complete flash address ranFF00.000016 ...FFFF.FFFF16 are accessible for 8-bit wide organized flash devices. 1 Mbyte is used for the user flash.

The register map below shows the additional bits to be added to achthe maximum of 8-Mbyte user flash. The user flash can be divided inflash devices each consisting of 2 banks with 1 Mbyte. CIO port A hothese additional bits.

VPP_CTRL (W)

VPP_CTRL controls whether the +12V programming voltage VPP for theboot flash and user flash is ON.

= 0 (default) VPP is turned off.

= 1 VPP is turned on.

ISA_IDENT see table 50 “CIO port A data register, bit [6]” on page 82

BOOT_SIZE see table 40 “CIO port A data register, bits [7] and [5]” on page 58

FLSH_SEL[1…0](R/W)

FLSH_SEL[1…0] selects the flash device that is paged into the memoryrange FFE0.0000 16 … FFEF.FFFF16 (default setting is 002).

Table 41 CIO port A data register, bits [7] and [3…0]

FE00.0302

Bit 7 6 5 4 3 2 1 0

Value VPP_CTRL

ISA_IDENT

BOOT_SIZE

re-served

FLSH_SEL [1…0]

FLSH [A21…A20]


Hardware User Flash

k un-

User are

FLSH [A21…A20](R/W)

The outputs FLSH_A21 and FLSH_A20 are directly connected to theaddress pins A21 and A20 of the user flash footprint. This allows to ad-dress flash devices up to a size of 4 Mbyte. Since the user flash can be ac-cessed only in the physical range FFE0.0000 16…FFEF.FFFF16, thesoftware has to set these bits appropriately to select the 1-Mbyte bander consideration.

Note: The firmware supports easy commands to select the devicebank which is to be mapped into the address range (see PowerBootInstruction Set, section "FSELECT – Selecting Flash Memory").

3.8.2 User Flash Size

The on-board user flash is accessible according to see table 42 “flash address map” on page 61. The following user flash capacitiesavailable:

• 0 Mbyte

• or 4 Mbyte if four 1M * 8 devices are used.

3.8.3 User Flash Devices

The user flash consists of up to 4 user programmable flash devices.

Base address FFE0.000016

Device type factory options

There are 2 device type factory options available:

• no flash devices

Table 42 User flash address map

User flash device #

FLSH_SEL [1…0] Address range

1 002 FFE0.000016… FFEF.FFFF16

2 012 FFE0.0000 16… FFEF.FFFF16

3 102 FFE0.0000 16 … FFEF.FFFF16

4 112 FFE0.0000 16… FFEF.FFFF16


PowerPC-to-PCI Bridge Hardware

ashault

tely de-ro-

on

cor-

dbly

liantory,

dressFur-

opy- data

helly,

• 1M * 8 flash devices

The following table shows the factory options available for the user flusing the device types listed (or equivalent). The first option is the defconfiguration.

3.8.4 Programming the User Flash

Writing to the user flash is only enabled when SW6-3 is set appropria(default “OFF”, see page 13). The programming voltage for the flashvices is turned on by setting bit 7 of the CIO port A data register apppriately (see table 40 “CIO port A data register, bits [7] and [5]” page 58).

When writing to the user flash is enabled, programming is handled rectly by PowerBoot packaged with PPC/PowerCore-6603/4 (see Power-Boot Instruction Set section “FERASE – Erasing Flash Memories” ansection “FPROG – Programming Flash Memories”) and by the assemprocess.

3.9 PowerPC-to-PCI Bridge

The PowerPC-to-PCI bridge provides an integrated, PowerPC compinterface between the PowerPC CPU, the L2 cache, the main memthe user and boot flash, and the PCI bus.

Processor interface

The processor interface provides a 64-bit data bus and a 32-bit adbus. It supports an external L2 cache and full memory coherency. thermore, it pipelines processor accesses.

L2 cache control The L2 cache controller provides write-through (store-through) or cback (write-back, store-in) modes and supports synchronous burstRAM.

Memory interface

The memory interface is programmed to support EDO DRAM. Tmemory interface provides a 64-bit data bus to EDO RAM. Additiona

Table 43 User flash factory options and device types

Device type Address range

1. No user flash installed

2. 28F008:1M * 812V user flash



Hardware PowerPC-to-PCI Bridge

d,

l

and

con-sternd

ffset

egis-e

ters

ECC for the EDO RAM is per default enabled by software. The Power-PC-to-PCI bridge supports up to 1-Gbyte EDO RAM memory size. The memory interface supports contiguous memory mapping, writing offlash memory, and write buffering for PCI and processor accesses.

Features of the PCI interface

The PCI interface implements the following features:

• compliance with PCI 2.1,

• operation at 30 or 33 MHz depending on the actual PCI bus spee

• PCI interlocked accesses to memory via lock pin and lock protoco

• accesses to all PCI address spaces,

• selectable big or little endian operation

• store gathering of PPC-to-PCI writes and PCI-to-memory writes memory prefetching of PCI read accesses,

• PCI configuration registers,

• data buffering (in/out),

• and parity support.

Miscellaneous features

Furthermore, the PCI interface provides the following features:

• error reporting mechanism,

• JTAG boundary scan,

• and concurrent transactions on the processor and the PCI bus.

Registers of the PowerPC-to-PCI bridge

The register set of the PowerPC-to-PCI bridge is accessible via the figuration address register (CAR) and the configuration data regi(CDR). To configure the memory or L2 cache controller, the CAR athe CDR must be set appropriately:

• To access the register set of the PowerPC-to-PCI bridge with oxy, the CAR must contain xy00.008016 (see table 25 “PPC/Pow-erCore-6603/4 configuration base addresses” on page 42). The rter offset xy has to be written into the most significant byte of thCAR. The lowest significant byte must be set to 8016 (byteswapped).

• The CDR contains the contents for the memory controller regis(R/W) to be accessed.


VMEbus Interface – Universe II Hardware

ata

see

n

the

Example If you want to enable memory bank 0 and 1, you have to access the mem-ory bank enable register at offset A016 and to write the value 0316 intothis register (see “PowerPC-to-PCI Bridge – MPC106 (Grackle)” DSheets):

1. Write the value A000.008016 to the CAR address FEC0.000016.

2. Write the value 0316 to the CDR address FEE0.000016.

Data sheet For a detailed description of configuring the memory controller,“PowerPC-to-PCI Bridge – MPC106 (Grackle)”, Data Sheets.

3.10 VMEbus Interface – Universe II

Universe II provides a direct PCI-to-VME interface. It is compliant withANSI/VITA 1-1994, acts as both master and slave in the VMEbus systemand is particularly convenient for PCI local bus systems.

Features of Universe II

Universe II provides:

• a fully PCI compliant, 64-bit, up to 33-MHz PCI bus interface,

• a fully ANSI/VITA 1-1994 compliant 64-bit VMEbus interface,

• integral FIFOs for write posting to maximize bandwidth utilizatio(64 bits wide, 32 entries deep),

• a programmable DMA controller with linked list support,

• a complete suite of VMEbus address and data transfer modes:

– A32/A24/A16 master and slave

– D64 (MBLT)/D32/D16/D08 master and slave

– BLT, ADOH, RMW, LOCK

• a flexible register set, programmable from both the PCI bus andVMEbus,

• a full VMEbus system controller functionality,

• four 32-bit mailboxes for interrupt generation on either bus,

Table 44 CAR and CDR address map

Register Address

CAR FEC0.000016

CDR FEE0.000016


Hardware VMEbus Interface – Universe II

ata

ec-

pli-

bitded,

inter-

up-hile and

II en-ter-nced,

ter-

upt

ple-.11

• a location monitor for interrupts and message passing,

• 7 VME software interrupts,

• 2 semaphore registers to control access to system resources,

• and IEEE 1149.1 JTAG testability support.

CSR base address

The CSR base address is located at address FE81.000016.

Data sheet For a detailed description see “PCI-to-VME bridge – Universe II” DSheets.

3.10.1 VMEbus Interface

The following sections describe the VMEbus interface in detail. This stion gives a short overview of the VMEbus interface features.

ANSI/VITA compliance

PPC/PowerCore-6603/4 provides a complete VMEbus interface comant with ANSI/VITA 1-1994.

Supported transfers

The VMEbus interface supports 64-bit (MBLT), 32-bit, 16-bit, and 8-data transfers, as well as unaligned data transfers (UAT). The extenstandard, and short I/O address modifier codes are implemented to face PPC/PowerCore-6603/4 to the VMEbus.

RMW cycles Read-modify-write cycles on the VMEbus (RMW cycles) are also sported. The address strobe signal is held low during RMW cycles wthe data strobe signals are driven low twice, once for the read cycleonce for the write cycle, and high between both of them.

Interrupt handler The complete VMEbus interrupt management is done by Universeabling the use of a high-end multiprocessor board with distributed inrupt handling. Universe II acts as D08(O) interrupt handler in compliawith ANSI-VITA 1-1994, i.e. 8-bit interrupt vectors are supportewhereas 16-bit interrupt vectors are not supported.

All 7 VMEbus interrupt request (IRQ) signals are connected to the inrupt handling logic of Universe II.

• All 7 VMEbus IRQ signals can be separately enabled or disabled.

• Every VMEbus interrupt request level causes a PCI interr(INTB#) if enabled.

Slot-1 function An arbiter with several arbitration modes and release functions is immented with all slot-1 system controller functions (see section 3“VMEbus Slot-1” on page 70):



ann-

isy-any

*,hee

the

if

setS-

er,

e

• VMEbus arbiter,

• SYSCLK driver,

• and IACK daisy-chain driver (see below).

IACK Daisy Chain Driver

In accordance with ANSI-VITA 1-1994 the CPU board includes IACK daisy-chain driver. If the CPU board is plugged in slot 1 and cofigured accordingly by SW7-1 and SW7-2, the board acts as IACK dachain driver (see table 47 “Slot-1 functions” on page 71). Plugged in other slot the board closes the IACKIN-IACKOUT path.

Caution Damaging PPC/PowerCore-6603/4 componentsFor proper operation the jumper for IACKIN-IACKOUT- andBGIN-BGOUT-bypass on the backplane must be removed. This isnot necessary on active backplanes.

3.10.2 Exception Signals SYSFAIL, SYSRESET, and ACFAIL

The ANSI-VITA 1-1994 standard includes the signals SYSFAILSYSRESET*, and ACFAIL* for signalling exceptions or status. TSYSFAIL*, SYSRESET*, and ACFAIL* signals are connected to thCPU board via buffers, switches, and Universe II.

SYSFAIL* Universe II may be programmed to generate local interrupts whenSYSFAIL* signal is active.

SYSRESET* input

The VMEbus SYSRESET* signal is only monitored by the CPU boardSW5-3 is set appropriately: OFF = enabled (default “OFF”).

SYSRESET* output

A SYSRESET* is generated by PPC/PowerCore-6603/4 if SW7-4 isappropriately: OFF = enabled (default “OFF”). The reason for the SYRESET* generation may be one of the following:

• the front panel reset key is active,

• the Universe II SW_SYSRESET bit is set in the MISC_CTL regist(see “PCI-to-VME bridge – Universe II” Data Sheets),

• the watchdog timer generates a reset,

• power-up occurs,

• or the voltage sensor detects a low voltage on-board.

ACFAIL* The ACFAIL* line can be mapped to a PCI interrupt (INTB#). ThCPU board can never drive the ACFAIL* signal.



3.10.3 VMEbus Master Interface

PCI images Universe II transfers data to the VMEbus within a maximum of four pro-grammed PCI slave images. Each image can be enabled or disabled inde-pendently. Posted write accesses are also programmable.



E

portsn-

(see9).

med un-

to-

Access address The VMEbus access address is programmable via Universe II. Both thestart and the end address of the accessible VMEbus address range areprogrammable in 4-Kbyte or 64-Kbyte increments (see “PCI-to-VMbridge – Universe II” Data Sheets).

Data transfer size The VMEbus master interface supports all 32 data lines. It sup64-bit (MBLT), 32-bit, 16-bit, and 8-bit data transfers as well as ualigned data transfers (UAT) and read-modify-write transfers.

The VMEbus address range is the largest portion of the address mapsection 3.1 “PPC/PowerCore-6603/4 Address Map” on page 3Universe II maps the PCI bus transaction to the maximum programVMEbus data width. According to this data width, data are packed orpacked.For further information on the read-modify-write support, see “PCI-VME bridge – Universe II” Data Sheets.

Table 45 VMEbus master transfer cycles def. for data bus width D32

Transfer type D31…24 D23…16 D15…08 D07…00

Byte on odd addressByte on even address x

x

Word x x

Long-word x x x x

Unaligned wordUnaligned long-word AUnaligned long-word B

xxxx

xxx x

Read-modify-writebyte on odd addressbyte on even addresswordlong-word x x

xxx

x

xx



data asrs.

and

ivi-nallyierbled or

Access modes For VMEbus master access, A32/A24/A16 accesses, and CR/CSR ac-cesses are allowed. Single-cycle transfers or blocktransfers are program-mable.Universe II allows data and program accesses in the privileged (supervi-sor) or non-privileged (user) mode. Additionally, Universe II supports 2user defined address modifier codes. Every access mode (address modifi-er) can be separately enabled or disabled within the PCI slave image.

3.10.4 VMEbus Slave Interface

Slave images Within a maximum of 4 programmed VMEbus slave images Universe IIcan be accessed from the VMEbus. Every image can be enabled or dis-abled independently. Prefetched read accesses and posted write accessesare also programmable.

Access address The access address of the shared RAM for other VMEbus masters is pro-grammable via Universe II. Both the start and the end address of theshared RAM are programmable in 4-Kbyte or 64-Kbyte increments (see“PCI-to-VME bridge – Universe II” Data Sheets).

Data transfer size The VMEbus slave interface for the shared RAM supports all 32lines. It supports 64-bit (MBLT), 32-bit, 16-bit, and 8-bit data transferswell as unaligned data transfers (UAT) and read-modify-write transfe

Access modes For VMEbus slave access to the shared RAM, A32/A24/A16CR/CSR accesses are allowed.Universe II allows accesses in the privileged (supervisor) or non-prleged (user) mode for both data and program accesses. AdditioUniverse II provides support for two user defined Address ModifCodes. Each access mode can (address modifier) be separately enadisabled within the slave images.

Table 46 VMEbus master transfer cycles defined for data bus width D16

Transfer type D31…24 D23…16 D15…08 D07…00

Byte on odd addressByte on even address x

x

Word x x

Read-modify-writebyte on odd addressbyte on even addressword

xx

x

x


VMEbus Slot-1 Hardware

ft-

mo-MAy bem-

wide

the bytemnc-

nd

3.10.5 DMA-Controller

Universe II uses a DMA controller for high-performance data transfer be-tween the PCI bus and the VMEbus. Source, destination, length of trans-fer, and transfer protocol are programmable in several registers ofUniverse II.

Direct and linked list DMA

The DMA controller can be set to one of the following modes:

• direct DMA

• or linked list DMA.

In direct DMA mode the DMA registers are programmed directly by soware. In linked list mode Universe II loads the registers from the system mery. The block of the system memory containing the values for the Dregisters is called command packet. The command packets malinked. If all linked command packets are executed, the DMA is coplete.

16-entry FIFO For increased performance the DMA uses a 16-entry deep, 64-bitbidirectional FIFO.

3.11 VMEbus Slot-1

PPC/PowerCore-6603/4 may be used as system controller whenboard is plugged into slot-1 or when it is forced to be slot-1 deviceswitch setting of SW7-1 and SW7-2, or when programmed as syscontroller. The slot-1 functions are also called system controller futions.

Note: MalfunctionIf not on an active backplane, remove the jumper on the backplane connecting BG3IN* andBG3OUT* for the PPC/PowerCore-6603/4 slot.

• assemble the jumpers for BG3IN* and BG3OUT* on lower ahigher slots on the backplane where no board is plugged.


Hardware VMEbus Slot-1

uired

K

e-ta

into(see

bus-si-

edis

illille

t be-ent

atthepri-

Slot-1 (system controller) functions

When the CPU board is a slot-1 device (see table 47 “Slot-1 functions”on page 71), the hardware of PPC/PowerCore-6603/4 sets up the reqsystem controller functions:

• enable the arbiter

• drive SYSCLK to the VMEbus (see section 3.11.2 “The SYSCLDriver” on page 72),

• drive floating bus grant levels 0, 1, 2, and 3,

• and allow the Universe II bus timer to terminate VME cycles (timout), if it is enabled (see “PCI-to-VME bridge – Universe II” DaSheets).

3.11.1 Slot-1 Detection

Auto-detection PPC/PowerCore-6603/4 detects automatically whether it is pluggedslot 1 and if the switches SW7-1 and SW7-2 are set accordingly table 11 “Switch Settings” on page 11).

The board’s slot-1 auto-detection mechanism probes the VMEbus grant-in-level-3 pin (BG3IN*) during power up to see whether it is posble to pull this signal down to a low-signal level.

• When PPC/PowerCore-6603/4 is plugged into slot 1, it will succein pulling the VME signal to a low-signal level, because BG3IN* floating on slot 1. Hence, the CPU board detects slot 1.

• When PPC/PowerCore-6603/4 is not plugged into slot 1, it wreceive the BG3IN* from a board plugged into a lower slot. It wfail trying to pull the VME signal to a low-signal level. Hence, thCPU board detects not being plugged into slot 1.

Manual slot-1 The following situation may cause PPC/PowerCore-6603/4 to detecing plugged into slot-1 although actually being plugged into a differslot:

A VMEbus system begins with the highest daisy-chain priorityslot 1, the left most slot. The higher the slot number, the lower daisy-chain priority. As the slots move right they lose daisy-chain

Table 47 Slot-1 functions

SW7-1 SW7-2 Slot-1 function

OFF don’t care automatic detection

ON OFF system controller disabled

ON ON system controller enabled


VMEbus Slot-1 Hardware

7-2

stemII”

rationa-

LKitryand

uto-tec-

heon-

ority, so slot 2 has higher daisy-chain priority than slot 3, and slot 3has higher daisy-chain priority than slot 4, and so on. When a boardwhich is not compliant with ANSI-VITA 1-1994 is plugged into aslot with higher daisy-chain priority, auto-detection may fail. This oc-curs if the higher daisy-chain priority board does not drive the bus-grant-out-level-3 (BG3OUT*) on the VMEbus to the high-signal lev-el as defined by ANSI-VITA 1-1994.

In this situation PPC/PowerCore-6603/4 probes its BG3IN* at a low-sig-nal level and concludes that slot 1 is detected. However, the conclusiondoes not fit the actual system setup. To prevent any mismatch you can en-able or disable the slot-1 function manually:

1. Disable the auto-detection by setting SW7-1 appropriately: ON =autodetection disabled (default “OFF”)

2. Enable or disable the slot-1 functions manually by setting SWappropriately: ON = slot-1 function enabled (default “OFF”).

Programmable slot-1

The MASC_CTL register can be used to program the board as sycontroller. For more information see “PCI-to-VME bridge – Universe Data Sheets.

Caution If more than one system controller is active in the VMEbus system,the board or other VMEbus participants can be damaged.

Slot-1 status The status of the slot-1 detection or manual mode SW7-2 configumay be read via the Universe II MISC_STL register. For more informtion see “PCI-to-VME bridge – Universe II” Data Sheets.

3.11.2 The SYSCLK Driver

The CPU board contains all necessary circuits to support the SYSCsignal. The output signal is a stable 16-MHz signal. The driver circufor the SYSCLK signal can source a current of 32 mA at high level sink a current of 64 mA at low level. The SYSCLK signal will be enabled if slot-1 has been detected (by adetection or because of switch setting, see section 3.11.1 “Slot-1 Detion” on page 71) or set by software. SYSCLK will be driven until tboard is powered down or low voltage is detected at the low voltage mitor.


Hardware VMEbus Arbitration

i-

ccessism

see

bus

desto-

Toity

3.11.3 VMEbus Timer

Universe II has a VMEbus timer to terminate VME transfers generating abus error when no acknowledge can be detected after a programmabletimeout period.In addition to the VMEbus timer, Universe II provides a VMEbus arbitertimer. This timer can only be enabled when the CPU board provides sys-tem controller functions. The timeout periods can be configured in theregister MISC_CTL within Universe II (see “PCI-to-VME bridge – Unverse II” Data Sheets).

3.12 VMEbus Arbitration

Each transfer to or from an off-board address causes a VMEbus acycle which is carried out in accordance with the arbitration mechandefined for the VMEbus. PPC/PowerCore-6603/4 includes:

• a VMEbus arbiter so that it may act as slot-1 system controller (section 3.11 “VMEbus Slot-1” on page 70)

• and a VMEbus requester so that it may access external VMEresources.

3.12.1 VMEbus Arbitration Modes

PPC/PowerCore-6603/4 includes one of the following arbitration moprogrammable via the Universe II MISC_CTL register (see “PCI-VME bridge – Universe II” Data Sheets):

• a 4-level fixed-priority arbitration mode,

• a single-level arbitration mode,

• or a 4-level round-robin arbitration mode (default).

Note: According to ANSI-VITA 1-1994, the arbiter must be enabledif the CPU board is located in slot 1 of the VMEbus backplane. Itmust be disabled if the CPU board is located in any other slot.

Single-level arbitration is a subset of fixed-priority arbitration mode. achieve single-level arbitration mode, set Universe II to fixed-priormode. The VMEbus mastership is only granted on level 3.


VMEbus Arbitration Hardware

busration

en-lingpro-

ess

bust busl (e.gre

E

wn-ata.E

3.12.2 VMEbus Requester

PPC/PowerCore-6603/4 includes a VMEbus requester so that it may ac-cess external VMEbus resources.

Request level selection

The request level is programmable via the Universe II MAST_CTL reg-ister (see “PCI-to-VME bridge – Universe II” Data Sheets).

Note: Note that the selection of the VMEbus request level does notdepend on the VMEbus arbiter located in Universe II.

3.12.3 VMEbus Release Modes

PPC/PowerCore-6603/4 provides several software-selectable VMErelease modes to release VMEbus mastership. The bus release opeis independent of the fact whether the on-board VMEbus arbiter isabled and independent of the VMEbus arbitration level. Easy handand use of the VMEbus release modes is provided by Universe II grammable in the MAST_CTL register.Before the bus is released a read-modify-write (RMW) cycle in progris always completed.

Release on request (ROR)

In the ROR mode bus mastership is released when another VMEboard requests bus mastership while the CPU board is the currenmaster. Ownership of the bus may be assumed by another channeUniverse II DMA channel) without rearbitration on the bus, if there ano other requests pending.For information on programming the ROR mode, see “PCI-to-VMbridge – Universe II” Data Sheets.

Release when done (RWD)

In the RWD mode the VME master interface releases the VMEbus oership, when the channel accessing the VMEbus has transferred its dFor information on programming the RWD mode, see “PCI-to-VMbridge – Universe II” Data Sheets.


Hardware Ethernet Interface

trol-

r –

twoace

. Afterset

3/4

ng

con-ds

ize

3.13 Ethernet Interface

PPC/PowerCore-6603/4 offers a Local Area Network (LAN) interface atthe front panel. This LAN interface is based on:

• an Ethernet controller located at the PCI bus (see “Ethernet Conler – LAN 21140A” Data Sheets),

• an Ethernet interface adapter (see “Ethernet Interface AdapteLXT901” Data Sheets)

• and a filter transformer which routes the two receive and the transmit lines of the 10Base-T interface to the Ethernet interfadapter.

Ethernet address The unique Ethernet address is permanently stored at the ID-ROMpower-on the Ethernet address is copied into the NVRAM at off1C1216 where it can be read by the software.

Features of the Ethernet interface

The Ethernet interface provides the following features:

• Compatibility with IEEE 802.3/Ethernet

• Data rate of 10 Mbit per second

• DMA capability

• Interrupt generation

3.13.1 Ethernet Controller

Features The fast Ethernet LAN controller implements the following features:

• supporting the 10 Mb/s Ethernet interface of PPC/PowerCore-660

• direct interface to the PCI bus

• full-duplex operation and external and internal loopback capability

• supporting a variety of flexible address filtering modes (includiperfect, hash tables, inverse perfect, and promiscuous)

• large independent receive and transmit FIFOs allow the Ethernet troller to efficiently operate in systems with longer latency periowithout requiring an additional on-board memory

• on-chip direct memory access (DMA) with programmable burst sprovided for low CPU utilization

• intelligent arbitration between DMA channels

• unlimited PCI burst


Ethernet Interface Hardware

ip-

s

e

at

see.

eanstputs

n theler – –

• supporting big or little endian byte ordering for buffers and descrtors

• JTAG-compatible test-access port with boundary-scan pins

• compliance with IEEE 802.3, ANSI 8802-3, and Ethernet standard

• AUI interface with 7 wires routed to PN15 (factory option) (sefigure 2 “PN15 Connector Pinout” on page 18)

CSR base address

The CSR base address of the Ethernet controller is locatedFE80.000016.

Interrupt The Ethernet controller uses INTA # for interrupting the CPU (table 28 “Default PPC/PowerCore-6603/4 interrupt map” on page 45)

General purpose register

The Ethernet controller controls the Ethernet interface adapter by mof the general purpose register. Inputs can only be read, whereas ouperform read/write capability.

Note: For enabling the loopback mode of the Ethernet adapter, GP3(LI) may be programmed as output and set according to theloopback condition. If GP3 is programmed as input (default) alwaysthe value 1 will be read.

Data sheets For more information on programming the Ethernet controller and ocontrol pins of the Ethernet interface adapter, see “Ethernet ControlLAN 21140A”, Data Sheets or see “Ethernet Interface AdapterLXT901” Data Sheets respectively.

3.13.2 Ethernet Interface Adapter

Features The Ethernet interface adapter integrates:

• Manchester encoder/decoder,

• 10Base-T compliant transceiver,

• selectable termination impedance,

• and LED drivers.

Table 48 General purpose register of the Ethernet controller

GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0

Direction Input Input Input Input Input Output Output Output

Signal name JAB PLR RCMPT RLD LI LBK NTH UTP


Hardware PCI-to-ISA Bridge and IDE Interfaces

pro-port32-

are

59 forI in-

ro-able

ogic

0,ntly,

ces,

The Ethernet interface adapter supports standard and full-duplex opera-tion and connects the Ethernet controller with the RJ45 connector via atransformer. Furthermore, it controls the Ethernet LED at the front panel(see section 2.4 “Front Panel” on page 13).

3.14 PCI-to-ISA Bridge and IDE Interfaces

PCI and ISA master/slave interface

The PCI-to-ISA bridge provides:

• a PCI master/slave interface up to 33 MHz

• and an 7.5-MHz or 8.25-MHz ISA master/slave interface.

IDE interfaces In addition, the PCI-to-ISA bridge has two fast IDE interfaces with grammed I/O (PIO) and bus master functions. The IDE interfaces supup to PIO mode 4 timings, transfer rates up to 22 Mbyte/s and an 8 *bit buffer for bus master IDE PCI burst transfers. The IDE interfacesonly available at a 5-row VMEbus P2 connector (factory option).

Timer/counter The PCI-to-ISA bridge integrates a 16-bit system timer/counter.

Interrupt controller

In addition, the PCI-to-ISA bridge includes 2 interrupt controllers 82Cwhich support 14 interrupts and can be programmed independentlyedge or level sensitivity. 2 steerable interrupt lines and 4 steerable PCterrupts are provided.

DMA functions The PCI-to-ISA bridge has 2 DMA controllers and 7 independently pgrammable channels. The PCI-to-ISA bridge also provides 2 steerDMA channels and a fast DMA with 4-byte buffer.

Chip select decode and NMI

The PCI-to-ISA bridge integrates chip select decoding and a control lgenerating non-maskable interrupts (NMIs).

Multifunction device

The PCI-to-ISA bridge is a multifunction device: the bridge is functionthe IDE interfaces are function 1. Both can be configured independein compliance with the PCI Local Bus Specification 2.0.

Data sheet For more information on the PCI-to-ISA bridge and the IDE interfasee “PCI-to-ISA Bridge – PIIX 82371FB” Data Sheets.


PCI-to-ISA Bridge and IDE Interfaces Hardware

ctor

andd to

P2

in-g.m to

3.14.1 PCI-to-ISA Bridge

The PCI-to-ISA-bridge connects the slower I/O devices to the PCI bus.

Devices on the ISA bus

The following devices are located on the ISA bus:

• serial interface,

• NVRAM and RTC,

• CIO for internal control,

• DRAM and cache configuration register (DCCR),

• and PN15 connector (factory option) for ISA extension.

ISA base address The ISA base address of the PCI-to-ISA bridge is FE00.000016.

3.14.2 IDE Interfaces

The IDE interfaces are available only at the 5-row VMEbus P2 conne(factory option).

IDE devices PPC/PowerCore-6603/4 supports up to 4 IDE devices: two primarytwo secondary IDE devices. The signals of the IDE interface are routethe 5-row VMEbus P2 connector rows Z and D (see figure 4 “5-RowConnector Pinout, Row Z and D” on page 21).

3.14.3 Interrupt Controller

The figure below shows the interrupt structure of the CPU board. Theterrupt controller of the PCI-to-ISA bridge is used for interrupt routinThe PCI-to-ISA bridge collects the possible interrupts and passes thethe CPU via the INTR line. An NMI is only generated:

• when a PCI system error (PCI signal SERR# active) occurs,

• when a watchdog timeout occurs,

• or when the ABORT key is pressed.

All interrupts can be disabled independently.


Hardware PCI-to-ISA Bridge and IDE Interfaces

Figure 10 PCI-to-ISA bridge interrupt structure

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IRQ1

IRQ12

IRQ6

IRQ7

IRQ8#

IRQ4IRQ0

IRQ1

IRQ4

IRQ3

IRQ6

IRQ7

IRQ5

IR0

IR1

IR4

IR3

IR6

IR7

IR5

IR0

IR1

IR4

IR3

IR6

IR7

IR5

IRQ8#

IRQ9

IRQ11

IRQ10

IRQ13

IRQ14

IRQ12

IRQ15

IR2

IRQ0

IRQ3IRQ11

IRQ14 and IRQ15

IRQ5

IRQ10

IRQ router

User available

INTA #

INTB #

INTC #

INTD #

INTR

NMI

INTR

IR2

System timer

IDE interface

Master 8259 programmable interrupt controller

Slave 8259 programmable interrupt controller

PCI-to-ISA bridge

/INT

/MCP

NMI

/MCP

PowerPC-to-PCI bridge

PowerPC CPU

IRQ0IRQ1IRQ8#IRQ9IRQ10IRQ11IRQ12IRQ13IRQ14IRQ15IRQ3IRQ4IRQ5IRQ6IRQ7

Timer 1/counter 0User availableCIO CascadeINTA #INTB #User availablereservedPrimary IDE interfaceSecondary IDE interfaceIINTC #Serial portINTD #User availableUser available

IRQ Priority (in descending order)

User available

User available

User available

CIO

Serial port

IRQ5

IRQ10

IRQ11

IRQ3


Real-Time Clock / Non-Volatile RAM Hardware

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3.15 Real-Time Clock / Non-Volatile RAM

The real-time clock (RTC) and the non-volatile RAM (NVRAM) arehoused in one device including a battery backup.

Features of the battery

The battery is mounted as snaphat on top of the device with a direct con-nection to its power supply. For information on exchanging the battery,see section 2.1 “Installation Prerequisites and Requirements” on pagWhen the power fails, the device is automatically deselected and chainto write-protected mode.

Address space The RTC/NVRAM address space is divided into three parts.

Address access to the RTC/NVRAM

The access to the RTC/NVRAM is 8-bit wide and indirect.To access a location within the device:

1. write the lower address byte to address FE00.007316 (write-only),

2. write the higher address byte to address FE00.007516 (write-only),

3. and read or write data from or to address FE00.007716.

NVRAM Since the last 16 bytes are used for the RTC or unused, the NVRAMa capacity of 8 Kbyte — 16 bytes. The complete address space oNVRAM is 000016 … 1FF016.

User defined area

The user may store important data in the user defined area ofNVRAM.

Configuration area

The NVRAM configuration area is used for internal configuration data

Note: The user must not change the values stored in theconfiguration area.

Table 49 Address space of the RTC/NVRAM

Address range Access

000016… 1BFF16

NVRAM user defined area

1C0016… 1FF016

NVRAM configuration area

1FF116… 1FF716

unused

1FF816… 1FFF16

RTC registers


Hardware PPC/PowerCore-6603/4 Parameters and Timers – CIO

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Features of the RTC

The on-board RTC maintains accurate time and date based on its owncrystal.

Data sheet For more information on the registers and the operation of the RTC, see“Real-Time Clock and NVRAM – RTC/NVRAM M48T58” Data Sheets

3.16 PPC/PowerCore-6603/4 Parameters and Timers – CIO

The configuration and status information for several PPC/PowerCore-6603/4 parameters and timers are accessible via an 8-bit register, the CIOdata and timer registers, and the NVRAM configuration area. They are alllocated on the ISA bus.

3.16.1 Parameters

Some of the following parameters can only be read, others can be readand written:

– DRAM reading the DRAM and cache configuration register (see table“DRAM and cache configuration register, bits [5…0]” on page 53)

– Cache reading the DRAM and cache configuration register (see tab“DRAM and cache configuration register, bits [7…6]” on page 49)

– Boot flash reading the boot flash size on CIO port A, bit 1 (see table 41 “CIO podata register, bits [7] and [3…0]” on page 60)

– User flash writing parameters of the user flash devices via CIO port A (see tab“CIO port A data register, bits [7] and [5]” on page 58 and see table“CIO port A data register, bits [7] and [3…0]” on page 60)

– Boot parameters

reading the boot parameters from the NVRAM (see section 3.15 “RTime Clock / Non-Volatile RAM” on page 80)

– ID-ROM the ID-ROM includes different internally used parameters.

– BUSMODE The PMC BUSMODE signals can be set and read via CIO port B table 53 “CIO port B data register, bits [5…3] and [2…1]” on page 85

3.16.2 Timers

A 64-bit counter is available in the processor. A system timer is proviin the PCI-to-ISA bridge (counter 0, IRQ 0). Three 16-bit timers are cessible via the CIO (see “CIO Counter/Timer – CIO Z8536” DaSheets).

CIO counters and timers

The CIO offers 3 independently programmable 16-bit timers with 500resolution which can also be used as counters (see “CIO Counter/TimCIO Z8536” Data Sheets).


PPC/PowerCore-6603/4 Parameters and Timers – CIO Hardware

Hz

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15

The peripheral clock of the CIO device is connected

• to a 4.125 MHz source when the PCI clock frequency is 33 MHz

• or to a 3.75 MHz source when the PCI clock frequency is 30 M(120-MHz processor).

3.16.3 CIO

PPC/PowerCore-6603/4 integrates one CIO which controls internal nals and devices. The CIO includes the 3 independently programmports A, B, and C.

Features of the CIO

The CIO contains:

• 2 independent 8-bit ports (ports A and B),

• one special-purpose 4-bit port (port C),

• and 3 independently programmable 16-bit timers which can alsoused as counters.

Base address FE00.030016

IRQ The interrupt request output of the CIO uses IRQ8#.

Data sheet For information on programming the timers and the ports, see Counter/Timer – CIO Z8536” Data Sheets.

3.16.4 CIO Port A Data Register

VPP_CTRL see table 40 “CIO port A data register, bits [7] and [5]” on page 58 ortable 41 “CIO port A data register, bits [7] and [3…0]” on page 60

ISA_IDENT(R)

ISA_IDENT indicates whether ISA devices are installed at the PNconnector (see figure 2 “PN15 Connector Pinout” on page 18).

= 0 ISA devices installed.

= 1 (default) no ISA devices installed.

Table 50 CIO port A data register, bit [6]

FE00.030216

Bit 7 6 5 4 3 2 1 0

Value VPP_CTRL

ISA_IDENT

BOOT_ SIZE

re-served

FLSH_SEL [1…0]

FLSH[A21…A20]


Hardware PPC/PowerCore-6603/4 Parameters and Timers – CIO

sig-

BOOT_SIZE see table 40 “CIO port A data register, bits [7] and [5]” on page 58

FLSH_SEL[1…0] and FLSH[A21 … A20]

see table 41 “CIO port A data register, bits [7] and [3…0]” on page 60

3.16.5 CIO Port B Data Register

ID_SCL(W)

ID_SCL controls the ID-ROM SCL signal (I2C bus) (default setting = 1)

ID_SDA(R/W)

ID_SDA controls and indicates the status of the ID-ROM serial data nal (I2C bus) (default setting = 0)

BUSMODE [4…2] and BUSMODE [1…0]

see table 53 “CIO port B data register, bits [5…3] and [2…1]” on page 85

WDNMI see table 33 “CIO port B data register, bit [0]” on page 51

3.16.6 CIO Port C Data Register

TRWD see table 32 “CIO Port C data register, bit [2]” on page 50

Table 51 CIO port B data register, bits [7…6]

FE00.030116

Bit 7 6 5 4 3 2 1 0


Table 52 CIO port C data register, bits [1…0]

FE00.030016

Bit 7 6 5 4 3 2 1 0

Value used as masking bits for writeaccesses to bit 3…0 (e.g.: if bit 4is 1, bit 0 cannot be written)

re-served

TRWD LED[1…0]


Serial I/O Port – SCC Hardware

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LED [1…0](R/W)

LED [1…0] controls the user LED U at the front panel.

= 00 2 User LED U is off.

= 01 2 User LED U is green.

= 10 2 User LED U is red.

= 11 2 (default) User LED U is off

3.17 Serial I/O Port – SCC

The serial I/O port is implemented by using a serial communication con-troller (SCC).

Features of the SCC

The serial communication controller (SCC)

• runs with all existing 16C450 software,

• and provides

– programmable baudrate generator,

– standard asynchronous communication bits,

– and fully programmable serial interface characteristics.

Clock input The peripheral clock input of the SCC is driven by a 1.8432-MHz clo

IRQ The interrupt request of the SCC is connected to the IRQ4 input ofPCI-to-ISA-bridge. It is low active.

SCC base address

The SCC base address is FE00.03F816.

RS-232 interface The serial I/O interface is implemented as RS-232 interface, availathe front panel. The following 4 control lines are also available via VMEbus P2 connector: RXD, TXD, RTS, and CTS.

Serial I/O configuration

For more information on the configuration of the serial port, see “SeI/O Port – TL16C550C” Data Sheets.

Connector pinout For the connector which is available at the front panel and the cotors’ pinout, see section 2.6 “Serial I/O Port” on page 15 and section“VMEbus P2 Connector Pinout” on page 20.

Data sheet For more information on the SCC, see “Serial I/O Port – TL16C55Data Sheets.


Hardware PMC Slots

3.18 PMC Slots

PPC/PowerCore-6603/4 provides 2 PMC slots compliant withIEEE P1386 ("Draft Standard Physical and Environmental Layers forPCI Mezzanine Cards: PMC"). For more information see section 2.8“PMC Slots” on page 16.

3.18.1 Busmode

By the BUSMODE [4…0] signals the host gets information on:

• the presence of PMC modules (= card)

• and the logical protocol of the PMC modules.

Via the BUSMODE [4…2] signals, which are driven by the host, the PMCmodules get the information whether a host is present. The answer of thePMC modules is transferred by the signal lines BUSMODE [1…0] . Allsignals are compliant with IEEE P1386/Draft 2.0.

Note: The BUSMODE [4…2] signals must be set accordingly. IfPort B is not initialized, the PMC modules do not detect the host andtherefore, they do not work. Per default, the firmware initializes theBUSMODE [4…2]signals.

ID_SCL and ID_SDA

see table 51 “CIO port B data register, bits [7…6]” on page 83

BUSMODE[4…2](R/W)

The bits 5…3 indicate the meaning of the 3 output signals BUSMODE[4…2] which are routed to both PMC slots.

= 000 2 Card Present Test: The cards at PMC slot 1 and 2 return "Card Present",if they are plugged into the slot and no bus protocol is used.

=001 2 (default) Card Present Test: The cards at PMC slot 1 and 2 return "Card Present" ifthey are PCI capable and PCI protocol is used.

= 010 2 Card Present Test: The cards at PMC slot 1 and 2 return "Card Present" ifthey are PCI capable and SBus protocol is used.

Table 53 CIO port B data register, bits [5…3] and [2…1]

FE00.030116

Bit 7 6 5 4 3 2 1 0



PMC Slots Hardware

= 0112 Reserved

= 1002 Reserved

= 1012 Reserved

= 1102 Reserved

= 1112 No host present.

BUSMODE[1…0](R)

The PMC cards indicate their presence to the given protocol (e.g.PCI protocol, SBus protocol) by the message "Card present" (default set-ting = 002). BUSMODE [1] is connected with PMC slot 2,BUSMODE [0] with PMC slot 1.

= 0= 1

Card present. No card present.

WDNMI see table 33 “CIO port B data register, bit [0]” on page 51


Please Note…

The PowerBoot Instruction Set is an integral part of the PPC/PowerCore-6603/4 Reference Guide (P/N 204421), which is packaged separately.

The PowerBoot Instruction Set will always be shipped together with theReference Guide.

Please:

☞ Insert the PowerBoot Instruction Set (P/N 204525) nowinto the PPC/PowerCore-6603/4 Reference Guide(P/N 204421).

☞ Remove this sheet.

PPC/PowerCore-6603/4

PowerBoot (= PowerBoot Instruction Set)

4 PowerBoot (= PowerBoot Instruction Set)


PowerBoot (= PowerBoot Instruction Set)


PowerBoot for PPC/PowerCore-6603/4

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5 PowerBoot for PPC/PowerCore-6603/4

This chapter describes the board specific commands of PowerBoot.

Command overview

PowerBoot includes the following board specific commands:

• command to manually map the PCI bus devices at PMC slot 1 or

“PMCPCI – Mapping PMC Modules” on page 93,

• command to restart the CPU board:

“RESET – Restarting the Board” on page 95,

• command to set and display auto boot after power-on:

“SETBOOT – Editing Auto Boot Parameters” on page 96,

• command to turn the user LED at the front panel ON or OFF:

“USERLED – Setting User LED” on page 104.

• command to enable or disable the VMEbus system controller oindicate its current status:

“VMESYS – Enabling VMEbus System Controller” on page 107.

• commands to initialize an A32/D32 master or slave interface to VMEbus:

“VMEMST – Opening an A32/D32 Master Window” on page 10“VMESLV – Opening an A32/D32 Slave Window” on page 106.

Supports and Requirements

PowerBoot supports up to 9-Mbyte on-board flash memory:

• 1-Mbyte boot flash for PowerBoot, OpenFirmware, or other opeing systems, which can always be accessed,

• and an 8-Mbyte user flash which can be accessed in 8 windows consisting of 1 MByte.

The PowerBoot flash memory must be located at the CPU addFFF0.000016, because the PPC/PowerCore-6603/4 CPU vectors toaddress FFF0.010016 after an active /HRESET. Additionally, this flasmemory has to be visible to the CPU at all times (no bank switching).


PPC/PowerCore-6603/4 Address Map PowerBoot for PPC/PowerCore-6603/4

5.1 PPC/PowerCore-6603/4 Address Map

The following table lists the default addresses of the PPC/Power-Core-6603/4 board mapped by PowerBoot.

Table 54 PPC/PowerCore-6603/4 address map seen from the CPU

Address Device

0000.000016 … 00FF.FFFF 16

EDO RAM: on-board memory

0100.0000 16 … 3FFF.FFFF 16

memory modules

4000.0000 16 … 7FFF.FFFF 16

PowerPC-to-PCI bridge

8000.0000 16 … FDFF.FFFF16

PCI memory: VME windows

FE00.0000 16 PCI-to-ISA bridge: base address of ISA registers

FE00.0073 16 and FE00.0074 16

1)ISA RTC/NVRAM: low-address byte port

FE00.0075 16 high-address byte port

FE00.0077 16 data byte port

FE00.0300 16 … FE00.0303 16

CIO parallel port addresses

FE00.0308 16 DCCR

FE00.0310 16 Chip select signal (PN15 connector)

FE00.03F8 16 … FE00.03FF 16

Serial console: I/O port

FE80.0000 16 Ethernet controller: base address of CSR registers

FE81.0000 16 Universe: base address of CSR registers

FEC0.0000 16 PCI bus: configuration address register (CAR)

FEE0.0000 16 configuration data register (CDR)

FEF0.0000 16 Interrupt acknowledge cycle

FFE0.0000 16 … FFEF.FFFF16

User flash: window for devices 1, 2, 3, 4

FFF0.0000 16 … FFF3.FFFF 16

Boot flash (default: 256 Kbyte):

device 1

FFF4.0000 16 … FFF7.FFFF 16

device 2


PowerBoot for PPC/PowerCore-6603/4 PMCPCI – Mapping PMC Modules

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5.2 PMCPCI – Mapping PMC Modules

PMCPCI manually maps a user mounted PMC module to any location inthe PCI addressing space by defining its PCI I/O space address and/or itsPCI memory space address. The PCI addressing space is divided into twoareas:

At PPC/PowerCore-6603/4 the addresses for the local Ethernet devicesand the Universe VMEbus interface are already mapped to the PCI I/Ospace (see table 54 “PPC/PowerCore-6603/4 address map seen froCPU” on page 92).

FFF0.000016 … FFF7.FFFF 16

Boot flash (fact. opt.: 512 Kbyte):

device 1

FFF8.0000 16 … FFFF.FFFF 16

device 2

1. If you address the NVRAM/RTC via FEOO.007416, the address FEOO.007016 will beoverwritten (see “PCI-to-ISA Bridge – PIIX 82371FB”, Data Sheets). To avoid this, address theNVRAM/RTC via FE00.007316.

Table 54 PPC/PowerCore-6603/4 address map seen from the CPU (cont.)

Address Device

Table 55 PCI addressing spaces

PCI addressing space Address

PCI addressing space seen from the

PCI I/O space FE80.000016…FEBF.FFFF16

CPU

0080.000016…00BF.FFFF16

PCI bus master

PCI memory space 8000.000016…FCFF.FFFF16

CPU or PCI bus mas-ter


PMCPCI – Mapping PMC Modules PowerBoot for PPC/PowerCore-6603/4

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Syntax PMCPCI PmcModule PciIOSpaceAddr PciMemSpaceAddr

PmcModuledefines the PMC module to be mapped:

– 1 = PMC module 1

– 2 = PMC module 2

PciIOSpaceAddrdefines the PCI I/O space address seen from the PCI bus. If the PCspace address is set to 0000.000016, it will be ignored.

PciMemSpaceAddrdefines the PCI memory space address seen from the PCI bus. PCI memory space address is set to 0000.000016, it will be ignored.

Description PMCPCI checks the capabilities of every device.

• If the PCI device mounted on a PMC module supports both addring spaces, the PCI bus device register at offset 1016 is used for thePCI I/O space and the PCI bus device register at offset 1416 is usedfor the PCI memory space. In this case both addresses given buser are programmed in the PCI bus device.

• If a PCI bus device mounted on a PMC module does not support addressing spaces, only the supported one will be used even if addressing spaces have been defined.

• If a PCI bus device mounted on a PMC module is able to support addressing spaces, but only one should be used, set the addressshould not be used to FFFF.FFFF16.

• If no PCI bus device is installed, one of the following messagappears:

PMC 1/2 modules:Error: Can’t set base-address of PMC1

PMC 1/2 modules:Error: Can’t set base-address of PMC2

Example In the following example a PMC module at PMC slot 1 is mapped to thePCI memory space 0082.000016 and to the PCI bus memory space8000.000016. A user application can access the PCI bus device CSRregisters via the PowerPC CPU at the PCI I/O space addressFE82.000016 and at the PCI memory space address 8000.000016.


PowerBoot for PPC/PowerCore-6603/4 RESET – Restarting the Board

5.3 RESET – Restarting the Board

The restarting of the CPU board via RESET is not as strong as a power-on reset. RESET incites only a jump to the /HRESET exception vector atFFF0.010016.

Syntax RESET

Description All devices based on the PCI bus will keep their PCI configuration spaceheader region, e.g. the Ethernet controller will keep its default base ad-dress. But the EDO RAM, the PCI-to-ISA bridge, the serial console, theCIO parallel port, the Ethernet controller, the VMEbus interface etc. willbe initialized. The L1 cache and L2 cache will be flushed and invalidated.

Example PowerBoot> RESETInit serial at address: 0xFE0003F8Init CIO at address: 0xFE000300Init Ethernet Controller at address: 0xFE800000Init UNIVERSE VMEbus device at address: 0xFE810000PowerCore is -NOT- VMEbus System Controller (SYSCON=0)Found CPU603ev, PVR=00070201, CPU clock: 166MHz, Bus clock: 66MHzDRAM EDO mode enabled, DRAM ECC mode disabledOnboard DRAM : 16MB, 0x00000000..0x00FFFFFFInit DRAM Module 1: noneInit DRAM Module 2: noneInit DTLB/ITLB for block translation, enable MMUInit L1-IcacheInit L1-DcacheInit L2-Cache, found 2 Banks, 512 kByte cacheInit exception vectors starting at address: 0x00000100

PowerBoot> PowerBoot> PowerBoot> PMCPCI 1 00820000 80000000

PMC1/2 modules:PMC1, PCI address 0x00820000, Base Reg. 0x10, PCI I/O space, Master enablePMC1, PCI address 0x80000000, Base Reg. 0x10, PCI MEM space, Master enableDevice ID = 0x0009; Vendor ID = 0x1011; Status = 0x0280; Command = 0x0007; Base Class= 0x02; Sub Class = 0x00; Prg. Inter= 0x00; Rev. ID = 0x20; BIST = 0x00; Header Typ= 0x00; Latency Ti= 0x00; Cache Line= 0x00; base addr0= 0x00820001, base addr1= 0x80000000; Max Lat = 0x28; Min Gnt = 0x14; IRQ Pin = 0x01; IRQ Line = 0xFF; Found PCI device: DEC Chip 21140A Fast Ethernet LAN

PowerBoot>_


SETBOOT – Editing Auto Boot Parameters PowerBoot for PPC/PowerCore-6603/4

ary

CPU

the

oot:

Read NVRAM...identify boardSerial #: 927F02PB0541, Ethernet: 00:80:42:0E:02:1DPMC1/2: no auto mapping setup

<<PowerBoot Software V1.00 for PowerPC>>

PowerBoot>

5.4 SETBOOT – Editing Auto Boot Parameters

SETBOOT prompts the user to enter values for the parameters requiredfor the auto booting. The defined parameters become valid after the nextpower-on or when RESET is entered. The parameters are stored in the on-board NVRAM which keeps its contents during power-off and checksthem after power-on or after RESET has been entered.

Syntax SETBOOT

Description After SETBOOT has been entered, the user is prompted to assign a valueto each parameter described in the following. The prompt describes brief-ly the possible values of the respective parameters and the current setting.

The parameters described in the following

• define the location of the automatically loaded binary image: bootselect

• determine the kind of booting and the location where the binimage is started: auto boot, boot address, load address

• define a byte-sized value which has to be read by the PowerPC and which determines when instructions are executed: magic waitnumber

• select one of the user flash devices: boot user_flash

• select a harddisk SCSI ID for booting a bootfile: boot disk SCSIID

• select a controller SCSI ID for a mounted PMC module: PMCxcontroller SCSI ID

• select a boot delay time for waiting after power-on: boot delayfor SCSI disk

• select the location and the size of the VMEbus slave window andlocation of the VMEbus master window: VMEbus slave windowbase and size, PCI bus master window base

• define the name and the path of the file loaded during auto bTFTP/disk boot file name


PowerBoot for PPC/PowerCore-6603/4 SETBOOT – Editing Auto Boot Parameters

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• select the internet protocol for connecting a server to the CPU boRARP or ARP protocol

• select the protocol numbers for selecting the TFTP file server andidentifying the CPU board: serverIP#, targetIP#

• define the I/O or MEM address seen from the PCI bus which willwritten to the PCI bus device of the PMC1 or the PMC2 moduPMC1 PCI bus I/O base address and MEM baseaddress, same for PMC2

boot selectdefines the location of the automatically loaded binary image:

– 0 = autoloads a binary image to boot address via Ethernet(TFTP and front-panel connector). The user must link the dowload application image to boot address.

– 1 = selects the user flash device preset by boot user_flash.Only one user flash device can be mapped to the CPU at addFFE0.000016 (paging). The execution is started at bootaddress.

– 2 = a VMEbus slave interface is opened. The VMEbus slave wdow is preset by VMEbus slave window base address andsize and by PCI bus master window base address. Nobinary loading nor execution is done. Instead PowerBootinvoked.

– 3 = a VMEbus slave interface is opened. and a binary imagautoloaded to boot address via TFTP. The VMEbus slave win-dow is preset by VMEbus slave window base address andsize and by PCI bus master window base address. Theexecution is started at boot address.

– 4 = a VMEbus slave interface is opened and the user flash dedefined by boot user_flash is assigned to addressFFE0.000016. The VMEbus slave window is preset by VMEbusslave window base address and size and by PCI busmaster window base address. The execution is started aboot address.

– 5 = a VMEbus slave interface is opened. For an outline of the pcedure see “magic wait number” on page 98. After the CPUhas detected the byte-sized parameter magic wait number atthe PCI bus master window base, a binary image is startedat boot address. Before magic wait number is detected,the wait state can be interrupted for debugging purposes by pring a key. By this, PowerBoot will be invoked and the binaimage is not executed.



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– 6 = autoloads a PREP boot image from a SCSI harddiskdescribed in the PREP specification. If no PREP partition is foua DOS 4.0 partition will be used. It is assumed that a PMC modis mounted at PMC1 or PMC2, which holds an NCR53C825 orNCR53C875 SCSI 2 controller. The user has to prepare the hdisk format to be PREP- compliant or DOS 4.0-compliant. Furthmore, the application image must be prepared for booting. If partition format DOS 4.0 is used, the pure binary file to be boocan be copied from PC as normal DOS file to the root partitionthe harddisk. The parameter boot address is used for down-loading, boot disk SCSI ID for identifying the harddisk,PMCx controller SCSI ID is used for identifying the PMCbased SCSI controller and boot delay for SCSI disk forselecting a delay period after power-on.

auto bootenables or disables the auto booting.

– 0 = auto boot disabled. All NVRAM parameters are ignored. TPowerBoot debugger is invoked.

– 1 = auto boot enabled. Auto boot will take place after the npower-on or when RESET is used.

load addressspecifies the location in the CPU addressing space where the opcodownloaded. load address does not depend on other NVRAM parameters. The binary image is always downloaded to load addressby using the boot select parameters 0, 3, 6.

boot addressspecifies the location in the CPU addressing space where the opcostarted. It is independent of other NVRAM parameters. The binary age always starts at boot address, regardless, whether it is downloaded during power-on or stored in the user flash. For furtinformation on the address map see section 5.1 “PPC/PowerC6603/4 Address Map” on page 92.

magic wait numberselects a byte-sized value which appears at PCI bus master win-dow base address. It is only used if boot select is set to 5.

The magic wait number enables easy downloading of a user apption from a central master CPU to PPC/PowerCore-6603/4, the taCPU, via the VMEbus backplane. After the master CPU has booteoperating system, it reads every VMEbus location where it expecVMEbus slave window of the target CPU. When a target VMEbslave window has been found, the master CPU fills every target VMbus slave window with application code or data. After the transfer



ed

ter

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been finished, the master CPU writes the byte-sized value magicwait number to every target VMEbus slave window base.Every target will read this value and start executing the application in-structions at boot address.

Opposed to the preceding description, the following paragraph de-scribes the same procedure from the target CPU’s perspective.

After power-on, a VMEbus slave window is opened which is definby VMEbus slave window base address, VMEbus slavewindow size, and PCI bus master window base address.After this the PowerPC CPU writes its own predefined parameVMEbus slave window base address as long-sized value toPCI bus master window base address to indicate to an ex-ternal VMEbus CPU that PPC/PowerCore-6603/4 has openedVMEbus slave window. Then the PowerPC CPU polls the addrstored at PCI bus master window base address. ThePPC/PowerCore-6603/4 CPU tries to read this address, until the vdefined by magic wait number is read. This value must be writtenby another CPU board on the VMEbus to VMEbus slave windowbase address. After the PowerPC CPU has read the magic waitnumber, it starts executing instructions at boot address. Bootaddress can be a location at PCI bus master window baseaddress or any other location at the CPU addressing space.

boot user_flashselects one of the four 8-bit wide organised user flash devices. Theboard logic of the PowerPC-to-PCI bridge provides only a 1-Mbsized window at the addressing space for user flash devices. Thisdow ranges from FFE0.000016 to FFEF.FFFF16 seen from theCPU addressing space. boot user_flash is used only

– if boot select is set to 1 or 4

– and if auto boot is set to 1.

In all other cases boot user_flash will be ignored and user flash 1will always be preset after power-on.

boot disk SCSI IDselects the harddisk SCSI ID for booting the harddisk. boot diskSCSI ID is set

– to 0 for harddisk drive 0,

– to 1 for harddisk drive 1,

– to 2 for harddisk drive 2, and so on.

boot disk SCSI ID can range between 0 and 15 and supportswide SCSI drives. boot disk SCSI ID is used only for the auto-boot functionality. Other drives and their SCSI IDs may also be c



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nected but they will be ignored during autobooting. SCSI paritychecking is not supported.

PMCx controller SCSI IDselects the SCSI controller ID for booting the harddisk. PMCx con-troller SCSI ID is set

– to 0 for SCSI ID 0,

– to 1 for SCSI ID 1,

– to 2 for SCSI ID 2 and so on.

PMCx controller SCSI ID can range between 0 and 15 andsupports wide SCSI drives. PMCx controller SCSI ID is usedonly for the autoboot functionality. It may be changed on demandan application software. SCSI parity checking is not supported.

boot delay for SCSI diskselects a delay time ranging from 0 to 99 seconds. boot delay forSCSI disk delays the first access to the harddisk by a preset peof time. It is used only if boot select is set to 6. Other power-on booting options do not use this parameter.

VMEbus slave window basesets the 32-bit sized base address where the VMEbus slave wincan be accessed from the VMEbus (if boot select is set to 5, see“magic wait number” on page 98). There is always one A32/D3MBLT window opened. For further information see “PCI-to-VMEbridge – Universe II”, Data Sheets.

VMEbus slave window sizeselects the size of the VMEbus slave window (if boot select is setto 5, see “magic wait number” on page 98). The minimum size is64 Kbyte and the maximum size is 1956 Mbyte. The maximum sizlimited by the PPC/PowerCore-6603/4 address map and the 3VMEbus addressing space.

PCI bus master window basesets the 32-bit sized base address of PCI addressing space whecesses from the VMEbus into the VMEbus slave window are translainto the PPC/PowerCore-6603/4 memory (if boot select is set to 5,see “magic wait number” on page 98). In general a VMEbusslave window always refers to a PCI bus master window. In most cmon cases PCI bus master window base holds an address point-ing to the PPC/PowerCore-6603/4 DRAM. Usually this address ranfrom 0000.000016 to the end of the DRAM, i. e. 00FF.FFFF16 at16-Mbyte on-board DRAM.



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Note: The DRAM address range 0000.000016 … 0001.000016is used for CPU exception vectors and PowerBoot internals.

For further information on the VMEbus interface, see “PCI-to-VMbridge – Universe II”, Data Sheets.

PowerBoot checks PMC1 and PMC2 for a mounted PMC module ctaining one of the following SCSI controllers:

– NCR53C825

– or NCR 53C875

If one of the SCSI controllers mentioned above is found, it will mapped automatically by firmware to the addresses shown in thelowing table.

Other SCSI controllers are not supported and therefore they will benored.

RARP or ARP protocolselects the internet protocol used for connecting a server to the board.

– 1 = selects RARP (Reverse Address Resolution Protocol). In cof RARP the parameters serverIP# and targetIP# areignored.

– 2 = selects ARP (Address Resolution Protocol). In case of ARPvalues entered for the parameters serverIP# and targetIP#are valid.

If another value is entered, the default setting 1 is assigned to the pa-rameter.

serverIP#defines the internet protocol number which selects the TFTP file ser. If the internet protocol RARP is selected, serverIP# is ignored.serverIP# is stored as string, therefore it has to be written as shoin the following example 123.3.255.255.

Table 56 PCI I/O addressing spaces of the SCSI controllers

PCI I/O addressing space NCR53C825 NCR53C875

seen from the CPU FE82.000016 FE83.000016

seen from the PCI bus 0082.000016 0083.000016



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targetIP#defines the internet protocol number identifying the CPU board at in-ternet layer. If the internet protocol RARP is selected, targetIP# isignored. targetIP# is stored as string, therefore it has to be writtenas shown in the following example 3.255.37.67.

TFTP/disk boot file namedefines the name and path of the file which will be loaded during autoboot (if boot select = 0, 3, or 6). The file name including path isat most 128 characters.

If TFTP is used for booting, the host must be set up as TFTP server(boot select = 0 or 3). The host has to be able to provide the de-sired file via Ethernet (TFTP and front-panel connector).

If a harddisk is used for booting (boot select = 6), it must be setto the corresponding parameters defined by boot disk SCSI ID,PMCx controller SCSI ID, and boot delay for SCSIdisk. At first the harddisk partitions 0 to 3 are scanned in order tofind a PREP partition (4116). If no PREP partition is found, aDOS 4.0-compatible harddisk partition (0616) will be searched. Incase of a valid DOS 4.0 partition, TFTP/disk boot file namemust be limited to a maximum of 8 characters followed by a dot . andan extension consisting of 3 characters (e.g. myfile.bin). All othernames are ignored. Do not type a harddisk character like C:\ in frontof TFTP/disk boot file name. The root directory of the hard-disk partition is searched only for TFTP/disk boot file name.Subdirectory levels are not searched and FAT32 systems are not sup-ported.

In both cases (TFTP and harddisk) the user is fully responsible for up-per case letters, lower case letters, and the file name itself.

PMCx PCI bus I/O or MEM base addressdefines the respective I/O or MEM address based on the PCI bus de-vice of the PMCx module.

The following description is divided into two parts:

– the first part is a general description of the PMC modules and tbase addresses

– whereas the second part describes the 4 parameters.

On PPC/PowerCore-6603/4 up to 2 PMC modules can be instaEvery PMC module can have 2 different base addresses:

– one base address in the PCI bus I/O space

– and one base address in the PCI bus MEM space.

Depending on the features of the installed PMC modules, the addes have to be set differently:



ace,

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– If no PMC module is installed, set both addresses to 0.

– If the installed PMC modules support only one addressing spset the address which is not supported to FFFF.FFFF16 to disableit.

– If the installed PMC modules support both addressing spacesboth addresses to the desired value.

Note: Do not set a PMC module base address to an address alreadyused by the on-board PCI bus devices (see table 54“PPC/PowerCore-6603/4 address map seen from the CPU” onpage 92).

In the following the 4 parameters are described:

– PMC1 PCI bus I/O base address

– PMC1 PCI bus MEM base address

– PMC2 PCI bus I/O base address

– PMC2 PCI bus MEM base address

When defining the I/O base address of PMCx, the following is done:

– The PCI bus master bit (bit 2) is set to 1.

– The PCI bus I/O space control bit (bit 0) is set to 1.

– The value of the I/O base address is written to offset 1016, whichdefines the first I/O base address register in the PCI device hetype region.

When defining the MEM base address of PMCx, the following isdone:

– The PCI bus master bit (bit 2) is set to 1.

– The PCI bus MEM space control bit (bit 1) is set to 1.

– The value of the MEM base address is written to offset 1416,which defines the first MEM base address register in the Pdevice header type region.

After the last parameter has been typed in, a checksum is calculatprotect the NVRAM contents from 1C0016 to 1FF016 containing all ed-ited parameters.

Example PowerBoot> PowerBoot> SETBOOT

-General boot parameters-


USERLED – Setting User LED PowerBoot for PPC/PowerCore-6603/4

Boot select [0=Net, 1=Flash, 2=VME, 3=VME+Net, 4=VME+Flash, 5=VME+Magic, 6=SCSI disk], (6) : Auto boot [0=disable, 1=enable], (0) : Load address (00100000) : Magic wait number (EA) : Boot USER_FLASH [1..4], (1) : Boot Disk SCSI-ID [0..15], (1) : PMCx Controller SCSI-ID [0..15], (7) : Boot delay for SCSI Disk [0..99s], (8) :

-VMEbus boot parameters-

VMEbus slave window base address (C8000000) : VMEbus slave window size (00800000) : PCIbus master window base address (00800000) :

-TFTP Ethernet/Harddisk boot file parameters-

RARP [1] or ARP [2] protocol : (2) : Server-IP# [aaa.bbb.ccc.ddd] : 192.1.40.21 : Target-IP# [aaa.bbb.ccc.ddd] : 192.7.405.222 : TFTP/Disk Boot file name :pcore603 :

-PMC modul mapping parameters-

PMC1 PCIbus 0000000) : PMC1 PCIbus MEM base address (00000000) : PMC2 PCIbus I/O base address (00000000) : PMC2 PCIbus MEM base address (00000000) : CSUM : 0xA5CPowerBoot>

5.5 USERLED – Setting User LED

USERLED defines the color of the user LED at the front panel. Theon-board user LED lights red, green, or can be turned off.

Syntax USERLED colorcolor

defines the color of the user LED:

– red = user LED U lights red

– green = user LED U lights green

– dis = user LED U is off

Example In the following example the user LED U lights green: PowerBoot> USERLED greenPowerBoot> _


PowerBoot for PPC/PowerCore-6603/4 VMEMST – Opening an A32/D32 Master Window

p. Acess-VME

5.6 VMEMST – Opening an A32/D32 Master Window

VMEMST initializes an A32/D32 master interface to the VMEbus. ThePCI and VME address as well as the window size have to be 64k-aligned.If they are not aligned, an error message is displayed and the slave win-dow is not invoked.

Syntax VMEMST PciAddr VmeAddr windowSize reqLevel mode

PciAddr specifies the PCI bus address where the VME window is accessed.PciAddr has to be located between 8000.000016 and8FFF.FFFF16 of the PCI memory.

VmeAddr specifies the VMEbus address where the master window starts.

windowSize specifies the size in byte of the VMEbus master window.

reqLevelspecifies the VMEbus request level. The possible values range from 0 to 3:

– 0 = VMEbus request level 0




modeselects one of the data transfer operations:

– 0 = BLT (Block Transfer)

– 1 = MBLT (Multiplexed Block Transfer)

Description To initialize a VME master interface, the VME device has to be set uVMEbus master interface requires a PCI bus slave interface to be aced by the CPU. The PCI bus slave interface 0 is used to setup the master interface.


VMESLV – Opening an A32/D32 Slave Window PowerBoot for PPC/PowerCore-6603/4

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If mode is set to 0, the following parameters are selected:

• VMEbus Maximum Data Width (VDW) = 102, i.e. 32-bit data width

• VMEbus Address Space (VAS) = 0102, i.e. A32 addressing space

• Program/Data AM Code (PGM) = 002, i.e. data AM code

• Supervisor/User AM Code (SUPER) = 012, i.e. privileged mode

• VMEbus Cycle Type (VCT) = 02, i.e. single cycle mode

If mode is set to 1, the following parameters are selected:

• VMEbus Maximum Data Width (VDW) = 112, i.e. 64-bit data width

• VMEbus Cycle Type (VCT) = 12, i.e. single cycle and block transfemode

The other parameters (VAS, PGM, SUPER) are not changed, i.e. thetain the selections as shown above.

Example The following example shows a setup of a VME master window1 Mbyte at address 8000.000016. Every CPU ranging locally from8000.000016…8010.000016 accesses the VMEbus betweeC800.000016 and C810.000016. The VMEbus is requested at level3and block transfer is selected.If the setup has been successful, the following message is displayedPowerBoot> VMEMST 80000000 c8000000 100000 3 0Init VME Master Window PCI address:80000000VME address: C8000000Window size: 100000VMEbus request level: 03VMEbus cycle type (BLT=0, MBLT=1): 0

5.7 VMESLV – Opening an A32/D32 Slave Window

VMESLV initializes an A32/D32 slave interface to the VMEbus. The PCIand VME address as well as the window size have to be 64k-aligned. Ifthey are not aligned, an error message is displayed and the slave windowis not invoked.

Syntax VMESLV PciAddr VmeAddr windowSize

PciAddr specifies the PCI bus address where the VME slave window is access-ed. It has to be an address of the PCI memory space.

VmeAddr specifies the VMEbus address where the slave window starts.


PowerBoot for PPC/PowerCore-6603/4 VMESYS – Enabling VMEbus System Controller

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windowSize specifies the size in byte of the VMEbus slave window.

Description To initialize a VME slave interface the VME device has to be set up. TheVMEbus slave interface requires a PCI bus master interface. The PCI busmaster interface 0 is used to setup the VME slave interface.

The following parameters are selected:

• VMEbus Address Space (VAS) = 102, i.e. A32 addressing space

• Program/Data AM Code (PGM) = 112, i.e. both data AM codes

• Supervisor/User AM Code (SUPER) = 002, i.e. both user modes

Example The following example shows a setup of a VME slave window1 Mbyte at address 0040.000016: PowerBoot> PowerBoot> PowerBoot> vmeslv 400000 c8000000 100000 Init VME Slave Window using:PCI master base address: 00400000VME slave base address: C8000000Window size: 00100000

PowerBoot>

5.8 VMESYS – Enabling VMEbus System Controller

VMESYS enables or disables the on-board VMEbus system controller orshows its current status. When enabling or disabling the VMEbus systemcontroller, the setting of SW7-1 and SW7-2 is temporarily overridden.

Syntax VMESYS status

status defines whether the VMEbus system controller is enabled or disabled:

– ena (or short: e) = VMEbus system controller enabled

– dis (or short: d) = VMEbus system controller disabled

– ? = indicates the current status of the VMEbus system controlle

Description If the VMEbus system controller is enabled, PPC/PowerCore-6603/4to be mounted at slot 1 of the VMEbus backplane. The VMEbus syscontroller is located in the Universe PCI bus device. Only the SYSCbit at register offset 040416 (MISC_CTL) is set or cleared. All other registers keep their settings.


VMESYS – Enabling VMEbus System Controller PowerBoot for PPC/PowerCore-6603/4

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During power-on SW7-1 and SW7-2 are read by the VMEbus interface toenable or disable the VMEbus system controller (see section 2.3 “SwSettings” on page 11). VMESYS is capable of overriding the switch seting for debugging purposes. An enabled system controller is indicatea green user LED regardless of the state defined by USERLED section 5.5 “USERLED – Setting User LED” on page 104).

Example To enable the VMEbus system controller enter: PowerBoot> VMESYS enaPowerBoot> _


Product Error Report

✉ Send this report to the nearest Force Computers headquarter listed on the back ofthe title page.

PRODUCT: SERIAL NO.:

DATE OF PURCHASE: ORIGINATOR:

COMPANY: POINT OF CONTACT:

TEL.: EXT.:

ADDRESS:

PRESENT DATE:

AFFECTED PRODUCT:

❏ HARDWARE ❏ SOFTWARE ❏ SYSTEMS

AFFECTED DOCUMENTATION:

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ERROR DESCRIPTION:

THIS AREA TO BE COMPLETED BY FORCE COMPUTERS:

DATE:

PR#:

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ENGINEERING ➠ ❏ BOARD ❏ SYSTEMS

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