power re ducat ion techniques for cache memory design

8/3/2019 Power Re Ducat Ion Techniques for Cache Memory Design

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RATNAKARAM PHANEENDHRA KUMAR


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INTRODUCTION

y WHAT IS CACHE

y IMPORTANCE OF CACHE MEMORY POWER

REDUCTIONy MAPPING FUNCTIONS

y POWER REDUCTION TECHNIQUES


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WHAT IS CACHE

y Cache is employed by micro processor for channeling the performancegap between processor and main memory.

Data Transfer

Cache is the simplest cost effective way to achieve high speed memoryhierarchy


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IMPORTANCE OF CACHE POWER REDUCTION

y On chip cache memories dominate chip area, so we need powerefficient cache memories.

y Cache is one of the most power consuming component in theprocessors.

y So cache is one of the most appealing targets for power reduction.


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MAPPING FUNCTIONS

y The cache memory is filled by using mapping techniques

i.e. 1. Direct mapping

2. Full associative cache

3. Set associative cache

Direct mapped: Each block from main memory can be mapped only toa unique cache block.

Fully associative: Each block from main memory can be mapped to any

of cache blocks. Set associative : the cache is split into many sets, the data can be

mapped only to the blocks of a certain set.


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COMPARISON BETWEEN MAPPING FUNCTIONS


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y The effectiveness of the cache is determined by the number of timesthe cache successfully provides the required data.

y Hit: when the data required by the processor is found in the cache thenwe call it as cache hit.

y Miss: If the data is not found in cache then we call it as cache miss.

y In order to minimize the power reduction in cache memory design weneed to increase the hit ratio or decrease the miss ratio.


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POWER MINIMIZATION TECHNIQUES

PARTIAL TAG COMPARISON TECHNIQUE

TAG SKIPPING TECHNIQUE

WAY MEMOIZATION TECHNIQUE


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y PARTIAL TAG COMPARISON TECHNIQUE:

y AIM: This technique proposes to use set-associative caches to reduce power

consumption on major cache components.

y Idea: Comparing small part of two tags to filter out most of the unmatched

tag comparisons.

y RESULT: By using 4-way set associative cache in partial tag comparison weeliminated number of mismatch comparisons in cache and yields to 37.5%reduction in comparisons .


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y TAG SKIPPING TECHNIQUE :

y AIM: Skipping the tag look-ups to achieve better power consumption design.

y Idea: Reducing the miss rates by using write tag skipping (WTS) buffer.

y Design Details : NLOWM withWTS buffer.

y A cache line buffer is placed between the lower level memory and thecache memory. This buffer will act as temporary storage for the requestedblock on the write miss. Mishandling procedure consists of fetching therequested block memory to theWTS buffer.


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INSTANCES FOR USING TAG SKIPPING

y When the first access read/write resulted in cache hit.

y When the first read access results in a cache miss implying that cache

does not contain the requested datas cache line. By using mishandlingprocedure we can access cache line from main memory and the cacheline is updated.

y When the first write access resulted in a cache miss implying that

cache does not contain the corresponding cache line. The WTS bufferwrite mishandling procedure is applied and the cache line istransferred to the buffer from the main memory.

y In the above cases the second tag comparison can be skipped.


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y WAY MEMOIZATION TECHNIQUE:

AIM: This technique for eliminating redundant cache tag and cache way access to

reduce power consumption.

IDEA : Placing small number of most recently used addresses in a memory address

buffer (MAB).

According to this technique one simple approach is to reduce power consumption to

employ small cache (L0) between CPU and cache (L1)

L0 cache is small so it consumes less power per access if there is a hit in L0 cache.

On the other hand there is a miss in cache L0 then extra cycle need to access L1 cache.


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y TWO PHASE CACHE APPROACH:

y In the first phase tags of all cache- ways or accessed to find the cache-way

having the data

y If there is a hit, in the second phase, only one of the cache way is activated.

y Cache Tag access and tag comparisons do not need to be performed for all

instruction fetches.

y Consider an instruction j which is executed immediately after an instruction i.


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y There are 4 cases to fetch instructions from cache.y 1)Intra-cache-line sequential f low:

This occurs when both i and j instructions reside on the

same cache line and target address is next address.

2)Intra-cache-line non sequential flow:

This occurs when both I and j instructions reside on the

same cache line and target address is not next address.

3)Inter-cache-line sequential flow:

This occurs when both I and j instructions reside on

different cache lines.4)Inter-cache-line non sequential flow:

This occurs when both I and j instructions reside ondifferent cache lines but target address is not next address.


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CONCLUSION

y In partial comparison number of comparisons in cache memory isreduced and there is no performance loss cache memory speed.

y In Tag skipping technique number of write misses decreased by50% and efficient for power reduction.

40% power reduction in way memoization technique but it coulddegrade the performance of cache.


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REFERENCESy H. Choi, M-K. Yim, J-Y Lee, B-W. Y, andY-T. Lee, Low Power 4-WayAssociative Cache For Embedded

SOCDesign, Proc. 13th Annual IEEE Intl ASIC/SOC Conf., pp.231-235, 2000.

y Y-J. Chang, C-L. Yang, and F. Lai, APower-Aware SWDR cell for Reducing Cache Write Power,

ISLPED 03, 2003.

y R. Min, Z. Xu, Y. Hu, and W-b. Jone, Partial Tag Comparison: A newTechnology for Power-EfficientSet-Associative Cache Designs, VLSID 04,

y Sing, Joel. Computer Technology Cache Memory.http://ironbark.bendigo.latrobe.edu.au/subjects/int11ct/2002/lectures/l17/cache.html

y Prof. Schulte, Mike. Lecture 10 Memory Hierarchy and Cache Design.http://fizbin.eecs.lehigh.edu/~mschulte/ece401-01/lect/my-lec10-p2.pdf

y Sing, Joel. Computer Technology cache memoryhttp://ironbark.bendigo.latrobe.edu.au/subjects/int11ct/2002/lectures/l17/cache.html


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THANQ

power re ducat ion techniques for cache memory design

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