power management through head count

8/8/2019 Power Management Through Head Count

1/29

DON BOSCO INSTITUTE OF

TECHNOLOGY

POWER MANAGEMENT

THROUGH HEAD COUNT

ASHLEY JOSE

SNADDE

N BRAGANZA

SUSHANT

CHAVAN

KELVIN

DSOUZA

JASON

FERNANDES

PROJECT GUIDE-

MRS.MADHAVI PEDNEKAR

1| P a g e


2/29

DEPARTMENT OF ELECTRONICS AND

TELECOMMUNICATIONS

UNIVERSITY OF MUMBAI 2010-11

CERTIFICATE

This is to certify that Mr. ____________________________________

has successfully completed his Project Work on the Topic

POWER MANAGEMENT THROUGH HEAD COUNT in the

subject of Electronic Hardware Workshop, in the partial

fulfillment of Engineering in the department of Electronics

and Telecommunication Engineering of the University of

Mumbai during the year 2010-2011.

(Internal Examiner) (External

Examiner)

2| P a g e


3/29

Department of Electronics and Telecommunication

Engineering

Don Bosco Institute of Technology

University of Mumbai

2010-2011

ACKNOWLEDGEMENT

We would like to thank our college - D.B.I.T for

providing us with all the components required

for the project free of cost and for granting us

permission to use the labs as and when

required. We would like to thank our project

guide Mrs. MADHAVI PEDNEKAR without whom

this project would not have come into

existence .She has been like fuel to our

engines, constantly encouraging and

motivating us in our endeavor .We would also

like to thank JOHN sir from the workshop for

letting us use tools to create the casing. And

last but not the least we would like to thank

3| P a g e


4/29

KISHORE sir for acquiring the components and

helping us out whenever we faced a problem.

4| P a g e


5/29

INDEX

SR.

NO.

TOPIC

PG.NO.

1 INTRODUCTION 5

2 PROGRAM FLOW CHART 6

3 BLOCK DIAGRAM 7

4 EXPLANATION OF BLOCK DIAGRAM 8

5 CIRCUIT DIAGRAM 9

6 COMPONENT LIST 10

7 SOFTWARE USED:PROTEAS 12

8 SNAP SHOTS OF SOLDERING ANDTESTING 14

9 TROUBLESHOOTING 18

10 APPLICATIONS 19

11 CONCLUSON 20

12 APPENDIX 21

5| P a g e


6/29

INTRODUCTION

In todays modern world, energy conservation is of prime

importance. Due to the ever increasing population, resources

are becoming insufficient for sustainable development.

People all over the world are becoming aware of this scarcity

in resources like water, fuel and electricity .Many of them are

opting for designs which reduce wastage of these precious

resources. Thus energy efficiency in design adds value to it.

In our project titled POWER MANAGEMENT THROUGH HEAD

COUNT we have inculcated this idea of conserving a

resource as in electricity.

Through the help of microcontroller, photo transistors and

triacs we have developed a project which can controlelectrical devices such as fans and tube lights in a room

based on the number of people present thus saving

electricity.

6| P a g e


7/29

Microcontroller over discrete ICs

In our project the reason we have chose to use a

microcontroller over the discrete is not only to help us in the

understanding of the device i.e. the microcontroller but also

it greatly simplifies the circuit in terms of the amount of

hardware used the great thing about microcontrollers is they

require a very little hardware for their own operation where

as the amount of connection that would go into the same

circuit if it were to be made of discrete devices would be

greatly larger hence by using the AT89C51 we have not only

reduced the work of connections but also this has been a

learning opportunity for us and has given us a chance to use

the classroom knowledge about the microcontroller into a

real world application.

7| P a g e


8/29

PROGRAM FLOW CHART

The above program flow chart lucidly explains

the main logic behind our project.

BLOCK DIAGRAM

8| P a g e


9/29

9| P a g e

8

8


10/29

EXPLANATION OF THE BLOCK DIAGAM

EVERY TIME A CARD IS SWIPED THE OPTICAL

SENSOR SENSES IT AND SENDS A SIGNAL TO THE

MICROCONTROLLER

THIS SIGNAL ACTS LIKE A COUNT VALUE.

THE MICROCONTROLLER CONVERTS THIS COUNT

VALUE TO ITS BCD EQUIVALENT.

THE DECIMAL EQUIVALENT OF THE BCD CODE IS

DISPLAYED USING TWO SEVEN SEGMENT

DISPLAYS

AS SOON AS THE COUNT VALUE CROSSES A

PARTICULAR THRESHOLD VALUE SAY 30 IN A

CLASS OF 100 ,THE POWER CONTROL UNIT AS INTRIAC GETS TRIGGERED AND SOME OF THE

LIGHTS AND FANS ARE TURNED ON

10| P a g e


11/29

CIRCUIT DIAGRAM

11| P a g e


12/29

COMPONENT LIST

Category Reference Value

Resistors "R1" 470

Resistors "R2" 10k

Capacitors "C1" 33p

Capacitors "C2" 33p

Capacitors "C3", 33u

Integrated Circuits "U1", AT89C51

Integrated Circuits "U2", 74LS47

Integrated Circuits "U3", 74LS47

TRIAC "U4", BT126

TRIAC "U5" BT126

TRIAC "U6" BT126

Transistors "Q1" 2N4410

12| P a g e


13/29

Lamp "L1" 240V

Lamp "L2" 240V

CRYSTAL X1 12 Mhz

7 SEG DISPLAY CA

13| P a g e


14/29

SOFTWARE USED IN DESIGN: PROTEUS

Features of PROTEUS include:

True Mixed Mode simulation based on BerkeleySPICE3F5 with extensions for digital simulation and true

mixed mode operation.

Support for both interactive and graph based

simulation.

CPU Models available for popular microcontrollers such

as the PIC and 8051 series.

Interactive peripheral models include LED and LCD

displays, a universal matrix keypad, an RS232 terminal and a

whole library of switches, pots, lamps, LEDs etc.

Virtual Instruments include voltmeters, ammeters, a

dual beam oscilloscope and a 24 channel logic analyser.

On-screen graphing - the graphs are placed directly on

the schematic just like any other object. Graphs can be

maximised to a full screen mode for cursor based

measurement and so forth.

Graph Based Analysis types include transient,

frequency, noise, distortion, AC and DC sweeps and fourier

transform. An Audio graph allows playback of simulated

waveforms.

14| P a g e


15/29

Direct support for analogue component models in SPICE

format.

Open architecture for plug in component models

coded in C++ or other languages. These can be electrical.,

graphical or a combination of the two.

Digital simulator includes a BASIC-like programming

language for modelling and test vector generation.

A design created for simulation can also be used to

generate a netlist for creating a PCB - there is no need to

enter the design a second time.

15| P a g e


16/29

SNAP SHOTS OF SOLDERING AND

TESTING OF THE PROJECT

16| P a g e


17/29

17| P a g e


18/29

18| P a g e


19/29

WHEN NO CARD IS PRESENT INBETWEEN THE PHOTO TRANSISTER

LED REMAINS OFF

19| P a g e


20/29

WHEN CARD IS PRESENT IN BETWEEN

THE PHOTO TRANSISTERLED TURNS ON

20| P a g e


21/29

TROUBLE SHOOTING

During the testing of our project ,when we brought the card in

betweem the photo-transistor the led did not glow.

When we further investigated the cause of this problem we came to

know that the reason for this was that the transistor was connected in

forward bias instead of reverse bias.

Then we connected the photo transistor in reverse bias and the light

began to glow.

When we wanted to program the micro controller using the universal

programmer present in the college we foud that the parallel 25 pin

cable connecting the computer to the programmer was missing.

We then contacted DYNALOG systems and went to Vikhroli topurchase the cable but they did not have the required cable.

So then we bought a DP 25 cable from an electronics shop and

programmed our micro controller.

21| P a g e


22/29

APPLICATIONS

Our project POWER MANAGEMENT THROUGH HEAD

COUNT has many applications in todays world where

we are facing shortage of electricity.

This project can be made to interface with any electrical

device like fans, tube lights and bulbs.

It can be used to control the number of fans and lights

that need to be on depending on the strength of the

class.

It can even be used as a counter to count the number

of people who have swiped their cards and have

entered the class.

With further research we can create a system which

can create a database of the students that have swiped

their cards based on the barcoded information on their

i-cards for which we will require a bar code reader

22| P a g e


23/29

CONCLUSION

We have thus successfully developed a project which

manages power through head count. This project has

tremendous scope in the energy sector. With further

research and funding in this field it can be practically

implemented in our day to day lives thus saving electricity- a

valuable resource. With the smart use of new age power

devices coupled with the versatility of a microcontroller

based digital system the interface between the high power

and low power devices has been seamlessly achieved thus

through sheer innovation and brilliant design we hope we

can bring some respite to the never ending problem of

power shortage

23| P a g e


24/29

APPENDIX

AT89C51

Features

Compatible with MCS-51 Products

4K Bytes of In-System Reprogrammable Flash Memory

Endurance: 1,000 Write/Erase Cycles

Fully Static Operation: 0 Hz to 24 MHz

Three-level Program Memory Lock

128 x 8-bit Internal RAM

32 Programmable I/O Lines

Two 16-bit Timer/Counters

Six Interrupt Sources

Programmable Serial Channel

Low-power Idle and Power-down Modes

Description

The AT89C51 is a low-power, high-performance CMOS 8-bit

microcomputer with 4K

bytes of Flash programmable and erasable read only memory (PEROM).

The device

is manufactured using Atmels high-density nonvolatile memory

technology and is

compatible with the industry-standard MCS-51 instruction set and

pinout. The on-chip

Flash allows the program memory to be reprogrammed in-system or by

a conventional

nonvolatile memory programmer. By combining a versatile 8-bit CPU

with Flash

on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer

which provides

24| P a g e


25/29

a highly-flexible and cost-effective solution to many embedded control

applications.

PDIP

25| P a g e


26/29

DM74LS47

BCD to 7-Segment Decoder/Driver with

Open-Collector Outputs

General Description

The DM74LS47 accepts four lines of BCD (8421) input

data, generates their complements internally and decodes

the data with seven AND/OR gates having open-collector

outputs to drive indicator segments directly. Each segment

output is guaranteed to sink 24 mA in the ON (LOW) state

and withstand 15V in the OFF (HIGH) state with a maximumleakage current of 250 mA. Auxiliary inputs provided

blanking, lamp test and cascadable zero-suppression functions.

Features

n Open-collector outputs

n Drive indicator segments directly

n Cascadable zero-suppression capability

n Lamp test input

Logic Symbol

VCC = Pin 16

GND = Pin 8

Connection Diagram

Pin Descriptions

Note 1: OCOpen Collector

Order Number Package Number Package Description

26| P a g e


27/29

DM74LS47M M16A 16-Lead Small Outline Integrated Circuit (SOIC),

JEDEC MS-012, 0.150 Narrow

DM74LS47N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC

MS-001, 0.300 Wide

Pin Names Description

A0A3 BCD Inputs

RBI Ripple Blanking Input (Active LOW)

LT Lamp Test Input (Active LOW)

BI/RBO Blanking Input (Active LOW) or

Ripple Blanking Output (Active LOW)

a g Segment Outputs (Active LOW) (Note 1)

www.fairchildsemi.com 2

Truth TableNote 2: BI/RBO is wire-AND logic serving as blanking input (BI) and/or

ripple-blanking output (RBO). The blanking out (BI) must be open or

held at a HIGH

level when output functions 0 through 15 are desired, and ripple-

blanking input (RBI) must be open or at a HIGH level if blanking or a

decimal 0 is not

desired. X = input may be HIGH or LOW.

Note 3: When a LOW level is applied to the blanking input (forced

condition) all segment outputs go to a HIGH level regardless of the

state of any other input

condition.

Note 4: When ripple-blanking input (RBI) and inputs A0, A1, A2 and A3

are LOW level, with the lamp test input at HIGH level, all segment

outputs go to a

HIGH level and the ripple-blanking output (RBO) goes to a LOW level

(response condition).

Note 5: When the blanking input/ripple-blanking output (BI/RBO) is

OPEN or held at a HIGH level, and a LOW level is applied to lamp test

input, all segmentoutputs go to a LOW level.

27| P a g e


28/29

Functional Description

The DM74LS47 decodes the input data in the pattern indicated

in the Truth Table and the segment identification

illustration. If the input data is decimal zero, a LOW signal

applied to the RBI blanks the display and causes a multidigit

display. For example, by grounding the RBI of the

highest order decoder and connecting its BI/RBO to RBI of

the next lowest order decoder, etc., leading zeros will be

suppressed. Similarly, by grounding RBI of the lowest order

decoder and connecting its BI/RBO to RBI of the next highest

order decoder, etc., trailing zeros will be suppressed.Leading and trailing zeros can be suppressed simultaneously

by using external gates, i.e.: by driving RBI of a

intermediate decoder from an OR gate whose inputs are

BI/RBO of the next highest and lowest order decoders. BI/

RBO also serves as an unconditional blanking input. The

internal NAND gate that generates the RBO signal has a

resistive pull-up, as opposed to a totem pole, and thus BI/

RBO can be forced LOW by external means, using wiredcollector

logic. A LOW signal thus applied to BI/RBO turns

off all segment outputs. This blanking feature can be used

to control display intensity by varying the duty cycle of the

blanking signal. A LOW signal applied to LT turns on all

segment outputs, provided that BI/RBO is not forced LOW.

28| P a g e


29/29

Decimal

Inputs Outputs

or Note

Function LT RBI A3 A2 A1 A0 BI/RBO a b c d e f g

0 H H L L L L H L L L L L L H (Note 2)

1 H X L L L H H H L L H H H H (Note 2)

2 H X L L H L H L L H L L H L

3 H X L L H H H L L L L H H L

4 H X L H L L H H L L H H L L

5 H X L H L H H L H L L H L L

6 H X L H H L H H H L L L L L

7 H X L H H H H L L L H H H H

8 H X H L L L H L L L L L L L9 H X H L L H H L L L H H L L

10 H X H L H L H H H H L L H L

11 H X H L H H H H H L L H H L

12 H X H H L L H H L H H H L L

13 H X H H L H H L H H L H L L

14 H X H H H L H H H H L L L L

15 H X H H H H H H H H H H H H

BI X X X X X X L H H H H H H H (Note 3)

RBI H L L L L L L H H H H H H H (Note 4)

LT L X X X X X H L L L L L L L

power management through head count

Documents