power aware testing strategies (slides).pdf

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Power-Aware Testing and Test Strategies for Low Power

Devices

Patrick Girard, Nicola Nicolici, Xiaoqing Wen

To cite this version:

Patrick Girard, Nicola Nicolici, Xiaoqing Wen. Power-Aware Testing and Test Strategies forLow Power Devices. ATS2012: Asian Test Symposium, Nov 2012, Niigata, Japan. IEEE,.

HAL Id: lirmm-00820737

http://hal-lirmm.ccsd.cnrs.fr/lirmm-00820737

Submitted on 6 May 2013

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1

Power-Aware Testing and Test Strategies

for Low Power Devices

LIRMM / CNRS

France

McMaster University

Canada

Kyushu Institute of Technology

Japan

2

Power-Aware Testing and Test

Strategies for Low Power Devices

Springer web site:

http://www.springer.com/engineering/circuits+%26+systems/book/978-

1-4419-0927-5


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MARKET

Final Teston ATE

Burn-In (4-24 hrs)

Termal Cycling+ Final Test

on ATEWhole population

Sample population

Wafer sorton ATE

A

NALYSIS

Stress(up to 2000 hrs)

Test onATE

Selected products

Known Good Dies (KGDs)

Reliability measurements

(courtesy: Bernardi et al., ETS, 2009)


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CLK

ScanENA

CLK

ScanENA

Primary

Inputs

Primary

Outputs

D Q

ScanEna

D

Qi-1

Clk

Qi


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CLK

ScanENA

FF1 FF2 FF3 FF4

FF1 FF2 FF3 FF4

Primary

Inputs

Primary

Outputs

8

1.35 millions of flip-flops, all are scannable !!


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Switching (dynamic) Power

Leakage (static) Power

10

Much higher than during functional operations

determine

Excessive

Test PowerDuring

Structural

Testing


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Much higher than during functional operations

Toggle activity under functional mode : 15%-20%

Toggle activity under test mode : 35%-40%

Power under test mode up to 3.8X power during functional mode

12

Main reasons for excessive test power

For conventional (non low-power) designs, dynamic power

is the main responsible for excessive test power !!

Leakage power is a real issue during IDDQ test (reduced sensitivity) and

during burn-in test (can result in thermal runaway condition and yield loss)


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Conventional (slow-speed) scan testing

14

At-speed scan testing with a LOC/LOS scheme

Example


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one peak is not relevant


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high average power

problems may occur

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one peak is highly relevant


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Elevated Average Power

Reduced ReliabilityChip Damage

Yield Loss

20

Elevated Average Power

Low Test Throughput


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Elevated Peak Power

Manufacturing Yield Loss

As huge designs can be manufactured today, most power-related

test issues (during scan) are due to excessive peak power

22

IR Drop

I

L(di/dt)

i(t)

L

(courtesy: O. Sentieys, IRISA, France)


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23

(courtesy: A. Domic, Synopsys, USA)

24


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(courtesy: K. Hatayama, STARC, Japan)

activate all modules activate only one module

26

Costly or longer test time

Straightforward Solutions


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27

Main classes of dedicated solutions

Make test power dissipation comparable to functional power

Objective

28



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The Role of Test Data in Test Flow

Comparison

Design Data

Tester

ActualResponses

LSI Chip

Fabrication

TestPatterns

ExpectedResponses

Passing Chips Falling Chips

Probe Card

Prober

Socket Board

Handler

GO NG

Test

Data

30

Target of Scan Test Pattern Generation

PI

PPI

PO

PPO

Scan-In

Scan-Out

Scan Chain


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31

Automatic Test Pattern Generation (ATPG)

X

1

X

0

1

1

X

X

CUT

32

X-Bits in Test Cubes

20

30

40

50

6070

80

90

100

0 50 100 150 200 250 300 Vec.

X-bitsRatio(%)

i.e., assigning logic values to X-bits


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33

Conventional X-Filling Technique: Random-Fill

Small test pattern count due to fortuitous detection

High test (shift and LTC) power

34

Various Low-Power X-Filling Techniques

Low-Shift-Power X-Filling

0-fill1-fill

MT-filladjacent fill / repeat fill

MTR-filloutput-justification-based X-

filling

Low-LTC-Power X-Filling

PMF-fillLCP-fill

preferred fillJP-fill

CTX-fill

CCT-fillCAT-fill

PWT-fillstate-sensitive X-filling

Low-Shift-and-LTC-Power X-Filling

impact-oriented X-filling hybrid X-filling bounded adjacent fill

Low-PowerX-Filling for Compressed Scan Testing

0-fill PHS-fill CJP-fill

(source: X. Wen and S. Wang, Low-Power Test Generation, Chapter 3 in Power-Aware Testing and

Test Strategies for Low Power Devices, edited by P. Girard, N. Nicolici & X. Wen, Springer, 2009)


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Example 1: Low-Shift-Power X-filling

Goal

0-fill1-fill MT-fill adjacent-fill

0-fill

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Example 1 (contd): Low-Shift-Power X-filling

X

X

X-

X-

X-

0 0 0 0 0

X

1 1 1 1 1

1 1 0 0 0

0 0 1 0 0

0 1


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Example 2: Low-LTC-Power X-Filling

0

1

1

0

0 0

Stimulus Response

Combinational Circuit

Launch-to-Capture (LTC) Power

IR-Drop

Delay Increase

Malfunction

VDD

Timing

38

X0X

X

X0X1

XX

1

Example 2 (contd): Low-LTC-Power X-Filling

1

01

0

0

1

Signal Probability Calculation

Logic Value Determination

Justify

JP-Fill

0-Prob

1-Prob

No DecisionNext Pass

1

Assign

f

Test Response

(source: X. Wen et al., Proc. ITC, Paper 25.1, 2007)

too close to call


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Example 2 (contd): Low-LTC-Power X-Filling

0.00

0.01

0.02

0.03

0.04

0.05

0.06

0 50 100 150 200 250 300

Test Vectors.

-

OriginalJP-Fill

LTC

IR-Drop(V)

Risky

Safe

Risky Safe

JP-FillOriginalChip-Level

IR-Drop Distribution

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Example 3: Low-Shift-&-LTC-Power X-Filling

Test Cube XXX Shift Direction

0000 0 0 0 0 0 00000

0 0 0 0 11111 0 0 0 0 0

0 0 0

0-Fill

Adjacent Fill

Bounded Adjacent Fill

000

1st0-Constraint Bit Bounding Interval = 6

X adjacent fill

The occurrence of 0 in the resulting fully-specified test vector is increased, which helps

reduce shift-out and LTC power. making use of the benefit of 0-fill

At the same time, applying adjacent fill helps reduce shift-in power.

(source: A. Chandra et al., Proc. VTS, pp. 131-138, 2008)


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41

Summary - (1)

Vector-Pinpoint

Area-Pinpoint

42

Summary - (2)

2012

Current

Low-Power Test

Generation

Coarse-Grained Fine-Grained

Global

20??

Future

Power-Safe Test

Generation

Regional

(source: X. Wen, ETS, Invited Talk, 2012)


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Objective

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Shift Power Reduction LTC Power Reduction

Partial Capture

circuit modification- scan chain disable

- one-hot clocking

- capture-clock staggering Scan Chain Modification

scan cell reordering

- scan chain segmentation

scan chain disable

Shift Impact Blocking

blocking gate special scan cell first-level power supply gating

Scan Clock Manipulation

splitting staggering

- multi-duty clocking


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Example 1: Low power scan cell

(source: A. Hertwig and H.-J. Wunderlich, Proc. ETW, pp. 49-53, 1998)

46

ENAB

SISO

Example 2: Scan chain segmentation

ENAA

ScanENA


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CK/2CK/2

CK

SISO

Example 3: Staggered clocking

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Example 4: Scan cell reordering

(courtesy: H.-J. Wunderlich and C. Zoellin, Univ. Stuttgart)


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Example 5: Inserting logic into scan chains


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Example 6: Scan segment inversion



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52(source: P. Girard et. al., Proc. VTS, pp. 407-412, 1999)

Example 1: Masking logic insertion during BIST

ViVj

Vk

Vl

V0


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Example 2: Adaptation to Scan-Based BIST

(source: F. Corno et. al., Proc. DFT, pp. 219-226, 1999)

54

(source: S. Wang and S. Gupta, Proc. ITC, pp. 848-857, 1997)

Example 3: Dual-speed LFSR for BIST


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55(source: S. Wang and S. Gupta, Proc. ITC, pp. 848-857, 1997)

Example 3 (contd): Dual-speed LFSR for BIST

56

Example 4: Coding for compression and test power

(courtesy: K. Chakrabarty and S.K. Goel, Duke Univ.)


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Example 5: Linear Finite State Machines

(source: F. Czyusz et al., Proc. VTS, pp. 75-83, 2007)

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Improve Test Throughput by Exploiting Design Modularity

(source: Y. Zorian, Proc. VTS, pp. 4-9, 1993)

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Example 1: Resource Allocation and Incompatibility Graphs

(source: R. Chou et al., IEEE Trans. on VLSI, Vol. 5, No. 2, pp. 175-185, 1997)


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Example 1 (contd): Power Model and Test Schedule

(source: R. Chou et al., IEEE Trans. on VLSI, Vol. 5, No. 2, pp. 175-185, 1997)

62

Example 2: Power Profile Manipulation


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Example 3: Thermal Considerations

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Test Power Reduction Strategies

High

High

Low

Low

Low

Low

Low

Low

Minimum

Minimum

(source: S. Ravi, TI, ITC07)


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The new power-performance paradigm:

Adoption of low-power design and power management techniques

Density 2X

Performance 1.4X

Power 1X

Cost 0.5X

Applications

Units

Users

Revenue

(courtesy: M. Hirech, Synopsys, USA)

68


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69

Main LPD techniquesPower reduction

These techniques are often combined together to

achieve the maximum power optimization value

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Even more critical for Low-Power Design !!

PM structures

often disabled

during test

application

(courtesy: X. Wen, KIT)


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71

And still target:

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Objective (again)


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Multi-Voltage Design Styles

0.9V0.9V0.7V0.7V

0.9V0.9V

OFF0.7 0.9V0.7 0.9V

PWR

CTRL

PWR

CTRL

0.7V0.7V0.9

V

OFF0.9V0.9V0.7V0.7V

0.9V0.9V

Dynamic Voltage

Frequency Scaling

(DVFS)

Multi-Voltage

with power gating

Multi-Voltage

Multi-supply


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Example 1: Multi-Voltage Aware Scan Cell Ordering

L ogical Physical M ulti-

Voltage

1

2

3

4

5

6

7

8

9

Design (1.2V)

B1

B3

B2

C2

C1

C3

A1

A2

A3

Block A

0.9V

Block B

1.2V

Block C

0.9V

Position

Ordering

76

EncounterTM

Example 2: Power-Aware Scan Chain Assembly


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Example 3: Voltage scaling in scan mode

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Example 3 (contd): Voltage scaling in scan mode


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S

OS

I

PD4

SC1 SC4

PD1

Test

Controller

Power

Controll

Power

Controller

Test

Controller

PD2

SC2

PD3

SC3

Example 4: Power Domain Test Planning

Objective:

(Source: M. Hirech, Synopsys, DATE, 2008)

80



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not

only in logic portions but also

in clock trees (> 50%)

Basic Clock Gating Design

GClk

Clock Gator

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Impact of Clock Gating on Test

Impact on Shift ModeNegative

Impact on Capture ModePositive

Shift Operation Guarantee Needed

Good for LTC Power Reduction

Dynamic In-ATPG Techniques

Static In-ATPG Techniques

Post-ATPG X-Filling Techniques

DfT for Clock Gating Logic


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Example 1: DfT for Clock Gating Logic

Shift ModeSE

SE

Capture ModeSE

Clock Gator

SE

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Example 1 (contd): DfT for Clock Gating Logic

shift mode

SE

capture modeSE

Shift Register Operation

LTC Power Reduction

1

SE

11

SE

0


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Example 2: LTC Power Reduction by Clock Gating

(source: R. Illman et al., Proc. LPonTR, pp. 45-46, 2008)

default value

A preset value is to be used to fill an X-bit in a test cube

Identify all clock gators

For each clock gator, calculate a set of input settings that set the clock off

The values in each input setting are default values..

Generate a test cube for fault detection

Assign default values to the X-bits in the test cube

If there are multiple choices of default values, use the one that can turn-off more FFs.

86

Example 2 (contd): LTC Power Reduction by Clock Gating

Test Cubes after ATPG Test Cubes after Assigning Default Values

Default Values

S1 = 0 / S2 = 0

S1 = 1 / S2 = 1



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Example 2 (contd): LTC Power Reduction by Clock Gating

Circuit Statistics


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Summary

shift mode

capture mode

Assign pre-determined clock-gator disabling values to dont-care bits

(X-bits) in a test cube initially generated for fault detection.

Find and assign proper logic values to dont-care (X-bits) in a test

cube so as to disable as many clock gators as possible.


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89


90

Typical Power Management (PM) Structures

Unified Power Format Common Power Format


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Segmented Switch

Segmented Switch

Header Switch Footer Switch Symmetric Switch

Header Switch/ Footer Switch/ Symmetric Switch

Example 1: Test for Power Switches

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Example 1 (contd): Test for Power Switches

Test for Short TE standby_t

Out Out

Test for Open TE standby_t

Out Out

from powercontrol logic

(source: Goal (NXP) et al., Proc. ETS, pp. 145-150, 2006)


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Example 2: Parametric Test of Micro Switches

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Example 2 (contd): Parametric Test of Micro Switches


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Example 2 (contd): Parametric Test of Micro Switches

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Example 3: Test for State Retention Registers (SRRs)

Master

Latch

Retention

Latch


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Example 3 (contd): Test for State Retention Registers (SRRs)

SRR

V

(2) Save

Restore

V

Repeat for V = 0 and V = 1

Retention Capability Test

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Example 4: Test for Isolation Cells - (1)

SLEEP_1

SLEEP_2

ISO_1 OUT

OUT


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Example 4: Test for Isolation Cells - (2)

OR

Power Domain OFF

Power Domain ON

Check for 1

AND

Power Domain OFF

Power Domain ON

Check for 0

FF

Power Domain OFF

Power Domain ON

Check for 0 and 1

Power Domain ON

Power Domain ON

Power Domain ON

100

Example 5: Test for Level Shifters

Power Domain 1 Power Domain 2

Level Shifter

Test as a whole under all power supply voltage combinations

of Power Domain 1 and Power Domain 2.

(VDD-1, VDD-2, ) (VDD-a, VDD-b, )


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101

Example 6: Test for Power Mode Control Logic in SRAMs

Low-Power SRAM

corecellarray

IOIO control

wordlinedriver

corecellarray

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Summary


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103

(source: CADENCE, 2007)

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Solutions for high quality at-speed fault coverage are needed !


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105

Synopsys:

http://www.synopsys.com/Tools/Implementation/RTLSynthesis/Test/Pages/def

ault.aspx

106

Mentor:

http://www.mentor.com/products/silicon-yield/logic_test/

Cadence:

http://www.cadence.com/products/ld/test_architect/pages/default.aspx


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Thank You !

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