post layout simulation with cadence netlist/model in...
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2006/May/03 Wei-li TsaiPage 1
Post Layout Simulation with Cadence Netlist/Model in ADS2005A
Agilent EEsof AE
Ming-chih Lin
Wei-li [email protected]
+886-3-4959378
V.02
2006/May/03 Wei-li TsaiPage 2
Introduction
• ADS2005A MSR-1 內建辨識功能，自動認得Cadence Model/Netlist
• XCalibre 做完LPE後，可以輸出Cadence格式的Netlist*
• 擁有ADS2005A, 毋須 import netlist，改用Include的方式，不會更動到Netlist
• Pre-Sim 和 Post-Sim 共用同一個Schematic，切換容易，設定方便。
*不同使用者的XCalibre設置不盡相同，可能需要略微修正Netlist以進行Post Lyaout Simulation.
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Post Layout Simulation Flow Chart
產生Netlist做LVS和LPE
設定XCalibre輸出Cadence Netlist
在ADS電路圖中Include LPE Netlsit
在ADS電路圖中Include Cadence Model
關閉ADS Model
Simulate
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Pre-Layout Simulation
VO_N
VO_P
LIMITER_originalX1
agnd
av dd
PD
I_sink
IN_N
IN_P
VO_P
VO_N
CC2C=1.0 f FC
C1C=1.0 f F
TSMC_CM018RF_PROCESSTSMC_CM018RF_PROCESS
Resistance=Ty picalCornerCase_3p3M=TT_3MCornerCase_1p8M=TT_MCornerCase_3p3NA=TT_3VNACornerCase_1p8NA=TT_NACornerCase_33=TT_3VCornerCase_18=TT
Si - Substrate
TSMC RF CMOS 0.18um
TranTran1
MaxTimeStep=0.1 nsecStopTime=10.0 nsec
TRANSIENT
I_DCSRC5Idc=350 uA
VtSineSRC7
Phase=180Damping=0Delay =0 nsecFreq=2.4 GHzAmplitude=0.49 VVdc=1.109 V
VtSineSRC6
Phase=0Damping=0Delay =0 nsecFreq=2.4 GHzAmplitude=0.49 VVdc=1.109 V
V_DCSRC2Vdc=1.8 V
進入下一層，產生spi給Calibre做LVS和LPE
Pre-Sim的電路LIMITER_original
– 範例電路：SIM_Limiter_Tran.dsn
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Export Netlist to Calibre
VO1_PVO1_N
VO2_N
VO2_P
VO_P
VO_N
PortagndNum=7
PortavddNum=8
PortVO_PNum=6
PortVO_NNum=5
PortPDNum=4
TSMC_CM018RF_NMOSMN12
Port
IN_PNum=1
PortIN_NNum=2 TSMC_CM018RF_NMOS
MN6
TSMC_CM018RF_NMOSMN11
TSMC_CM018RF_NMOS_RF
MN1TSMC_CM018RF_NMOS_RFMN0
TSMC_CM018RF_NMOS_RF1
TSMC_CM018RF_NMOS_RFMN4
TSMC_CM018RF_NMOSMN9
TSMC_CM018RF_RESR1
TSMC_CM018RF_NMOSMN7
TSMC_CM018RF_NMOSMN3
TSMC_CM018RF_NMOSMN2
TSMC_CM018RF_NMOS_RFMN8TSMC_CM018RF_NMOS_RFMN10
TSMC_CM018RF_RESR6TSMC_CM018RF_RES
R5TSMC_CM018RF_RESR4
TSMC_CM018RF_RESR3TSMC_CM018RF_RES
R2
PortI_s inkNum=3
範例電路：Limiter_original.dsn。產生Netlist給Calibre的方法，請參閱Application Note—how to generate Netlist to do LVS
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LPE: Setup in XCalibre
1. XCalibre中，可以選擇LPE輸出的格式，有HSPICE和Cadence兩種，請選擇Cadence 格式
2. 如果XCalibre產生的檔案，附檔名不是.scs時，如.pex或.dist，請手動改為.scs (有時候，XCalibre會將寄生元件另外放在一個.pex檔中）
3. 請將選項”Hierarchical name separator”，由原本的”/”改成”_”(底線）
• 如果沒有將“/”改成“_”時，XCalibre 在加寄生元件時，會表示為R12\/rxx1。
(R12是您電路中的電阻，rxx1則是寄生電阻的代號。 )
• 因為\/是ADS內部保留符號，所以會相衝突。
• 改成”_”（底線）後，當XCalibre產生寄生電阻時，名稱表示為ADS R12__rxx1。
• 對於既有的Netlist,可用文字編輯器如 Wordpad 或 vi，gedit (Unix or Linux)，用 Find and Replace 的功能，一次將”\/”符號，置換成“_”。
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After LPE, Include Netlist into ADS
雙擊”Netlist Include”，指向XCalibre產生的limiter_original.scs
1
2
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Put “Netlist Include” Tab1
2將Spectre Model 掛進來,細部操作如後2頁所示
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Setup the Spectre Model and Section
Double click the Tab
按 “browse” 鍵指向Model file,並填入Section.
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Include multiple models
Press “Add” to include multiple models
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Instance Name is Case sensitive
Case Sensitive, 大小寫必須一致。
Netlist的檔名則沒有大小寫限制。
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Disable ADS design Kit’s Model
將ADS Model 關閉後，即可開始模擬
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m1time=VO_P=376.4mV
4.347nsecm2time=VO_P=1.830 V
4.582nsec
4.5 5.0 5.5 6.0 6.54.0 7.0
0.5
1.0
1.5
0.0
2.0
time, nsec
VO
_P
, V
m1
m2
m1time=VO_P=376.4mV
4.347nsecm2time=VO_P=1.830 V
4.582nsec
Post Simulation Result
Examine Simulation Result
2006/May/03 Wei-li TsaiPage 14
Switch Back to Pre-Simulation1. 將ADS Model啟動 2. 將Spectre Model關閉
3. 將LPE的Netlist關閉 4. 進行模擬 （Pre-Simulation)
VO_N
VO_P
TSMC_CM018RF_PROCESSTSMC_CM018RF_PROCESS
Resistance=Ty picalCornerCase_3p3M=TT_3MCornerCase_1p8M=TT_MCornerCase_3p3NA=TT_3VNACornerCase_1p8NA=TT_NACornerCase_33=TT_3VCornerCase_18=TT
Si - Substrate
TSMC RF CMOS 0.18um
NetlistIncludeNetlistInclude1
UsePreprocessor=y esIncludeFiles[1]=limiter_original.scs IncludePath= C:/test_ADS_f low
NETLIST INCLUDE
NetlistIncludeNetlistInclude2
IncludeFiles[5]=rf 018.scs tt_mos3vIncludeFiles[4]=rf 018.scs tt_resIncludeFiles[3]=rf 018.scs ttIncludeFiles[2]=rf 018.scs tt_rf mosIncludeFiles[1]=rf 018.scs tt_rf res_hri
NETLIST INCLUDE
LIMITER_originalX1
agnd
av dd
PD
I_sinkIN_N
IN_P
VO_P
VO_N
TranTran1
MaxTimeStep=0.1 nsecStopTime=10.0 nsec
TRANSIENT
V_DCSRC2Vdc=1.8 V
VtSineSRC6
Phase=0Damping=0Delay =0 nsecFreq=2.4 GHzAmplitude=0.49 VVdc=1.109 V VtSine
SRC7
Phase=180Damping=0Delay =0 nsecFreq=2.4 GHzAmplitude=0.49 VVdc=1.109 V
I_DCSRC5Idc=350 uA
CC1C=1.0 f F
CC2C=1.0 f F