porting freertos on openrisc
DESCRIPTION
TRANSCRIPT
Porting FreeRTOS on OpenRISC
Speaker:Yi-Chiao Lin
• Motivation
• OpenRISC
• Porting FreeRTOS on OpenRISC
• Experiments
Outline
Multi-Tasking Management Support
• Round-Robin 、 FIFO ……
Memory Management Unit Support
• TLB、Page Table ……
On-chip Memory Architecture Support
• Cache and SPM (scratch pad memory)
Motivation
Scratch Pad Memory(SPM)
• Software controlled on-chip memory
• Consume less energy than cache
SPM (scratch pad memory)
• Motivation
• OpenRISC
• Porting FreeRTOS on OpenRISC
• Experiments
Outline
Or1200 Open Hardware CPU released
Implemented in the Verilog
5-stage pipeline
32 register
Special-Purpose Registers
OpenRISC
l.mfspr / l.mtspr
MMU、Cache、Interrupt……
OpenRISC
Enable/Disable
• Motivation
• OpenRISC
• Porting FreeRTOS on OpenRISC
• Experiments
Outline
Real time operating system
Designed to be small and simple(2k~3k)
Stack can be shared between tasks
For free!!
FreeRTOS benefit
Task Create
xTaskCreate(
pdTASK_CODE pvTaskCode,
const portCHAR * const pcName,
unsigned portSHORT usStackDepth,
void *pvParameters,
unsigned portBASE_TYPE uxPriority,
xTaskHandle *pvCreatedTask )
void vRtosTask(void *pvParameters){
while(1){
.........
}
}
Task
xTaskCreate
prvAllocateTCBAndStack( usStackDepth, puxStackBuffer
);
prvInitialiseTaskLists();
prvInitialiseTCBVariables( pxNewTCB, pcName, uxPriority, xRegions,
usStackDepth );
prvAddTaskToReadyQueue( pxNewTCB );
• FreeRTOS porting file :
1. Port.c
2. Portmacro.h
3. Portasm.S
4. Port_spr_def.h(OpenRISC)
(Definition of special-purpose registers)
FreeRTOS/Source/portable/[Platform]
FreeRTOS Porting
FreeRTOS Porting
Ported layer Port.c Portmacro.c Portasm.S Port_spr_def.h
Kernel layer
Application layer
Pagetable.c
TLB-miss ISR
Software(FreeRTOS)
Timer ISR
task.c
Data Moving ISR TLB.c
cache.c Interrupt handler
Reset.S
Hardware(OpenRISC) SPM Redirector
Page miss
Bookkeeping
Port_spr_def.h
Portmacro.h
Define Kernel Type
pxPortInitialiseStack
vPortDisableInterrupts
vPortEnableInterrupts
prvSetupTimerInterrupt
xPortStartScheduler
port.c
port.c (*pxPortInitialiseStack)
PxCode
uTaskSR
r31:0x00000031
r30:0x00000030
r29:0x00000029
.
.
.
High address
Low address
vPortDisableInterrupts
vPortEnableInterrupts
port.c
Exception Handler Exception type Vector offect[11:0] Example
Reset 0x100 Caused by Software or
Hardware reset
Bus error 0x200
Data Page fault 0x300
Instruction Page fault 0x400
Tick Timer 0x500 Timer interrupt
Alignment 0x600
Illegal Instruction 0x700
External interrupt 0x800 External interrupt asserted
D-TLB miss 0x900 No matching entry in DTLB
I-TLB miss 0xA00 No matching entry in ITLB
Range 0xB00
System call 0xC00
Float Point 0xD00
Trap 0xE00
Exception Program Counter Registers
Exception Supervision Registers
Exception Effective Address Register
Exception Register
Maximum timer count of 2^32 clock cycles
Tick Timer
TTMR
TTCR
RISC Clk Tick INT
Tick Timer Mode Register
Tick Timer Counter
prvSetupTimerInterrupt
Port.c
xPortStartScheduler
Task 1
Task2
Memory
Stack_TCB
Stack_TCB
Setup Timer
Load register
Load TCB
• Context Switch
portSAVE_CONTEXT
portRESTORE_CONTEXT
Portasm.S
Task1 Task2
Stack_TCB Stack_TCB
Portasm.S (Tick Handler)
Reset register
Set Stack point、Clear BSS
Reset Cache、MMU、UART
Reset.S(Booting)
OpenRISC Start at 0x100
Clear general-purpose registers
Reset register
Set Stack Pointer
Clear BSS
Clear BSS (Block Started by Symbol)
• Flush Cache
Data Cache Block Invalidate Register
Cache
D-cache 8k 512Line 4word
PPN[31:13] 0x1[12:4] 0x8[3:0]
Physical [31:13]
Physical [31:13]
Physical [31:13]
Physical [31:13] WORD
WORD
WORD
WORD
WORD
Physical [31:13] V
V
V
V
V WORD
WORD
WORD
WORD 0
1
2
3
4
5
6
7
2047
0
1
2
3
511
13:2 12:4
Task address space isolation
Allow safe sharing of memory among multiple tasks
Why OS need MMU Support?
CPU
Task1
Task2
Virtual
Task 1
Task2
Memory
Physical
Page Index Level 1[31:24] Page Offset[12:0] Page Index Level 2[23:13]
0
255
PTE
PTE2
+
0
2047
Physical Page Number Page Offset[12:0]
+
Address
Page Table entry
Physical Page Number D A WBC CI CC WOM W R W R REV
Entry Store in Memory
Set in Data Translation Lookaside Buffer Translate Registers when
DTLB-MISS
TLB miss Handler
TLB MISS
Find the Task
Find Page Table
Set TLB register
Exception Effective Address Registers
or1200_except.v
Exception Effective Address Registers
DTLB Architecture
Virtial address[19:31] Index[13:18] Offset[12:0]
VPN [19:31] V
VPN [19:31] V
VPN [19:31] V
VPN [19:31] V
PPN [13:31]
PPN [13:31]
PPN[13:31]
PPN [13:31]
PPN [13:31] VPN [19:31] V
Direct mapped
相等
&& V=1
Physical address[13:31] Offset
DTLB miss
DTLB Match Register
DTLB Translate Regidter
EEAR:0x6000
W R W R CI
W R W R CI
W R W R CI
W R W R CI
W R W R CI
Super User
W R W R CI
Waveform
DTLB Miss
0x900
Interrupt ->
Dmmu Disable
0x100->0x20000100
Interrupt ->
Dmmu Disable
0x100->0x20000100
FreeRTOSConfig.h
Set Total Stack、SYSCLK……
• Set Uart Base Address、System CLK……
• Cache size set……
Board.h
Modify OpenRISC memory architecture
CPU
D-MMU
Data ram
Wishbone bus
Redirector
D-Cache SPM
Page miss
Bookkeeping
circuit
Interrupt
PIC (Programmable Interrupt Controller)
Page miss
Bookkeeping
circuit
or1200_cpu.v external_interrupt.v
or1200_pic.v
spr_cs
spr_we
spr_addr
spr_dat_i
intr
spr_dat_o
clk
rst
pic_int[31:0]
SPM data moving interrupt handler
Free SPM
space?
Interrupt
Select a victim page and
move it to Data ram
Move the page into SPM
No
Yes
Update D-TLB
Translate Regidter
Update Page table
• Motivation
• OpenRISC
• Porting FreeRTOS on OpenRISC
• Experiments
Outline
Verify on FPGA Board
Verify on FPGA Board
VeriComm
Dump Counter
學習移植OS與底層硬體的整合
善加運用身邊工具Debug
更加了解CPU之運作
Summary