pll basic linkedin2
TRANSCRIPT
1Goldman Technology 1/26/2012 Page 1
PLL Basics 2PLL Basics 2--2828--20092009Stan GoldmanStan Goldman
Goldman TechnologyGoldman Technology
Goldman Technology 1/26/2012 Page 2
PLL Basics Agenda
• History
• Applications
• Overview of PLLs
• Background information
• Control Systems
• Test and Measurement
• References and Background Material
Goldman Technology 1/26/2012 Page 3
History
• De Bellescize in 1932– Synchronous reception of radio signals
– Received audio amplified to speaker
• Television, 1st wide spread use– Synchronization of horizontal and vertical scan
in television
Goldman Technology 1/26/2012 Page 4
Applications
• Frequency multiplier by multiplying the frequency of the reference oscillator.
• Modulator by adding the modulating signal to the phase error.
• Demodulator by tracking the changes in modulation to the reference input.
• Coherent receiver by operating as a narrow band tunable filter to track the carrier frequency.
• Data synchronizer by operating as a narrow band tunable filter to recover the clock.
Goldman Technology 1/26/2012 Page 5
Serializer/Deserializer
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Hard Disk Drive
Goldman Technology 1/26/2012 Page 7
Wireless
CELL PHONE
Goldman Technology 1/26/2012 Page 8
KEY PLL DESIGN REQUIREMENTS
• Architecture
• Loop Stability
• Frequency Range
• Time Jitter
Goldman Technology 1/26/2012 Page 9
PLL Control System Block DiagramWith Phase Relationships
θ
i θ
i
θo
nmf
θ0
[Goldman 2007 p19]
Goldman Technology 1/26/2012 Page 10
Key Signals of Interest within a PLL
• Input frequency or reference frequency
• Output frequency
• Tune voltage or current input to the VCO or CCO
• Phase error (comparison of the positive edge of the reference input signal to the phase detector with the positive edge of the feed back signal from the VCO to the phase detector with the positive edge of the reference input as the trigger source)
Goldman Technology 1/26/2012 Page 11
Ideal VCO Transfer Function,Transduces Voltage to Frequency (Edges)
ωout=ωoff+Kv Vtune ωout=∆θout/∆t
To = 2 M Td
[Goldman 2007 p3]
1 E9
8 E8
4 E8
0
Goldman Technology 1/26/2012 Page 12
Relationship of Phase/Frequency in VCO,(1/s transfer function relationship)
• Mathematical description of a phase modulated signal, from Taub and Shilling, Principles of Communication Systems, p117 and modified with PLL terminology:
Instantaneous Frequency
Deviation of instantaneous frequencyfrom ωc which equals ω ref in modeling
V o t( ) V a cos ω c t⋅ K v tV tune t( )⌠⌡
d⋅+
⋅
ωt
ω c t⋅ K v tV tune t( )⌠⌡
d⋅+
d
dω c K v V tune t( )⋅+
fo
ω ωc t⋅−
2 π⋅
Kv Vtune t( )⋅
2 π⋅
θ oi ω c t⋅ K v tV tune t( )⌠⌡
d⋅+
θ o θ ω c t⋅− K v tV tune t( )⌠⌡
d⋅ K v1
s⋅ V tune s( )⋅
Instantaneous phase
Deviation of instantaneous phase
Goldman Technology 1/26/2012 Page 13
Digital Phase Detector Timing and Response to Ramped VCO Phase
V C O I N
R I N
V DD
V DD
U P
D O W N
QCC L
QCC L
D Q
D Q
Reset
Goldman Technology 1/26/2012 Page 14
Ideal Phase Detector Transfer Function,Transduces Frequency (Edge) Differences to Voltage
Vpdavg=Kd θe (5MHz Ref. Freq.)
[Goldman 2007 p2]
-200 -100 0 100 200Ref. – VCO Edge (ns)
Goldman Technology 1/26/2012 Page 15
Output of Analog Phase Detector vs Phase Error (-cos) with Various Measures of Abscissa
[Goldman 2007 p18]
Goldman Technology 1/26/2012 Page 16
Example of Lock, Digital Loop(In Phase)
[Goldman 2007 p4]
Goldman Technology 1/26/2012 Page 17
Mathematical Relationship of Phase and Frequency (Analog Phase Detector)Phase detector as a mixer (analog multiplier)
Signal DefinitionMixing of Two Signals
Eliminating the high frequency productwith a low pass filter yields
Slope
Phase Detector Gain
Kd=Vpbeat
where:
Vpds ( φ)= Phase detector phase slope (volts).
Vpds(θe) = Vpbeat sin(θe )
V pdsθ e
V pbeat cos θ e( )⋅d
dV pbeat sin θ e( )⋅
V1(t) V2(t) =Vp1 Vp2 0.5 [ cos(ωrf t - ωlo t + θe ) ]
=Vpbeat cos( ωbeat t + θe )
where: ωbeat= ωrf - ωlo for ωrf > ωlo, Vpbeat= Vp1 Vp2 x 0.5 x mixer losses, and = The resulting voltage level after mixing (volts).
V1(t) V2(t) = Vp1Vp2 cos(ωrf t + θe ) cos(ωlo t )
Using the trigonometric identity for products of a trigonometric function:
V1(t) V2(t)=Vp1Vp2 0.5 [cos ( ωrf t- ωlo t + θe ) +cos( ωrf t + ωlo t + θe )]
where: V1(t) V2(t) = Mixing process.
V1(t)= Vp1 cos(ωrft+ θe ) where: V1(t)= Source 1 signal, Vp1= Maximum amplitude of source 1 (volts), ωrf= Angular frequency of a Signal at the RF port of the mixer (rad./sec), = 2 π frf, θe= Phase error difference between signal 1 and 2 (rad.), and t= Time variable (seconds).
V2(t) = Vp2 cos(ωlo t ) where: V2(t)= Source 2 signal, Vp2= Maximum amplitude of source 2 (volts), and ωlo= Angular frequency of a signal at the LO port of a mixer (rad./sec).
Goldman Technology 1/26/2012 Page 18
Charge Pump Output Transduces Frequency (Edge) Differences to Current, Kp=I/(2 π)
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Loop Classifications
[Goldman 2007 p8]
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Loop Classifications (Continued)
[Goldman 2007 p8]
Goldman Technology 1/26/2012 Page 21
Example of Lock, Analog Loop (Sinewaves) Phase detector as a mixer (analog multiplier)
VCO Tune Voltage
Goldman Technology 1/26/2012 Page 22
Vtune, Input, and Output Signals, Locked (Quadrature)
Goldman Technology 1/26/2012 Page 23
Vtune, Input, and Output Signals, During Acquisition,Searching For Lock
In phase for higher tune voltage Out of phase for lower tune voltage
Goldman Technology 1/26/2012 Page 24
PLL TRANSFER FUNCTION AND CONTROL SYSTEMS THEORY
• Control System's General Equation for a Closed Loop
- =For positive feedback, + =For negative feedback,
=The closed-loop transfer function,
G(s)=Forward transfer function,H(s)=Feedback transfer function,
G(s) H(s)=Open-loop transfer function, andG(s) H(s)=Ratio of 1 and angle of 0 deg for positive feedback
and 180 deg for negative feedback are theconditions for oscillation.
• Closed Loop PLL Transfer Function from General Equation
Co
Ri
θo
θi
( )sG ( )s
1 .G ( )s H ( )s
=Output phase (rad) and=Input phase (rad).
θ0
θi
)()(1
)(
sHsG
sG
R
C
i
o
⋅±=
Goldman Technology 1/26/2012 Page 25
Judging Stability from Step Response
[Goldman 2007 p20]
.2 Damping22 deg. Phase Margin
.42 Damping45 deg. Phase Margin
.035 Damping4 deg. Phase Margin
0
0
3 10 4
3 104
6 104
6 104
Freqeuncy (Hz)
0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010
3 104
6 10 4
Time (s)
30 deg or 45 deg. Phase Margin are levels supported in references
~90% Overshoot
~60% Overshoot
~40% Overshoot
Goldman Technology 1/26/2012 Page 26
PLL Basic Block Diagram For Cascade of Transfer functions for Open Loop Gain
[Goldman 2007 p22]
Goldman Technology 1/26/2012 Page 27
Type 2 Second Order Open Loop Gain Function (Active Filter)
Cascade of Transfer functions for Open Loop GainG(s)H(s)= (Phase Detector Gain)(Filter Transfer Function)
(VCO Transfer Function)(Divider Transfer Function)
Substitute and Rearrange for Open Loop Gain Expression
Substitute and Rearrange for Closed Loop Gain Expression
= Capacitor in the operational amplifier'sfeedback path (F),
= Resistor in operational amplifier's feedback path (ohms) and,
= Resistor at the negative input terminalof the operational amplifier (ohms).
= Phase detector gain (volts/radian),= VCO transfer function gain
constant (radians/second/volt),= Integer divider value,= Loop Frequency Multiplication Factor,= Output frequency/ input frequency,
Kd
nmf
C
R1
R2
.G( )s H( )s ...K
dK
v
..nmf
C R1
1
s 2..s C R
21
Kv
Goldman Technology 1/26/2012 Page 28
Converting to Servo Terminology
Closed Loop Gain Expression
G( )s
1 .G( )s H ( )s
..nmf
ωn
2 .s.2 ζ
ωn
1
s 2 .s .2 ζωn
ωn
2
Error Expression
1
1 .G( )s H ( )s
s 2
s 2 .s .2 ζωn
ωn
2
Open loop gain Expression
.G( )s H ( )s ..ωn
2 1
s 2.s
.2 ζω
n
1
Goldman Technology 1/26/2012 Page 29
Synthesis of Loop Component Values from Servo Terminology
• Active Filter ωn
.Kd
Kv
..R1
C nmf
ζ ..R
2C
2
.Kd
Kv
..R1
C nmf
For selected C value, damping factor, and natural frequency and given Kd and Kv
R1
.Kd
Kv
..ωn
2C n
mf
• Passive Filterω
n
.Kd
Kv
..R1
R2
C nmf
ζ ..1
2
.Kd
Kv
..R1
R2
Cnmf
.R2
C1.K
dK
v
• Charge Pumpω
n
.Kv
Ip
...2 π C nmf
ζ
..Kv
Ip
R2
..2 π nmf
.2 ωn
R2
.2 ζ.ωn C
Goldman Technology 1/26/2012 Page 30
Charge Pump PLL with Regulator
•Charge pump can not drive high current load•1 pin for external components
Goldman Technology 1/26/2012 Page 31
Loop Stability, Bode Plot
[Goldman 2007 p27]
Phase Margin
Gain Margin
Magnitude
Phase
Goldman Technology 1/26/2012 Page 32
Graphical Relationship of Natural Frequency to 0 dB Crossover Frequency
[Goldman 2007 p29]
Goldman Technology 1/26/2012 Page 33
Open Loop Response (ASIC APLL External Components ) 32, 71, 147 MHz
32 MHz
71 MHz
147 MHz
32 MHz
71 MHz
147 MHz
Goldman Technology 1/26/2012 Page 34
Closed Loop Response (APLL)
32 MHz
71 MHz
147 MHz
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Error Function Response
Goldman Technology 1/26/2012 Page 36
Test and Measurement of PLL (Brief)
• Spurious signals, hold in range, and lock range
• Frequency Switching Time
• Jitter
Goldman Technology 1/26/2012 Page 37
Spurious Signals
[Goldman 2007 p357]
Goldman Technology 1/26/2012 Page 38
Hold In Range, Lock In Range
[Goldman 2007 p355]
Goldman Technology 1/26/2012 Page 39
Jitter Measurements
• Oscilloscope (Time Domain)
• Modulation Domain Analyzer
• Spectrum Analyzer ( Frequency Domain)
Goldman Technology 1/26/2012 Page 40
Jitter, Oscilloscope
[Goldman 2007 p388]
Goldman Technology 1/26/2012 Page 41
Relationship of Modulation Domain to Spectrum Analyzer and Oscilloscope
F
T
V
[Goldman 2007 p378]
Goldman Technology 1/26/2012 Page 42
Oscilloscope Measurement of 1 and Multiple Periods
1
1
1 clock period oscilloscope measurement with jitter FM modulation
1 period scope measurement
T
1
1
6 clock periods oscilloscope measurement with jitter FM modulation
6th period scope measurement
T
[Goldman 2007 p380]
Goldman Technology 1/26/2012 Page 43
Frequency Switching Time, Modulation Domain Analyzer
[Goldman 2007 p358]
Goldman Technology 1/26/2012 Page 44
Comparison Table of Measured Data with Comparable PLL References
0.02%/1%80ps p-p12-6000.061mW at 240MHz.065um 1.2VDCAS 2008
All Digital PLL, diff. ring VCO130ps p-p30-1603.12mW at 160MHz.25um 1.9VFahim TCAS '03
Differential ring VCO, VCR
155ps p-p360MHz10-3500.167mW at 200MHz.13um 1.5VHozer ISSCC '02
Differential ring VCO, self biased48ps p-p30-6500.187mW at 240MHz.13um 1.5V
Maneatis ISSCC '03
Single ended ring CCO21ps p-p500-23500.1530mW at 2000MHz.1um 1.2V
K. Minami CICC '01
Supply ControledRing VCO, wide BW, 2.5MHZ BW0.32%/1%[email protected] 1.9VH. Ahn JSSC '00
Regulator included, single ended ring CCO.007%/1%
44ps p-p at 700MHz600- [email protected] 3.3V
J.M. InginoISSCC '01
Simulated, Supply Controlled Ring VCO, wide BW.06%/1%[email protected] 3.3V
S. SidropoulosVLSI '00
Comments
power supply sensitivity, %-fvco/%-VddJitter
VCO Output Frequency (MHz)
Area (mm2) PowerProcessesDescription
Goldman Technology 1/26/2012 Page 45
Recommended PLL Books
1. Stanley Goldman, Phase Locked Loop Engineering Handbook, Artech House, Boston, 2007.
2. Roland Best, Phase Locked Loops Design Simulation, & Applications, McGraw Hill, New York, 1997.
3. Behzad Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, EEE Press, New York 1996.
4. James A. Crawford, Frequency Synthesizer Design Handbook, ArtechHouse, Boston.
5. William Egan, Frequency Synthesis by Phase-Lock, Wiley Interscience, New York, 1981.
6. Floyd Martin Gardner, Phaselock Techniques, Wiley Interscience, New York, 1979.
Goldman Technology 1/26/2012 Page 46
Recommended Background Books
Feedback Control Systems by Charles L. Phillips and Royce D. Harbor
The Fast Fourier Transform by E. Oran Brigham
Network Analysis by Van Valkenburg
Analysis and Design of Analog Integrated Circuits by Paul R. Gray and Robert G. Meyer
Principles of CMOS VLSI Design by Neil H. E. Weste and Kamran Eshraghian
Principles of Communicaton Systems by H. Taub and D. L. Schilling
Goldman Technology 1/26/2012 Page 47
External Websites
• Texas Instruments, High Performance PLLshttp://www.ti.com/sc/docs/products/msp/clock/pll/overview.htm
• National Semiconductorhttp://www.national.com/appinfo/wireless/
• Frequency Response Analysis and Design Tutorialshttp://me.www.ecn.purdue.edu/~me475/ctm/freq/freq.html
• Chip Directoryhttp://icat.snu.ac.kr/chipdir/f/pll.htm
• Phase Locked Loop Fundamentals ( Minicircuits)http://www.minicircuits.com/appnote/vco15-10.pdf
• Monolithic CMOS RF Transceiver (Berkeley)http://kabuki.eecs.berkeley.edu/rf/rf.html
• Analog IC Design, Dr Hellums (UTD)http://www.utdallas.edu/~hellums/
• PLLs , Stan Goldmanhttp://home.tx.rr.com/sgold_1