plecs-piece-wise linear electrical circuit simulation for simulink

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bination of both. External in this context means that the control

signal does not directly depend on voltages or currents in the

circuit but

is

instead supplied by the overlaying control system.

Examples for externally controlled switches are breakers and

half-bridges of VSIs. Internal control variables are voltages or

currents that can be measured in the circuit. The simplest ex-

ample of a purely internally controlled switch is a diode, which

is switched on by a positive voltage and off by a negative cur-

rent. Power electronic components such as thyristors,

GTOs

and IGBTs operate according to a logical combination of ex-

ternal and internal switching conditions.

Example: Buck Converter

As

an example, Fig.

1

to Fig.

3

show the schematic of a buck

converter, its implementation model in PLECS, and the corre-

sponding netlist. The voltage source

v-src

between the

nodes

nl

and

gnd

is controlled by the signal

input-1

which is imported from Simulink. The transistor is modelled as

the ideal switch s-T controlled by the imported signal

gate-1.

The switch is closed when the first condition is true,

i.e.

gate-1

is not equal zero. The second condition opens

the switch.

The ammeter am-D and the voltmeter m - D measure

the current through and the voltage across the diode. Their out-

puts are used in the switching conditions of the internally con-

trolled switch s-D. When the voltage across the diode

becomes positive the diode startsconducting. The diode blocks

when the current becomes negative.

The current measured by the meter

am-L

is exported back

to Simulink. There, it can be viewed with a scope or used in a

control loop, e.g. a hysteresis type control (Fig.

4).

III. STATE-VARIABLE EQUATIONS

A.

Setting

up

the Equation System

The algorithm of PLECS is based on state-variable equa-

tions, where the states represent storage components i.e. induc-

tors and capacitors.

A

circuit containing only linear

components can be described mathematically by one set of dif-

ferential equations:

x = A x B u (1)

y = C x D u

(2)

If the circuit contains one or more switches every combina-

tion

3

of switch positions yields a different linear circuit to-

pology and therefore a different set of equations characterized

by the matrices

A , , B , C , ,

nd

D , .

Having

n

switches the

system could have

2

different topologies. Thus, even if not

all

of the

2

opologies are needed in

a

simulation, the state

space approach is only practical if the matrices can be generat-

ed automatically.

For this purpose the independent mesh and node equations

must be set up according to Kirchhoff s voltage and current

Fig.

1:

Buck converter

grid I

Fig.

2:

Implementation model

of

the buck converter

v.v-src

s

s-T

am.

am-D

vm . m-D

s.s-D

am. am-L

l . L

r.R

c.c

r . G

nl gnd

i-D

gnd n3

>> v-D

gnd n3

0

i-D

> output-1

n4 n5

=

.1

n5 n6 = . 0 5

n6 gnd = le-3

n6 gnd = 10

Fig. 3:Netlist for the buck converter

v rc

4 U

PLECS y

i-L

1

-

i-ref

+

Sum Relay: +/-O. j Buck converter

Fig. 4: Sirnulink model of the controlled buck converter

law.

A

circuit with

e

arbitrary elements, i.e. branches, and

n

nodes has

e - n

1 independent mesh equations and

n -

1

independent node equations. In these equations the voltages

and currents of switch elements are left undetermined. After

the elimination

of

dependent variables, e.g. by applying

Ohm s

law to resistors, the reduced generic equation system describ-

ing the circuit is obtained. It is valid for any combination

of

switch positions. The variables are ordered as follows:

T

[x Y

s

x U]

where:

[. e

vc

1L

T

(state derivatives)

(3)

(4)

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T

y

=

[vout iouJ (output variables) ( 5 )

0 0 0 0 0

s = [vs idT

(undetermined switch variables)

( 6 )

0 0 0 0 0 0 1 0 0 0 0 1

0

0

1 0 0 - 1 0 -

x

=

vc

idT

(state variables)

7)

U

= [v

isrJT (input variables)

8)

In order to derive the matrices

A , ,

B , , C , nd

D

for a

specific topology from this generic equation system the voltag-

es across closed switches and the currents through open

switches are set to zero. Then the equation system is trans-

formed to the reduced row echelon form using Gauss Jordan

elimination with partial pivoting. In the reduced row echelon

form A , , B ,

C ,

nd D , appear as sub-matrices:

9)

I represents the identity matrix. The rows marked with

X

contain additional information about the switch variables

which is of no further interest here.

Example: Buck Converter

This method is illustrated using the example of the buck

converter. The independent mesh and node equations are:

0

= VT-VD -V

(10)

iL.L

=

-vD-vC-iL.

R

11)

0

=

iT+iD-iL 12)

vc .C

=

-vc .G+iL 13)

The output variables are:

This yields the generic equation system:

15)

0 0 0 0 0

O O O O

0 0 0 0 0

c o o o o

0 0 1 0 0

0 0 0 1 0

0 0 0 0 1

1 - 1 0 0 0 0 - 1

0

-1 0

0

-1 -R

0

0 0

1 1 0 - 1 0

0 0 0 0 - G 1 0

0 1 0 0 0 0 0

0 0 0 0 0 1 0

0 0 0 1 0 0 0

For example, for a conducting transistor (i.e. vT

=

0 ) and a

blocking diode (i.e.

i, =

0 ) the specific equation system has

the following form, where the matrices

A , ,

B , , C , , D , are

indicated:

0

1

0

0

0

0 0

0 0

0

0

0

0

0

0

1 0 0 0 0

0 1 0 0 0

0 0 1 0 0

0 0 0 1 0

0 0 0 0 1

0 0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

1 0 0 0

1 0

0 0 0 1 0 0 0 1 0 -1 o ]

B.

Implementation in Simulink

The state-space equations are embedded in Simulink by

means of an S-Function which is entirely programmed in C.

The interaction between this S-Function and Simulink is out-

lined in Fig. 5. At any integration step the actual states x and

inputs

U

are fetched from the model workspace. The state de-

rivatives re then computed according to

1)

and passed on

to the Simulink solver. There, they are integrated along with

the control system. The user has the choice between various

solving algorithms offered in Simulinks simulation parame-

ters menu.

At the same time, the system outputs

y

are calculated ac-

cording to

2)

and written back to the model workspace. The

switch manager decides which set of matrices has

to

be used.

This decision is based on the system outputs and the gate in-

puts

g

.

IV. CONTROL OFIDEAL SWITCHES

The switch manager constantly monitors the system output

and the gate signals and compares them with the thresholds

given in the switching conditions. The switching conditions

form the boundary of a specific topologys validity. If any

boundary condition is violated the switch manager toggles the

respective switch(es).

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controlled both by internal and external conditions. For com-

parison both examples are also simulated with the Power Sys-

tem Blockset and with Saber. All simulations have been

performed on a Sun Ultra 1C/200 MHz.

Simulation Program

Simulink/ Power System Blockset

A.

Example I Switched RC network

Fig. 7 shows the schematic of a RC network. The switches

S ands operate in anti-phase. When S is closed and

s

open the

capacitorC is charged via the resistors

RI

and R2. When S

is

open and

5

losed

C

is discharged through R2. The capacitor

voltage vc is used in a control loop as shown in Fig. 8. Sim-

ulink generates a repeating sequence in which the signal rises

linearly from

0

to 10V in 4.9 ms and falls back to

0

in 0.1 ms.

This ramp is compared with VC As long as

vc

is greater than

the ramp signal switch S is closed, otherwise open. The closed

form steady state solution for the circuit is easily determined

(121).

When S has been closed at t =

t l

he capacitor voltage is

CPU

time

33.49 s

When S has been opened at t = t 2 , he capacitor voltage is

1- ,

Saber

The resulting capacitor voltage in steady state operation and

the ramp signal are depicted in Fig. 9(a). Fig. 9(b) shows the

relative error of the simulated capacitor voltage with respect to

the analytical solution. The corresponding simulation times for

a time span of 0.1

s

are listed in Table I. Of course, in all pro-

grains there is a trade-off between the requested accuracy and

the resulting speed. The poor accuracy of the Power System

Blockset stems from the snubber circuits that have to be used

with any kind of switch.

6.58 s

B.

Example

2:

6-Pulse Controlled Rect$er

Simulink

/

PLECS

The schematic of a 6-pulse rectifier is outlined in Fig. 10.

The 3-phase grid is modelled by the 170V/50Hz voltage

sourcesVa,b,c and the impedance LN=

0.001

H. The DC load is

represented by the resistor RL

=

1 4 he inductance LL =

0.02 H, and the voltage source vL

=

120V.

The thyristors of the rectifier exemplify switches controlled

by both external and internal conditions: A thyristor can be

fired only if there is a positive voltage from anode to cathode

and will extinguish when the current becomes negative.

The DC current

id

is controlled in a feedback loop according

to Fig. 11.The difference between the reference currenti,f

and id is fed into a PI-controller. Its output is used as the alpha

order to generate the firing pulses for the thyristors. The pulse

generation is synchronized with the line to line voltage at the

rectifier input.

0.34 s

L

Fig.

7:

Switched RC network

U

PLECS

y

9

Switched

RC

Fig.

8:

Simulink model of the switched RC example

5

104-.

. . . . . .. . _ . _ .

5

0

2

4 6

8

10

time

ms)

Fig.

9:

(a) Capacitor voltage

and

ramp signal.

(b)

Relative errors

of

the simulation results compared to the exact solution

TABLE

I

Simulation times for the circuit in Fig. 7for a time span of 0.1 s

In order to ensure a proper start-up of the valve group the

reference signal for the DC current irefis kept equal to zero for

the first

10

ms until the pulse generator is synchronized. After

this period it ramps up linearly to 10 A within 20 ms. At t =

60 ms

iref

steps to 25 A.

The simulation results for id and the DC voltage V d are given

in Fig. 12.For this model an analytical solution can not be ob-

tained easily so that the accuracy cannot be determined. How-

ever, all three results show good accordance. The simulation

times for a time span of 0.1 s are listed in Table 11.

359


6/6

C. Other Applications

PLECS has been extensively used in various projects

of

the

Power Electronics and Electrometrology Laboratory. In these

projects, hard- and soft-switching converter and rectifier sys-

tems are investigated. Special interest is taken in the develop-

ment of fast control algorithms.

The largest of the simulation models consists

of

24 switches

and 20 state variables. However, this is not a limit for the size

of systems that can be simulated with PLECS.

VI. CONCLUSIONS

PLECS has been proven as a useful tool for the simulation

of arbitrary electric, especially power electronics circuits in a

Simulink control environment. Circuits are entered as netlists

and seamlessly integrated into Simulink as S-functions. Thus,

full benefit can be taken from Simulinks highly accurate inte-

gration algorithms.

Switches are modeled as short and open circuits, the actual

state of which may depend on internal and external conditions.

The use of Simulinks zero crossing detection ensures that the

exact switching instants

are

hit.

For models where ideal switches are to be simulated PLECS

is superior to both circuit simulation programs such as Saber

and the existing Power System Blockset regarding speed, ac-

curacy and stability.

REFERENCES

1.

P. Barnard, New Power System Blockset Enables

You

to

Model Electrical Power Systems, Matlab Newsletter,

pp. 1 11, Summer 1998

D.Bedrosian and J. Vlach, Time-Domain Analysis of

Networks with Internally Controlled Switches, IEEE

Transactions on Circuits and Systems

-

, vol. 39, no. 3,

R.

J. Dirkman, The Simulation of Circuits Containing

Ideal Switches, IEEE Power Electronics Specialists

Conference, pp. 185-194, June 1987

A.

Massarani,

U.

Reggiani and M.

K.

Kazimierczuk,

Analysis of Networks with Ideal Switches by State

Equations, IEEE Transactions on Circuits and

Systems

-

, vol.

44,

o. 8, pp. 692-697, August 1997

2.

pp. 199-212, Much 1992

3.

4.

ig. 10: 6-pulse controlled rectifier

U

line

to

line voltages

out@g PLECS y d ? DC

current

v-1-1

alpha

6-Pulse Rectifier

Pulse

generator

alpha i-en

Pl-controller

i-ref

Fig. 11: Sirnulink model

of

the 6-pulse conuolled rectifier

3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0

0.02 0.04 0.06 0.08

0.1

time

s)

Fig. 12: Simulation results

for

the circuit in Fig. 10

TABLE 1

Simulation times

for

the circuit in Fig. 10

for

a time span

of

0.1

s

CPU

time

Saber 39.30

360

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