pixel electronics for atlas · peter fischer, bonn university pixel 2000, genova, june 5-8, 2000...
TRANSCRIPT
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Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Pixel electronics for ATLAS
Peter Fischer, Bonn university
for the ATLAS pixel collaboration
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2 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Outline
• Overview of electronic components
• On-chip electronics:
− DORIC and VDC: chips for the optical link
− MCC: module controler chip
− FE-Chips: charge amplifer and readoutsingle chip & module performance
• Status and Outlook
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3 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
The ATLAS pixel modules
Flex Capton (barrel 1 & 2, disks)- Capton with routing glued to sensor- Chips connected with wire bonds
FE-Chip FE-Chip
sensorMCC
FE-Chip MCC
inactive sensor area⇐⇐⇐⇐ sensor
sensor: 47104 pixels, 16.4 × 60.8 mm2
MCMD (B-layer)- Multi-layer structure (busses) on sensor- All chips connected with bumps
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4 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Electronic components of the pixel system
1 Sensor16 front end chips (FE)1 module controler chip (MCC)2 VCSEL driver chips (VDC)1 PIN diode receiver (DORIC)
module control room
Opto ReveiversReadout Drivers (ROD)Readout Buffers (ROB)Timing Control (TIM)Slow Control, Supplies
11FE chips
FE chips
2880
1
11
1
Sensor 16 chips MCC
1
4 fast + 4 slow
2DORIC
VDC
Op
to P
acka
ge
PIN
VCSEL
VCSEL
3 fibres/module
Op
to C
ard
RO
D
RO
B
TIM
CTRL
2880
~30
Power supplies
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5 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Data transmission: VDC and DORIC
DMILLprototype chips
(Siegen, OSU,Wuppertal)
VDC:- drive VCSEL laser (digital signals @ 80 Mbit/s)- readjust current after irradiation- status: - chip works, still under test
DORIC:- amplify PIN diode signal- regenerate 40 MHz clock and data/cmd signal- status: - still some problems...
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6 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
The MCC: Event building & Control
Tasks of MCC:
• Decode data/cmd signal (from DORIC)configuration data‚slow‘ commands‚fast‘ commands (trigger, SYNC, ...)
• Generate control signals for FE chips• Receive serial data from 16 FE chips,
accumulate data in FIFOs• Check consistency of event (‚score board‘)• Build complete module event• Send event to DAQ (via VDC)• Error handling, fault conditions (disable
defective FE chips, ...)
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7 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
MCC: full prototype in AMS 0.8µm
• Chip isfully operational
• Has been usedsuccesfully on manymodules
• Meets basically allour specifications
• Size: 6.3 x 10.6 mm2
• Uses synthesizedstandard cellsand full customblocks (FIFO, IO)
• Design in Genova
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8 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Forward disks Barrel 2
Barrel 1
B-layer
MCC-D0 prototype in DMILL• DMILL Prototype with one input channel exists• works @ 100 MHz• Detailed simulations (Marseille) were done to
- check data rates, hit losses- simulate error conditions- fix FIFO size.
• Example: data rate FE MCC per link:
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9 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
The front end chips• Chip size: 7.4mm × 11mm• Pixel size: 50 µm × 400 µm• # pixels: 18 columns × 160 rows = 2880• ~ 700.000 transistors• Mirrored cells in odd/even columns• 40 MHz readout operation• On-chip data buffering until trigger arrives• Serial protocol for command in and data
out, compatible to MCC• Coarse hit amplitude information by reading
Time over Threshold (ToT)• Latest chips use time stamp readout• Fast IO signals are differential low voltage
swings
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10 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
FE Chips: history• Different chip developments in
LBNL, CPPM / Bonn• Final chips are a common design of the
three teams with− analog part of FE-A/C− time stamp readout of FE-B
• Analog part has been prototyped in‚MAREBO‘ chip in DMILL
• Successfull test beams have been donewith full modules with FEB and FEC chips
• Latest chip is (radhard) DMILL chip ‚FED‘it is presently being evaluated
• Honeywell chip ‚FEH‘ is in preparation
• Τwe work with two rad hard vendors
CPPM Bonn
DMILL
MAREBO
DMILL
LEPTON
DMILL
FE-D
Bonn LBNL CPPM
CPPMCPPM Bonn
Honeywell
Bonn CPPM
Bonn CPPM
AMS Bipolar
AMS
Beer&Pastis
AMS CMOS
FE-A (PIRATE)
FE-C (PIRATE)
LBNL
LBNL
2D Array
HP
FE-B
HP
Bonn LBNL CPPM
FE-H
exist
underdesign
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11 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Analog part
• Fast charge sensitive preamplifier with dc current feedback• Discriminator with individual threshold adjust (3 bit DAC with adjustable range)• Measurement of the pulseheight by Time-over-Threshold (ToT)• Mask and test injection in every pixel• Discriminator hit signal is sent to fast OR (‚hitbus‘)• Power consumption is ~40 µW per pixel, VDDA = 3 V, VCCA = 1.5 V
adjust range
C
If
f
DAC3 bit RAM
coarse, global
Inject Bump Pad Preamplifier Trim Mask Hit-OR Time Stamp
RAM
RAM
ROM
7 bit
Hit Data
Pixel ID
Time of
Time ofleading edge
trailing edge
Discriminator
3 bit trim value
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12 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
FED: preamplifier pulse shapes
(Measured on testchip with internal chopper, no sensor)
Very linear discharge good ToT
Very smallshaping loss
Different injected charges Different feedback currents
200 mV/div, 200ns/div 200 mV/div, 200ns/div
~ 1 mip
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13 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Threshold adjustment (3 bit DAC)
• threshold scans for the sameglobal threshold setting,but 8 different DAC values
• Threshold change for 8 trims forvarious range settings
• 10 - 250 e- / bit threshold trim
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14 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Adjusted thresholds
• Reduction of threshold dispersion (chip with sensor)from σthr = 323 e - to σthr = 144e -
0 500 1000 1500 2000 25000
1000
2000
3000
4000
5000
6000
7000
pixel num ber
thre
shol
d [e
- ]
without adjust
with adjust
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15 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
FED: Noise
Offset in load capacitancenot well known
Expected sensor - C
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16 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Time walk
• For correct hit association the time resolution has to be < 25 ns• Problem: higher charge → faster discriminator response• Measure response time with respect to a ‚high‘ reference charge (e.g. 50 ke)• Timewalk is the limiting factor for low thresholds !• Might be recovered if 2 crossings are read out
threshold
Hit times
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17 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
FED: Timewalk
Value for typical settings of preamplifierand disrcriminator bias currents:
require ~2000 e- above threshold for 25 ns
(Measured on FED analog testchip, internal chopper)
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18 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Time stamp readout
• A 7 bit time stamp is distributed to allpixels in the column
• After a hit the time stamps for leading andfalling edge of the discriminator are stored
• The hit is signalized to the end of columnlogic with a fast ripple scan
• Hit pixels are read out and the hit data isstored in EoC buffers.
• The hit pixel is cleared• After the trigger latency, the data is cleared
from the EoC buffers or sent to the MCCwhen a trigger occured
• 24 EoC buffers are used on FED
are
kept
in E
oC b
uffe
rs
RAM
RAM
ROM Pixel ID
Time of
Time ofleading edge
trailing edge
counter7 bit gray
Sca
n fo
r hi
t pix
el
Cle
ar p
ixel
hitflag
arbitrationColumn->EoC
24 EoCbuffers
write
Latency sub
trac
t
FIFO
trigger
hit
ReadoutControler Serializer Serial Out
Hits
with
mat
chin
g le
adin
g ed
ge
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19 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Simulation of hit losses in FED architecture
• Very realistic simulation takinginto account many details of thearchitecture
• Full Luminosity using−Geant tracks−realistic sensor simulation−Lorentz Angle...
• Simulation done in Marseille• Result:
−24 EoC buffers are ok (97% efficiency)−hope to implement more buffers inHoneywell design
Barrel 3
B - layer
Barrel 2
98 % efficiency
(Different curvesare for 10 MHz and20 MHz internalreadout speed. Wecan hopefullychose...)
24 EoC buffersin FED
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20 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
FED readout: layout
Time stamp busses
Pixel control(trim & mask bits)
Analog part
Pixel readout logic
Block of 2 x 16 pixels
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21 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
1 control bit
Injection
ChopperPreamp
4 Current
DACs
Threshold Discr. Mask
Current
DAC
Curr.
DAC DACs
2 Volt.Current
DAC
Hitbus
readout
circuit in every pixel
Select
Current
Reference
1 control bit 3 control bits
Additional analog control blocks on the FE chip
• Injection Chopper has 2 ranges:− high charge mode: ~ 0...10 fC− low charge mode: ~ 0...1 fC
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22 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Example of analog control blocks: DACs
0 32 64 96 128 160 192 224 256-0,4
-0,3
-0,2
-0,1
0,0
0,1
0,2
0,3
0,4
ICHOPPER output and nonlinearity
Mis
mat
ch [L
SB],
LSB
= 0.
86µA
ICHOPPER DAC setting
0
30
60
90
120
150
180
210
240
ICHO
PPER
out
put c
urre
nt [µ
A]
0 4 8 12 16 20 24 28 32-0,03
-0,02
-0,01
0,00
0,01
0,02
0,03
VCCD output and nonlinearity
Mis
mat
ch [L
SB],
LSB
= 32
.2m
V
VCCD DAC setting
0,0
0,5
1,0
1,5
2,0
2,5
3,0
VCC
D ou
tput
vol
tage
[V]
Two 5 bit voltage DACs:• global threshold setting• Shaping of AC coupling• ‚rad hard‘ design
• Nonlinearity < 0.03 LSB
Seven 8 bit current DACs:• Bias current setting• Generation of voltage step through internal chopper• ‚rad hard‘ design• Nonlinearity < 0.4 LSB
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23 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Source measurements: self triggering
• Problem in source measurements:FE chip needs external trigger in true ATLAS mode
• One possibility:Use scintillator → additional detector, not suitablefor γ-sources
• Better solution:- use hitbus signal of the chip which signalizes a hit somewhere in the pixel matrix- Use this signal with correct delay as a trigger
• This is a ‚fair‘ measurement using the readout in fullATLAS mode
FE-Chipwith
Sensor
hitbus
DAQ andTriggerlogic
delay
L1
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24 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Source measurement with 55Fe
• 55Fe-source (6keV γ) deposits only1700 eh-pairs
• FE-C chip with thresholds tunedto ~1200e-
• Some bump problems at edge• The chip can be operated ata
very low threshold
0 2 4 6 8 10 12 14 160
20
40
60
80
100
120
140
Column
Row
600 µm long sensor pixels-> higher rate
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25 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Source measurement on a module with 241Am
• Spot of 241Am-source on two neighbouring chips of a module• Module without MCC: chips were illuminated one after the other
5 10 15 20 25 30 35
20
40
60
80
100
120
140
160chip #4 chip #5
column
row
Higher count rate in600 µm long pixels
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26 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Module performance (thresholds & noise)
• Module with 16 chips, here FEB
• Noise and ToT response arecomparable to single chips.
• Performance of several modules:
0
1000
2000
3000
4000
5000
6000
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
File : t1izm_tune3k Summary Plots
EntriesMeanRMSUDFLWOVFLW
24594 3028. 230.0
0. 54.00
211.4 / 50Constant 5684.Mean 3036.Sigma 170.7
Threshold / e-
Ent
ries
per
100
e- b
in
EntriesMeanRMSUDFLWOVFLW
24593 150.4 63.47
0. 148.0
2181. / 85Constant 4913.Mean 137.1Sigma 16.27
Noise / e-
Ent
ries
per
9e-
bin
0
1000
2000
3000
4000
5000
0 100 200 300 400 500 600 700 800 900
Moduletype
Front-end
Bump Threshold[e]
Noise[e]
Bare FEB IZM 2000 140Flex FEB IZM 2000 180Bare FEC IZM 2500 140Flex FEB IZM 3000 160Flex FEB Alenia 3600 180
b
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27 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Testbeam: charge collection studies using ToT• ToT gives information about collected charge• ToT analysis in testbeam was able to show differences in charge collection between
different sensor designs, e.g. two different p-spray sensors:
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28 Peter Fischer, Bonn UniversityPixel 2000, Genova, June 5-8, 2000
Summary and Outlook
• Non-rad hard ATLAS chips (FEs, MCC) are close to meet our goals.• Radiation hard designs of all chips have been produced by DMILL• Problems here are:
− Very low yield in first FED run.‚Strange‘ behaviour of chips not seen before with same architecture.
− Identical second ‚backup‘ run has much higher yield.− We need to understand what is going on.
• New FED2 design is finished.− Some small bugs are fixed, buffering of many digital signals improved.
• Full DMILL MCC-D2 will be ready soon• FEH will be submitted late summer 2000 to Honeywell.