pipelined fast fourier transform for low power ofdm … · pipelined fast fourier transform for low...

PIPELINED FAST FOURIER TRANSFORM FOR LOW POWER OFDM BASED APPLICATIONS

1K. Vijayakanthan,

2M.Anand,

3M.Janakirani

1Research Scholar, Dr.M.G.R Educational and Research Institute University, Chennai-95.

2,3Professor, Dr.M.G.R Educational and Research Institute University, Chennai-95.

Abstract: In this paper, an area-efficient low power fast

Fourier transform (FFT) processor is intended for Multi

Input Multi Output—Orthogonal Frequency Division

Multiplexing (MIMO-OFDM) that consists of a modified

architecture of radix-2 algorithm that is delineated as

Radix-2 multipath delay commutation (R2MDC).

Orthogonal frequency division multiplexing may be a

widespread methodology for high data rate wireless

transmission. OFDM is also united with multiple

antennas at all the access point and mobile workstation to

extend diversity gain and/or Enhance system capability

on a time-varying multi path attenuation channel, leading

to a multiple input multiple output OFDM system. This

paper describes the planning of R2MDC FFT for

implementation of MIMO OFDM transceiver

exploitation FPGA targeted to future wireless local area

network systems. The proposed system is pipeline radix

2multipath delay commutation FFT has been designed

for MIMO OFDM. The MIMO OFDM transceivers are

designed consistent with the proposed OFDM

parameters. A low-power economical and full pipeline

design allows the time period operations of MIMO

OFDM transceivers. The FPGA board has been

developed to verify their circuit behavior and

implementation of MIMO OFDM Transceivers.

Keywords: Radix-2 multipath delay commutation ·

Frequency division multiplexing · Multi input multi

output—orthogonal frequency division multiplexing ·

Inverse fast Fourier Transform · Fast Fourier Transform ·

Discrete Fourier Transform

1. Introduction

Multiple input multiple output–Orthogonal frequency

division multiplexing (MIMO-OFDM) has become a

promising technique for future mobile transmission

communication system due to its lustiness to frequency

selective attenuation and its flexibility in handling

multiple information rates [ 1, 2].

MIMO-OFDM is that the economical answer for

transmittal and receiving the info over the long distance.

The sub-carrier frequency has been chosen in our

projected OFDM transceivers so cross-talk between the

sub-channels are eliminated, therefore the inhume carrier

guard bands aren't needed. The orthogonally permits for

economical modulator and rectifier implementation

exploitation the FFT algorithmic program. OFDM

Transceivers is fashionable for band communications

these days by means of low-priced MIMO OFDM

Transceivers needs terribly correct frequency

synchronization between the receiver and that they have

their reduced the complexness In Transmitter; with

frequency deviation, the sub-carriers shall not be

orthogonal, inflicting inter-symbol interference (ISI). The

projected FFT Processor relies on radix-2 multipath delay

commutation. we tend to compare this projected design

with existing base two and base four FFT and conjointly

provide the planning and implementation results of the

projected FFF processor.

2. MIMO – OFDM

The general transceiver structure of MIMO OFDM is

presented in Fig. 1. The system consists of N transmitter

antennas and M receiver antennas. Multiple antennas at

either side of receiver and transmitter will improve the

spectral potency and reliableness in multipath weakening

channels [ 3– 5]. Consistent with [6], the cyclic prefix is

assumed to be an extended than the channel delay unfold.

The OFDM signal for every antenna is obtained by

exploitation IFFT and may be detected by fast Fourier

transform (FFT). Every OFDM block of constellation

symbols is remodeled exploitation an inverse fast Fourier

transform (IFFT) and transmitted by the antenna for its

corresponding stream. The received signals at every

antenna are equally broken into blocks and processed

exploitation an FFT. [7].

International Journal of Pure and Applied MathematicsVolume 116 No. 23 2017, 371-376ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version)url: http://www.ijpam.euSpecial Issue ijpam.eu

371

Figure 1. MIMO OFDM Architecture

Bolcskei et al have bestowed an OFDM based mostly

abstraction multiplexing theme, the information streams

are 1st more experienced OFDM modulators and so

launched from the individual antennas. Within the

receiver, the individual signals are more experienced

OFDM demodulators [8]. A strong improvement over

standard OFDM was the introductions of multi-carrier

code division multiplex (MC-CDM) OFDM by kaiser in

[9].

In MC-CDM, instead of sending one symbol on every

subcarrier as in standard OFDM, teams of symbols are

multiplexed along by suggests that of orthogonal

spreading codes and at the same time transmitted on a

gaggle of subcarriers [10].

OFDM could be a multi-carrier system wherever

information bits are encoded to multiple sub-carriers. in

contrast to single carrier systems, all the frequencies are

sent at the same time in time. OFDM offers many

benefits over single carrier system prefer multipath

impact immunity, easier channel equalization and relaxed

temporal arrangement acquisition constraints. However

it’s a lot of prone to native frequency offset and radio

front-end non-linearity. The frequencies utilized in

OFDM system are orthogonal. Neighboring frequencies

with overlapping spectrum will so be used. This property

is shown within the Fig. 2, where A, B, C, D, and E

orthogonal. This leads to economical usage of BW. The

OFDM is so ready to give higher rate for identical

Bandwidth [11].

3. Proposed Pipelined R2MDC

The radix-2 multipath delay commutation (R2MDC) is

one among the reversed architectures of radix-2 FFT

formula that is employed to reverse the values as quick as

potential so as to method the values and to commutate the

FFT inputs, the design shown within the Fig. one consists

of various blocks that should be utilized in the R2MDC.

Investigated Radix-2 pipelined streaming FFT block that

is employed within the baseline MIMO-OFDM system

[12]. However we have a tendency to use radix-2

multipath delay commutation within the proposed

system.

Figure 2. Waveform of OFDM

Figure 3. (a) Transmitter

Figure 3. (b) Receiver Proposed System

Figure 4. Radix-2 MDC Architecture

Figure 5. (a) BF-I and (b) BF- II

International Journal of Pure and Applied Mathematics Special Issue

372

One of the foremost simple approaches for pipelined

implementation of radix-2 FFT algorithm is Radix-2

Multi-path Delay electrical switch (R2MDC) design.

Figure four shows the radix-2 multipath delay

commutation design with butterfly II structure. it's the

best way to arrange information for the FFT/IFFT

algorithm, the input knowledge file sequence square

measure broken into 2 parallel data stream flowing

forward, with correct distance between information

components getting into the butterfly regular by proper

delays. The 8-point FFT in R2MDC design is shown in

Fig. 3. At every stage of this architecture half of the

information flow is delayed via the Register and

processed with the last half data stream.

The A input comes from the previous element twiddle

issue multipliers (TFM). The B output is fed to future

element, unremarkably BFII. In 1st cycles, multiplexors

direct the computer file to the feedback registers till

they're stuffed (position “0”). On next cycles, the

multiplexors choose the output of the adders/sub tractors

(position “1”), the butterfly computes a 2-point DFT with

incoming knowledge and also the knowledge keep within

the feedback registers. The elaborate structure of BFI is

shown in Fig.5a.

Figure 6. FPGA implementation of OFDM Transceiver

Figure 7. OFDM transceiver simulation wave form

The B input comes from the previous element, BFI.

The Z output is fed to subsequent element, usually TFM.

In 1st cycles, multiplexors direct the input file to the

feedback registers till they're crammed (position “0”). On

next cycles, the multiplexors choose the output of the

adders/sub tractors (position “1”), the butterfly computes

a 2-point DFT with incoming information and therefore

the information keep within the feedback registers. The

multiplication by –j involves real-imaginary swapping

and sign inversion. The real-imaginary swapping is

handled by the multiplexors MUX in expeditiously and

therefore the sign inversion is handled by change the

adding-subtracting operations by mean of MUX. once

there's a requirement for multiplication by -j, all

multiplexors switches to position “1”, the real-imaginary

information are swapped and therefore the adding-

subtracting operations ar switched.

The design of BFI and BFII supporting 2 receive

chains is shown in Fig. 5a, b. In BFI structure the sample

routing MUXs and DEMUXs at the input and output of

the BF_RAMs are management led supported c2 and c3

control signals while the computation unit is management

led by c1 control signal. The management signals are

issued by the BFI controller. Depending on the

programming of range of receive chains the additional

BF_RAMs are enabled. WiMAX supports 1Rx and 2Rx,

LTE supports 1Rx, 2Rx and 4Rx. supported the necessity

further buffers may be extended to the present BF

structure. The adders and subtractors in BFI and BFII are

fully-pipelined and followed by divide-by-2 and

misreckoning. The divide-by-2 is employed. The

algorithmic program used here is to turn the radix-2

algorithmic program within the IFFT design and to

interchange by R2MDC design so as to urge a low space

than the present system.

4. FPGA Implementation of MIMO OFDM

Transceiver

The applications like signal process and tele-

communication need FFT implementations which may

perform with less latency computations and little in size

whereas exhibiting less power consumption. These

process tasks are executed either by one, high frequency

embedded processor or by exploitation an Application

Specific integrated circuit (ASIC).

Figure 8. Output in the FPGA Spartan 3E


373

Field Programmable Gate Arrays (FPGAs) and

Application Specific Integrated Circuits (ASIC) give

completely different values to designers, and that they

should be rigorously evaluated before choosing anyone

over the opposite. FPGA has been recommended as an

sanctioning technology [13-15] for the hardware platform

as they provide the potential of hardware-like

performance coupled with software-like programmability

[14].

The register transfer Verilog internet list of the OFDM

Transceiver, that is optimized for low power

consumption and ASIC implementation, is employed as

basic internet list for mapping on a Xilinx FPGA as

shown in Fig six. The DCM installs a zero section delay

between the inner and external clock and this permits

employing a first in first out interface operational on the

clock edges to transfer transmit information and received

information. The FPGA implementation is optimized for

power consumption by disabling the most internal clock

once a purposeful unit isn't operational. This derived

clock is that the output of a buffered AND gate with the

most internal units.

Table 1. Comparison results of proposed R2mdc IFFT

architecture with existing radix-2 and radix-4 architecture

Methods Slices Luts Power (W)

R2MDC

FFT

186 146 1.065

Radix-2

FFT

308 412 2.125

Radix-4

FFT

280 140 2.252

This was the case within the equalizer wherever extra

pipeline registers are another within the divider and

within the information path of represented higher than,

delay between every butterfly board presently permits

base band transmission via ADCs and DACs as shown

Fig. 6.

The FPGA board uses transmitter, receiver, and

Viterbi decoder functions enforced within the Xilinx

FPGA. We tend to another interpolator, decimator,

random signal generator, and computer interface. The

interpolator and decimator need 100-MHz clock

frequency and also the alternative modules operate at the

clock speed. This FPGA with computer interface is

employed for displaying Bit Error Rate (BER) and Packet

Error Rate (PER) results and dominant the transceiver.

we tend to shall execute information transmission

experiments in each base band and pass band channels.

The simulation results for R2MDC FFT algorithms

are tested much by implementing within the Spartan 3E

FPGA development board. The Quartus-II tool is

employed to transfer the planning in to FPGA

development board within the FPGA board, the reset

signal input is connected to the right switch.

Figure 9. RTL schematic of R2MDC FFT

Figure 10. Comparison results of proposed R2MDC with

existing radix-2 and radix-4 architecture

For the set binary inputs at the remaining switches,

when the method within the FPGA, the outputs are seen

in light-emitting diode displays within the board. These

FPGA outputs also can be verified with simulation results

obtained exploitation MODELSIM. The FPGA board has

been developed to verify their circuit behavior and

implementation of MIMO OFDM Transceivers.

The below simulation diagram is for R2MDC as

shown in Fig. 7. The reset price is high and when it slow

amount the worth is low whereas in reset is high the input

value doesn't taken into the method. The output value is

occurred once the reset is low. FPGA Spartan 3E

development board to illustrate the implementation of

R2MDC FFT is as shown in Fig. 8. The register Transfer

Logic schematic for R2MDC FFT that's targeted to

mapped on FPGA Spartan 3E is shown in Fig. 9.

5. Results


374

The prime objective is to construct a FFT so as to possess

low power consumption and lesser space. The parameters

power consumption and space occupancy got due

consideration for comparison the planned FFT with

different FFTs. we've designed all writing victimisation

Hardware Description Language (HDL). to induce

power, and space report, we tend to use Xilinx ISE

design Suite 10.1 as synthesis tool and Model Sim 6.3c

for simulation. The comparison of Radix-2 FFT and

Radix-4 with planned R2MDC FFT is shown within the

Table 1and Fig. 10.The planned FFT offers higher result

than Radix-2 FFT and Radix-4 FFT in terms of space and

power consumption as shown within the Table1 and Fig.

10.

6. Conclusion

We given a R2MDC pipeline FFT as MIMO OFDM sys-

tem with a 100-MHz bandwidth, that is an area-efficient

low power FFT processor for MIMO-OFDM transceivers

implementation exploitation FPGA. The transceiver uses

full-pipelined process and provides operations at

minimum clock frequency. The performance of assorted

FFT like Radix-2, Radix-4 and planned R2MDC were

meted out and their performance were analyzed with

relation to the amount of CLB slices, LUTs and Power

consumption. we tend to demonstrated transceiver design

appropriate for the advanced OFDM system. in this

paper, we tend to conclude that the projected R2MDC

design offers a lower space and fewer power than the

present radix-2 and radix-4 rule design. The proposed

design shows that it may be used for low power

applications like MIMO-OFDM transceiver.

References

[1] Sampath, H., Talwar, S., Tellado, J., Erceg, V., &

Paulraj, A. (2002). A fourth generation MIMO-OFDM

broadband wireless system: design performance, and

field trial results. IEEE Communications Magazine,

40(9), 143–149.

[2] Zelst, A., & Schenk, T. (2004). Implementation of a

MIMO OFDM-based wireless LAN system. IEEE

Transactions on Sig- nal Processing, 52(2), 483–494.

[3] Heath, R, Jr, & Paulraj, A. (2005). Switching

between diversity and multiplexing in MIMO systems.

IEEE Transactions on Communi- cations, 53(6), 962–

968.

[4] Forenza, A., Pandharipande, A., Kim, H., & Heath,

R. W, Jr. (2005). Adaptive MIMO transmission scheme:

exploiting the spatial selec-tivity of wireless channels. In:

Proceedings of the IEEE VTC-spring (Vol. 5, pp. 3188–

3192).

[5] Wei, Y. R., & Wang, M. Z. (2006). A practical

transmit antenna selection scheme with adaptive

modulation for spatial multiplexing MIMO systems. In

IEEE intl. conf. on inf. & commun. tech., ICTTA’06,

April 2006 Syria. IEEE Transactions on Information

Theory, 2, 2119–2124.

[6] Kirubanandasarathy, N., Karthikeyan, K. &

Thirunadanasikamani, K. (2010). VLSI design of mixed

radix FFT for MIMO OFDM in the wireless

communication. In: Proceedings of the IEEE

International conference on communication computing

control technologies (pp. 98–102), October 7–9, 2010,

Ramanathapuram, India.

[7] Blum, R. S., Li, Y. G., Winters, J. H., & Yan, Q.

(2001). Improved space time coding for MIMO-OFDM

wireless communications. IEEE Transactions on

Communications, 49(11), 1873–1878.

[8] Bolcskei, H., Gesbert, D., & Paulraj, A. J. (2002).

On the capacity of OFDM-based spatial multiplexing

systems. IEEE Transactions on Communication, 50(2),

225–234.

[9] Kaiser, S. (2002). OFDM code-division

multiplexing in fading channels. IEEE Transactions on

Communication, 50, 1266–1273.

[10] Femenias, Guilleum, & Riera-Palou, Felip. (2008).

Enhancing IEEE 802.11n WLANs using group-

orthogonal code-division multiplex.

Telecommunication Systems (TSMJ), 38(1–2), 37.

[11] Kirubanandasarathy, N., & Karthikeyan, K. (2013).

VLSI Design of Pipelined R2MDC FFT for MIMO

OFDM transceivers. Journal of Applied Sciences (JAS),

Science Alert Publications, 13(1), 197– 200.

[12] Kirubanandasarathy, N. & Karthikeyan, K. (2012).

VLSI Design and Implementation of MIMO OFDM

system for wireless communication. European Journal

of Scientific Research (EJSR), ISSN 1450-216X, 73(2),

269–277.

[13] Tuttlbee, W.H. Software defined radio: Enabling

technologies. Wiley. ISBN 0470843187.

[14] Coulton, P. & Carline, D. (2004). An SDR inspired

design for the FPGA implementation of 802.11a

baseband system. In Proceed- ings of the IEEE

international symposium on consumer electronics (pp.

470–475), September 1–3, Reading, UK.

[15] Liu. L., Ren. J., et al.: ‘Design of low-power, 1GS/s

throughput FFT processor for MIMO-OFDM UWB

communication systems’, Proc. IEEE Int. Symp. Circuits

Syst., May 2007, pp. 2594-2597

[16] T.Padmapriya, Ms. N. Dhivya, Ms U.

Udhayamathi, “Minimizing Communication Cost In

Wireless Sensor Networks To Avoid Packet

Retransmission”,International Innovative Research

Journal of Engineering and Technology, Vol. 2,

Special Issue, pp. 38-42.


375

pipelined fast fourier transform for low power ofdm … · pipelined fast fourier transform for low...

Documents