pin information for the cyclone v e 5ceba4 device · configuration function: dedicated tx/rx...

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PT-5CEBA4-1.1 Copyright © 2012 Altera Corp. Pin List U15 Page 1 of 26 Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel U324 DQS for X8 2A VREFB2AN0 IO DIFFIO_TX_L9n DIFFOUT_L9n E2 2A VREFB2AN0 IO DIFFIO_RX_L10n DIFFOUT_L10n J4 DQ1L 2A VREFB2AN0 IO DIFFIO_TX_L9p DIFFOUT_L9p D1 DQ1L 2A VREFB2AN0 IO DIFFIO_RX_L10p DIFFOUT_L10p J3 DQ1L 2A VREFB2AN0 IO DIFFIO_RX_L11n DIFFOUT_L11n K2 DQSn1L 2A VREFB2AN0 IO DIFFIO_TX_L12n DIFFOUT_L12n E3 DQ1L 2A VREFB2AN0 IO DIFFIO_RX_L11p DIFFOUT_L11p K3 DQS1L 2A VREFB2AN0 IO DIFFIO_TX_L12p DIFFOUT_L12p F2 2A VREFB2AN0 IO DIFFIO_TX_L13n DIFFOUT_L13n E1 DQ1L 2A VREFB2AN0 IO DIFFIO_RX_L14n DIFFOUT_L14n F4 DQ1L 2A VREFB2AN0 IO DIFFIO_TX_L13p DIFFOUT_L13p F1 DQ1L 2A VREFB2AN0 IO DIFFIO_RX_L14p DIFFOUT_L14p G3 DQ1L 2A VREFB2AN0 IO DIFFIO_RX_L15n DIFFOUT_L15n K1 2A VREFB2AN0 IO DIFFIO_TX_L16n DIFFOUT_L16n H2 DQ1L 2A VREFB2AN0 IO DIFFIO_RX_L15p DIFFOUT_L15p L1 2A VREFB2AN0 IO DIFFIO_TX_L16p DIFFOUT_L16p G2 DQ1L 2A VREFB2AN0 IO DIFFIO_TX_L17n DIFFOUT_L17n J1 2A VREFB2AN0 IO DIFFIO_RX_L18n DIFFOUT_L18n L2 DQ2L 2A VREFB2AN0 IO DIFFIO_TX_L17p DIFFOUT_L17p H1 DQ2L 2A VREFB2AN0 IO DIFFIO_RX_L18p DIFFOUT_L18p M2 DQ2L 2A VREFB2AN0 IO DIFFIO_RX_L19n DIFFOUT_L19n L5 DQSn2L 2A VREFB2AN0 IO DIFFIO_TX_L20n DIFFOUT_L20n R1 DQ2L 2A VREFB2AN0 IO DIFFIO_RX_L19p DIFFOUT_L19p M4 DQS2L 2A VREFB2AN0 IO DIFFIO_TX_L20p DIFFOUT_L20p P1 2A VREFB2AN0 IO DIFFIO_TX_L21n DIFFOUT_L21n R2 DQ2L 2A VREFB2AN0 IO DIFFIO_RX_L22n DIFFOUT_L22n N2 DQ2L 2A VREFB2AN0 IO DIFFIO_TX_L21p DIFFOUT_L21p T1 DQ2L 2A VREFB2AN0 IO DIFFIO_RX_L22p DIFFOUT_L22p N3 DQ2L 2A VREFB2AN0 IO DIFFIO_RX_L23n DIFFOUT_L23n L4 2A VREFB2AN0 IO DIFFIO_TX_L24n DIFFOUT_L24n T2 DQ2L 2A VREFB2AN0 IO DIFFIO_RX_L23p DIFFOUT_L23p M3 2A VREFB2AN0 IO DIFFIO_TX_L24p DIFFOUT_L24p R3 DQ2L 3A TDO TDO P5 3A nCSO DATA4 P3 3A TMS TMS P6 3A AS_DATA3 DATA3 M5 3A TCK TCK L6 3A AS_DATA2 DATA2 U3 3A TDI TDI N6 3A AS_DATA1 DATA1 U2 3A DCLK DCLK K6 3A AS_DATA0,ASDO DATA0 V1 3A VREFB3AN0 IO DATA6 DIFFIO_RX_B1n DIFFOUT_B1n M7 DQ1B 3A VREFB3AN0 IO DATA5 DIFFIO_TX_B2n DIFFOUT_B2n V2 3A VREFB3AN0 IO DATA8 DIFFIO_RX_B1p DIFFOUT_B1p N7 DQ1B 3A VREFB3AN0 IO DATA7 DIFFIO_TX_B2p DIFFOUT_B2p V3 DQ1B 3A VREFB3AN0 IO DATA10 DIFFIO_RX_B3n DIFFOUT_B3n M10 DQSn1B 3A VREFB3AN0 IO DATA9 DIFFIO_TX_B4n DIFFOUT_B4n U7 DQ1B 3A VREFB3AN0 IO DATA12 DIFFIO_RX_B3p DIFFOUT_B3p N10 DQS1B 3A VREFB3AN0 IO DATA11 DIFFIO_TX_B4p DIFFOUT_B4p T7 3A VREFB3AN0 IO DATA14 DIFFIO_RX_B5n DIFFOUT_B5n M8 DQ1B 3A VREFB3AN0 IO DATA13 DIFFIO_TX_B6n DIFFOUT_B6n P4 DQ1B 3A VREFB3AN0 IO CLKUSR DIFFIO_RX_B5p DIFFOUT_B5p M9 DQ1B 3A VREFB3AN0 IO DATA15 DIFFIO_TX_B6p DIFFOUT_B6p R4 DQ1B 3A VREFB3AN0 IO PR_DONE DIFFIO_RX_B7n DIFFOUT_B7n N11 3A VREFB3AN0 IO PR_READY DIFFIO_TX_B8n DIFFOUT_B8n P8 DQ1B Pin Information for the Cyclone ® V 5CEBA4 Device Version 1.1 Note (1)

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PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U15 Page 1 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U324 DQS for X8

2A VREFB2AN0 IO DIFFIO_TX_L9n DIFFOUT_L9n E22A VREFB2AN0 IO DIFFIO_RX_L10n DIFFOUT_L10n J4 DQ1L2A VREFB2AN0 IO DIFFIO_TX_L9p DIFFOUT_L9p D1 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L10p DIFFOUT_L10p J3 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L11n DIFFOUT_L11n K2 DQSn1L2A VREFB2AN0 IO DIFFIO_TX_L12n DIFFOUT_L12n E3 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L11p DIFFOUT_L11p K3 DQS1L2A VREFB2AN0 IO DIFFIO_TX_L12p DIFFOUT_L12p F22A VREFB2AN0 IO DIFFIO_TX_L13n DIFFOUT_L13n E1 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L14n DIFFOUT_L14n F4 DQ1L2A VREFB2AN0 IO DIFFIO_TX_L13p DIFFOUT_L13p F1 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L14p DIFFOUT_L14p G3 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L15n DIFFOUT_L15n K12A VREFB2AN0 IO DIFFIO_TX_L16n DIFFOUT_L16n H2 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L15p DIFFOUT_L15p L12A VREFB2AN0 IO DIFFIO_TX_L16p DIFFOUT_L16p G2 DQ1L2A VREFB2AN0 IO DIFFIO_TX_L17n DIFFOUT_L17n J12A VREFB2AN0 IO DIFFIO_RX_L18n DIFFOUT_L18n L2 DQ2L2A VREFB2AN0 IO DIFFIO_TX_L17p DIFFOUT_L17p H1 DQ2L2A VREFB2AN0 IO DIFFIO_RX_L18p DIFFOUT_L18p M2 DQ2L2A VREFB2AN0 IO DIFFIO_RX_L19n DIFFOUT_L19n L5 DQSn2L2A VREFB2AN0 IO DIFFIO_TX_L20n DIFFOUT_L20n R1 DQ2L2A VREFB2AN0 IO DIFFIO_RX_L19p DIFFOUT_L19p M4 DQS2L2A VREFB2AN0 IO DIFFIO_TX_L20p DIFFOUT_L20p P12A VREFB2AN0 IO DIFFIO_TX_L21n DIFFOUT_L21n R2 DQ2L2A VREFB2AN0 IO DIFFIO_RX_L22n DIFFOUT_L22n N2 DQ2L2A VREFB2AN0 IO DIFFIO_TX_L21p DIFFOUT_L21p T1 DQ2L2A VREFB2AN0 IO DIFFIO_RX_L22p DIFFOUT_L22p N3 DQ2L2A VREFB2AN0 IO DIFFIO_RX_L23n DIFFOUT_L23n L42A VREFB2AN0 IO DIFFIO_TX_L24n DIFFOUT_L24n T2 DQ2L2A VREFB2AN0 IO DIFFIO_RX_L23p DIFFOUT_L23p M32A VREFB2AN0 IO DIFFIO_TX_L24p DIFFOUT_L24p R3 DQ2L3A TDO TDO P53A nCSO DATA4 P33A TMS TMS P63A AS_DATA3 DATA3 M53A TCK TCK L63A AS_DATA2 DATA2 U33A TDI TDI N63A AS_DATA1 DATA1 U23A DCLK DCLK K63A AS_DATA0,ASDO DATA0 V13A VREFB3AN0 IO DATA6 DIFFIO_RX_B1n DIFFOUT_B1n M7 DQ1B3A VREFB3AN0 IO DATA5 DIFFIO_TX_B2n DIFFOUT_B2n V23A VREFB3AN0 IO DATA8 DIFFIO_RX_B1p DIFFOUT_B1p N7 DQ1B3A VREFB3AN0 IO DATA7 DIFFIO_TX_B2p DIFFOUT_B2p V3 DQ1B3A VREFB3AN0 IO DATA10 DIFFIO_RX_B3n DIFFOUT_B3n M10 DQSn1B3A VREFB3AN0 IO DATA9 DIFFIO_TX_B4n DIFFOUT_B4n U7 DQ1B3A VREFB3AN0 IO DATA12 DIFFIO_RX_B3p DIFFOUT_B3p N10 DQS1B3A VREFB3AN0 IO DATA11 DIFFIO_TX_B4p DIFFOUT_B4p T73A VREFB3AN0 IO DATA14 DIFFIO_RX_B5n DIFFOUT_B5n M8 DQ1B3A VREFB3AN0 IO DATA13 DIFFIO_TX_B6n DIFFOUT_B6n P4 DQ1B3A VREFB3AN0 IO CLKUSR DIFFIO_RX_B5p DIFFOUT_B5p M9 DQ1B3A VREFB3AN0 IO DATA15 DIFFIO_TX_B6p DIFFOUT_B6p R4 DQ1B3A VREFB3AN0 IO PR_DONE DIFFIO_RX_B7n DIFFOUT_B7n N113A VREFB3AN0 IO PR_READY DIFFIO_TX_B8n DIFFOUT_B8n P8 DQ1B

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U15 Page 2 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U324 DQS for X8

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

3A VREFB3AN0 IO PR_ERROR DIFFIO_RX_B7p DIFFOUT_B7p P113A VREFB3AN0 IO DIFFIO_TX_B8p DIFFOUT_B8p N8 DQ1B3B VREFB3BN0 IO DIFFIO_TX_B17n DIFFOUT_B17n V63B VREFB3BN0 IO DIFFIO_RX_B18n DIFFOUT_B18n U5 DQ2B3B VREFB3BN0 IO DIFFIO_TX_B17p DIFFOUT_B17p V7 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B18p DIFFOUT_B18p U4 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B19n DIFFOUT_B19n P9 DQSn2B3B VREFB3BN0 IO DIFFIO_TX_B20n DIFFOUT_B20n T4 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B19p DIFFOUT_B19p P10 DQS2B3B VREFB3BN0 IO DIFFIO_TX_B20p DIFFOUT_B20p T53B VREFB3BN0 IO FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn DIFFIO_TX_B21n DIFFOUT_B21n V8 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B22n DIFFOUT_B22n T9 DQ2B3B VREFB3BN0 IO FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB DIFFIO_TX_B21p DIFFOUT_B21p U8 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B22p DIFFOUT_B22p R9 DQ2B3B VREFB3BN0 IO CLK1n DIFFIO_RX_B23n DIFFOUT_B23n T113B VREFB3BN0 IO DIFFIO_TX_B24n DIFFOUT_B24n U9 DQ2B3B VREFB3BN0 IO CLK1p DIFFIO_RX_B23p DIFFOUT_B23p R113B VREFB3BN0 IO DIFFIO_TX_B24p DIFFOUT_B24p V10 DQ2B4A VREFB4AN0 IO RZQ_0 DIFFIO_TX_B25n DIFFOUT_B25n U134A VREFB4AN0 IO DIFFIO_RX_B26n DIFFOUT_B26n V13 DQ3B4A VREFB4AN0 IO DIFFIO_TX_B25p DIFFOUT_B25p U14 DQ3B4A VREFB4AN0 IO DIFFIO_RX_B26p DIFFOUT_B26p V12 DQ3B4A VREFB4AN0 IO DIFFIO_RX_B27n DIFFOUT_B27n M14 DQSn3B4A VREFB4AN0 IO DIFFIO_TX_B28n DIFFOUT_B28n U18 DQ3B4A VREFB4AN0 IO DIFFIO_RX_B27p DIFFOUT_B27p L13 DQS3B4A VREFB4AN0 IO DIFFIO_TX_B28p DIFFOUT_B28p V174A VREFB4AN0 IO DIFFIO_TX_B29n DIFFOUT_B29n U17 DQ3B4A VREFB4AN0 IO DIFFIO_RX_B30n DIFFOUT_B30n V16 DQ3B4A VREFB4AN0 IO DIFFIO_TX_B29p DIFFOUT_B29p T17 DQ3B4A VREFB4AN0 IO DIFFIO_RX_B30p DIFFOUT_B30p V15 DQ3B4A VREFB4AN0 IO CLK2n DIFFIO_RX_B31n DIFFOUT_B31n U124A VREFB4AN0 IO DIFFIO_TX_B32n DIFFOUT_B32n R18 DQ3B4A VREFB4AN0 IO CLK2p DIFFIO_RX_B31p DIFFOUT_B31p T124A VREFB4AN0 IO DIFFIO_TX_B32p DIFFOUT_B32p P18 DQ3B4A VREFB4AN0 IO DIFFIO_TX_B33n DIFFOUT_B33n T164A VREFB4AN0 IO DIFFIO_RX_B34n DIFFOUT_B34n P14 DQ4B4A VREFB4AN0 IO DIFFIO_TX_B33p DIFFOUT_B33p R17 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B34p DIFFOUT_B34p P15 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B35n DIFFOUT_B35n M13 DQSn4B4A VREFB4AN0 IO DIFFIO_TX_B36n DIFFOUT_B36n R16 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B35p DIFFOUT_B35p N12 DQS4B4A VREFB4AN0 IO DIFFIO_TX_B36p DIFFOUT_B36p P164A VREFB4AN0 IO DIFFIO_TX_B37n DIFFOUT_B37n N17 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B38n DIFFOUT_B38n R13 DQ4B4A VREFB4AN0 IO DIFFIO_TX_B37p DIFFOUT_B37p N16 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B38p DIFFOUT_B38p T14 DQ4B4A VREFB4AN0 IO CLK3n DIFFIO_RX_B39n DIFFOUT_B39n N134A VREFB4AN0 IO DIFFIO_TX_B40n DIFFOUT_B40n U15 DQ4B4A VREFB4AN0 IO CLK3p DIFFIO_RX_B39p DIFFOUT_B39p P134A VREFB4AN0 IO DIFFIO_TX_B40p DIFFOUT_B40p T15 DQ4B5A VREFB5AN0 IO RZQ_1 DIFFIO_TX_R1p DIFFOUT_R1p L16 DQ1R5A VREFB5AN0 IO INIT_DONE DIFFIO_RX_R2p DIFFOUT_R2p L145A VREFB5AN0 IO PR_REQUEST DIFFIO_TX_R1n DIFFOUT_R1n L15 DQ1R5A VREFB5AN0 IO CRC_ERROR DIFFIO_RX_R2n DIFFOUT_R2n K135A VREFB5AN0 IO nCEO DIFFIO_TX_R3p DIFFOUT_R3p M18 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R4p DIFFOUT_R4p J13 DQ1R

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U15 Page 3 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U324 DQS for X8

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

5A VREFB5AN0 IO CvP_CONFDONE DIFFIO_TX_R3n DIFFOUT_R3n N18 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R4n DIFFOUT_R4n J14 DQ1R5A VREFB5AN0 IO DEV_OE DIFFIO_TX_R5p DIFFOUT_R5p K175A VREFB5AN0 IO DIFFIO_RX_R6p DIFFOUT_R6p G13 DQS1R5A VREFB5AN0 IO DEV_CLRn DIFFIO_TX_R5n DIFFOUT_R5n K16 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R6n DIFFOUT_R6n H13 DQSn1R5A VREFB5AN0 IO DIFFIO_TX_R7p DIFFOUT_R7p L17 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R8p DIFFOUT_R8p J16 DQ1R5A VREFB5AN0 IO DIFFIO_TX_R7n DIFFOUT_R7n K185A VREFB5AN0 IO DIFFIO_RX_R8n DIFFOUT_R8n J15 DQ1R5B VREFB5BN0 IO CLK6p DIFFIO_RX_R9p DIFFOUT_R9p F145B VREFB5BN0 IO DIFFIO_TX_R10p DIFFOUT_R10p H17 DQ2R5B VREFB5BN0 IO CLK6n DIFFIO_RX_R9n DIFFOUT_R9n G145B VREFB5BN0 IO DIFFIO_TX_R10n DIFFOUT_R10n G17 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R11p DIFFOUT_R11p G15 DQ2R5B VREFB5BN0 IO FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB DIFFIO_TX_R12p DIFFOUT_R12p J18 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R11n DIFFOUT_R11n H16 DQ2R5B VREFB5BN0 IO FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn DIFFIO_TX_R12n DIFFOUT_R12n H18 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R13p DIFFOUT_R13p E16 DQS2R5B VREFB5BN0 IO DIFFIO_TX_R14p DIFFOUT_R14p E185B VREFB5BN0 IO DIFFIO_RX_R13n DIFFOUT_R13n F16 DQSn2R5B VREFB5BN0 IO DIFFIO_TX_R14n DIFFOUT_R14n D18 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R15p DIFFOUT_R15p G18 DQ2R5B VREFB5BN0 IO DIFFIO_TX_R16p DIFFOUT_R16p C18 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R15n DIFFOUT_R15n F17 DQ2R5B VREFB5BN0 IO DIFFIO_TX_R16n DIFFOUT_R16n C177A GND D157A VREFB7AN0 IO CLK11p DIFFIO_RX_T9p DIFFOUT_T9p F127A VREFB7AN0 IO DIFFIO_TX_T10p DIFFOUT_T10p D16 DQ1T7A VREFB7AN0 IO CLK11n DIFFIO_RX_T9n DIFFOUT_T9n F117A VREFB7AN0 IO DIFFIO_TX_T10n DIFFOUT_T10n C16 DQ1T7A VREFB7AN0 IO DIFFIO_RX_T11p DIFFOUT_T11p C13 DQ1T7A VREFB7AN0 IO DIFFIO_TX_T12p DIFFOUT_T12p B14 DQ1T7A VREFB7AN0 IO DIFFIO_RX_T11n DIFFOUT_T11n C12 DQ1T7A VREFB7AN0 IO DIFFIO_TX_T12n DIFFOUT_T12n B15 DQ1T7A VREFB7AN0 IO DIFFIO_RX_T13p DIFFOUT_T13p E12 DQS1T7A VREFB7AN0 IO DIFFIO_TX_T14p DIFFOUT_T14p B177A VREFB7AN0 IO DIFFIO_RX_T13n DIFFOUT_T13n E11 DQSn1T7A VREFB7AN0 IO DIFFIO_TX_T14n DIFFOUT_T14n B18 DQ1T7A VREFB7AN0 IO DIFFIO_RX_T15p DIFFOUT_T15p D13 DQ1T7A VREFB7AN0 IO DIFFIO_TX_T16p DIFFOUT_T16p A16 DQ1T7A VREFB7AN0 IO DIFFIO_RX_T15n DIFFOUT_T15n E14 DQ1T7A VREFB7AN0 IO DIFFIO_TX_T16n DIFFOUT_T16n A177A VREFB7AN0 IO CLK10p DIFFIO_RX_T17p DIFFOUT_T17p F97A VREFB7AN0 IO DIFFIO_TX_T18p DIFFOUT_T18p A14 DQ2T7A VREFB7AN0 IO CLK10n DIFFIO_RX_T17n DIFFOUT_T17n F107A VREFB7AN0 IO DIFFIO_TX_T18n DIFFOUT_T18n A15 DQ2T7A VREFB7AN0 IO DIFFIO_RX_T19p DIFFOUT_T19p C11 DQ2T7A VREFB7AN0 IO DIFFIO_TX_T20p DIFFOUT_T20p A12 DQ2T7A VREFB7AN0 IO DIFFIO_RX_T19n DIFFOUT_T19n B10 DQ2T7A VREFB7AN0 IO DIFFIO_TX_T20n DIFFOUT_T20n B12 DQ2T7A VREFB7AN0 IO DIFFIO_RX_T21p DIFFOUT_T21p D9 DQS2T7A VREFB7AN0 IO DIFFIO_TX_T22p DIFFOUT_T22p A117A VREFB7AN0 IO DIFFIO_RX_T21n DIFFOUT_T21n E9 DQSn2T7A VREFB7AN0 IO DIFFIO_TX_T22n DIFFOUT_T22n A10 DQ2T7A VREFB7AN0 IO DIFFIO_RX_T23p DIFFOUT_T23p D11 DQ2T

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U15 Page 4 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U324 DQS for X8

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

7A VREFB7AN0 IO DIFFIO_TX_T24p DIFFOUT_T24p A9 DQ2T7A VREFB7AN0 IO DIFFIO_RX_T23n DIFFOUT_T23n D10 DQ2T7A VREFB7AN0 IO RZQ_2 DIFFIO_TX_T24n DIFFOUT_T24n B98A VREFB8AN0 IO CLK9p DIFFIO_RX_T25p DIFFOUT_T25p G68A VREFB8AN0 IO DIFFIO_TX_T26p DIFFOUT_T26p A7 DQ3T8A VREFB8AN0 IO CLK9n DIFFIO_RX_T25n DIFFOUT_T25n F68A VREFB8AN0 IO DIFFIO_TX_T26n DIFFOUT_T26n A6 DQ3T8A VREFB8AN0 IO DIFFIO_RX_T27p DIFFOUT_T27p B7 DQ3T8A VREFB8AN0 IO FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB DIFFIO_TX_T28p DIFFOUT_T28p A4 DQ3T8A VREFB8AN0 IO DIFFIO_RX_T27n DIFFOUT_T27n B8 DQ3T8A VREFB8AN0 IO FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn DIFFIO_TX_T28n DIFFOUT_T28n A5 DQ3T8A VREFB8AN0 IO DIFFIO_RX_T29p DIFFOUT_T29p E8 DQS3T8A VREFB8AN0 IO DIFFIO_TX_T30p DIFFOUT_T30p C18A VREFB8AN0 IO DIFFIO_RX_T29n DIFFOUT_T29n F7 DQSn3T8A VREFB8AN0 IO DIFFIO_TX_T30n DIFFOUT_T30n C2 DQ3T8A VREFB8AN0 IO DIFFIO_RX_T31p DIFFOUT_T31p B4 DQ3T8A VREFB8AN0 IO DIFFIO_TX_T32p DIFFOUT_T32p B3 DQ3T8A VREFB8AN0 IO DIFFIO_RX_T31n DIFFOUT_T31n B5 DQ3T8A VREFB8AN0 IO DIFFIO_TX_T32n DIFFOUT_T32n C39A MSEL0 MSEL0 J69A CONF_DONE CONF_DONE C69A MSEL1 MSEL1 H59A nSTATUS nSTATUS D69A nCE nCE E49A MSEL2 MSEL2 D39A MSEL3 MSEL3 G59A nCONFIG nCONFIG D49A MSEL4 MSEL4 G49A GND D5

GND D12GND V18GND V14GND V4GND U1GND T13GND T3GND R10GND P17GND P12GND P7GND N14GND N9GND N4GND M12GND M6GND M1GND L18GND L11GND L9GND L7GND K12GND K10GND K8GND K5GND J17GND J11

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U15 Page 5 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U324 DQS for X8

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

GND J9GND J7GND H14GND H12GND H10GND H8GND H6GND G11GND G9GND G7GND G1GND F13GND F8GND F3GND E10GND E5GND D17GND D7GND D2GND C4GND B11GND B1GND A18GND A8GND A3VCC M11VCC L12VCC L10VCC L8VCC K11VCC K9VCC K7VCC J12VCC J10VCC J8VCC H11VCC H9VCC H7VCC G12VCC G10VCC G8DNU A2DNU B2DNU C15DNU C8VCCPGM T6VCCPGM M15VCCPGM E7VCCBAT C5VCCIO2A H4VCCIO2A P2VCCIO2A L3VCCIO2A J2VCCIO3A R5VCCIO3A U6VCCIO3B T8

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U15 Page 6 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U324 DQS for X8

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

VCCIO3B V9VCCIO4A T18VCCIO4A U16VCCIO4A U11VCCIO4A R15VCCIO5A K15VCCIO5A M16VCCIO5B F18VCCIO5B G16VCCIO7A B16VCCIO7A E15VCCIO7A C14VCCIO7A A13VCCIO8A C9VCCIO8A B6VCCPD1A2A K4VCCPD1A2A J5VCCPD3A R7VCCPD3B4A R12VCCPD3B4A R8VCCPD5A K14VCCPD5B H15VCCPD7A8A D8VCCPD7A8A E13

2A VREFB2AN0 VREFB2AN0 N13A VREFB3AN0 VREFB3AN0 V53B VREFB3BN0 VREFB3BN0 U104A VREFB4AN0 VREFB4AN0 V115A VREFB5AN0 VREFB5AN0 M175B VREFB5BN0 VREFB5BN0 E177A VREFB7AN0 VREFB7AN0 B138A VREFB8AN0 VREFB8AN0 C7

RREF_TL A1VCCA_FPLL H3VCCA_FPLL N5VCCA_FPLL F5VCCA_FPLL N15VCCA_FPLL F15VCC_AUX E6VCC_AUX C10VCC_AUX D14VCC_AUX R14VCC_AUX T10VCC_AUX R6

Note:(1) For more information about pin definition and pin connection guidelines, refer to theCyclone V Device Family Pin Connection Guidelines.

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U19 Page 7 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U484 DQS for X8 DQS for X16

2A VREFB2AN0 IO DIFFIO_TX_L9n DIFFOUT_L9n C12A VREFB2AN0 IO DIFFIO_RX_L10n DIFFOUT_L10n L1 DQ1L2A VREFB2AN0 IO DIFFIO_TX_L9p DIFFOUT_L9p C2 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L10p DIFFOUT_L10p L2 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L11n DIFFOUT_L11n N1 DQSn1L2A VREFB2AN0 IO DIFFIO_TX_L12n DIFFOUT_L12n E2 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L11p DIFFOUT_L11p N2 DQS1L2A VREFB2AN0 IO DIFFIO_TX_L12p DIFFOUT_L12p D32A VREFB2AN0 IO DIFFIO_TX_L13n DIFFOUT_L13n G1 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L14n DIFFOUT_L14n U1 DQ1L2A VREFB2AN0 IO DIFFIO_TX_L13p DIFFOUT_L13p G2 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L14p DIFFOUT_L14p U2 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L15n DIFFOUT_L15n W22A VREFB2AN0 IO DIFFIO_TX_L16n DIFFOUT_L16n AA1 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L15p DIFFOUT_L15p Y32A VREFB2AN0 IO DIFFIO_TX_L16p DIFFOUT_L16p AA2 DQ1L3A TDO TDO V33A nCSO DATA4 AB63A TMS TMS R43A AS_DATA3 DATA3 AA53A TCK TCK V53A AS_DATA2 DATA2 T53A TDI TDI P53A AS_DATA1 DATA1 W53A DCLK DCLK M53A AS_DATA0,ASDO DATA0 AB43A VREFB3AN0 IO DATA6 DIFFIO_RX_B1n DIFFOUT_B1n P6 DQ1B3A VREFB3AN0 IO DATA5 DIFFIO_TX_B2n DIFFOUT_B2n U73A VREFB3AN0 IO DATA8 DIFFIO_RX_B1p DIFFOUT_B1p N6 DQ1B3A VREFB3AN0 IO DATA7 DIFFIO_TX_B2p DIFFOUT_B2p U6 DQ1B3A VREFB3AN0 IO DATA10 DIFFIO_RX_B3n DIFFOUT_B3n M6 DQSn1B3A VREFB3AN0 IO DATA9 DIFFIO_TX_B4n DIFFOUT_B4n R5 DQ1B3A VREFB3AN0 IO DATA12 DIFFIO_RX_B3p DIFFOUT_B3p M7 DQS1B3A VREFB3AN0 IO DATA11 DIFFIO_TX_B4p DIFFOUT_B4p R63A VREFB3AN0 IO DATA14 DIFFIO_RX_B5n DIFFOUT_B5n R7 DQ1B3A VREFB3AN0 IO DATA13 DIFFIO_TX_B6n DIFFOUT_B6n L7 DQ1B3A VREFB3AN0 IO CLKUSR DIFFIO_RX_B5p DIFFOUT_B5p T7 DQ1B3A VREFB3AN0 IO DATA15 DIFFIO_TX_B6p DIFFOUT_B6p L8 DQ1B3A VREFB3AN0 IO PR_DONE DIFFIO_RX_B7n DIFFOUT_B7n T83A VREFB3AN0 IO PR_READY DIFFIO_TX_B8n DIFFOUT_B8n P7 DQ1B3A VREFB3AN0 IO PR_ERROR DIFFIO_RX_B7p DIFFOUT_B7p T93A VREFB3AN0 IO DIFFIO_TX_B8p DIFFOUT_B8p P8 DQ1B3B VREFB3BN0 IO DIFFIO_TX_B9n DIFFOUT_B9n V83B VREFB3BN0 IO DIFFIO_RX_B10n DIFFOUT_B10n N8 DQ2B3B VREFB3BN0 IO DIFFIO_TX_B9p DIFFOUT_B9p W8 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B10p DIFFOUT_B10p M8 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B11n DIFFOUT_B11n N9 DQSn2B3B VREFB3BN0 IO DIFFIO_TX_B12n DIFFOUT_B12n AA7 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B11p DIFFOUT_B11p N10 DQS2B3B VREFB3BN0 IO DIFFIO_TX_B12p DIFFOUT_B12p AB73B VREFB3BN0 IO DIFFIO_TX_B13n DIFFOUT_B13n Y7 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B14n DIFFOUT_B14n U8 DQ2B3B VREFB3BN0 IO DIFFIO_TX_B13p DIFFOUT_B13p W7 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B14p DIFFOUT_B14p V9 DQ2B3B VREFB3BN0 IO CLK0n,FPLL_BL_FBn DIFFIO_RX_B15n DIFFOUT_B15n R93B VREFB3BN0 IO DIFFIO_TX_B16n DIFFOUT_B16n AB8 DQ2B3B VREFB3BN0 IO CLK0p,FPLL_BL_FBp DIFFIO_RX_B15p DIFFOUT_B15p P93B VREFB3BN0 IO DIFFIO_TX_B16p DIFFOUT_B16p AA8 DQ2B3B VREFB3BN0 IO DIFFIO_TX_B17n DIFFOUT_B17n Y103B VREFB3BN0 IO DIFFIO_RX_B18n DIFFOUT_B18n AA9 DQ3B3B VREFB3BN0 IO DIFFIO_TX_B17p DIFFOUT_B17p AA10 DQ3B3B VREFB3BN0 IO DIFFIO_RX_B18p DIFFOUT_B18p Y9 DQ3B3B VREFB3BN0 IO DIFFIO_RX_B19n DIFFOUT_B19n L9 DQSn3B3B VREFB3BN0 IO DIFFIO_TX_B20n DIFFOUT_B20n W11 DQ3B3B VREFB3BN0 IO DIFFIO_RX_B19p DIFFOUT_B19p M10 DQS3B3B VREFB3BN0 IO DIFFIO_TX_B20p DIFFOUT_B20p Y113B VREFB3BN0 IO FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn DIFFIO_TX_B21n DIFFOUT_B21n AB10 DQ3B3B VREFB3BN0 IO DIFFIO_RX_B22n DIFFOUT_B22n U10 DQ3B3B VREFB3BN0 IO FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB DIFFIO_TX_B21p DIFFOUT_B21p AB11 DQ3B3B VREFB3BN0 IO DIFFIO_RX_B22p DIFFOUT_B22p U11 DQ3B3B VREFB3BN0 IO CLK1n DIFFIO_RX_B23n DIFFOUT_B23n T10

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U19 Page 8 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U484 DQS for X8 DQS for X16

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

3B VREFB3BN0 IO DIFFIO_TX_B24n DIFFOUT_B24n R11 DQ3B3B VREFB3BN0 IO CLK1p DIFFIO_RX_B23p DIFFOUT_B23p R103B VREFB3BN0 IO DIFFIO_TX_B24p DIFFOUT_B24p P12 DQ3B4A VREFB4AN0 IO RZQ_0 DIFFIO_TX_B25n DIFFOUT_B25n AA134A VREFB4AN0 IO DIFFIO_RX_B26n DIFFOUT_B26n W12 DQ4B4A VREFB4AN0 IO DIFFIO_TX_B25p DIFFOUT_B25p AB13 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B26p DIFFOUT_B26p Y12 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B27n DIFFOUT_B27n U12 DQSn4B4A VREFB4AN0 IO DIFFIO_TX_B28n DIFFOUT_B28n R12 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B27p DIFFOUT_B27p T12 DQS4B4A VREFB4AN0 IO DIFFIO_TX_B28p DIFFOUT_B28p T134A VREFB4AN0 IO DIFFIO_TX_B29n DIFFOUT_B29n AB15 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B30n DIFFOUT_B30n W13 DQ4B4A VREFB4AN0 IO DIFFIO_TX_B29p DIFFOUT_B29p AB16 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B30p DIFFOUT_B30p V13 DQ4B4A VREFB4AN0 IO CLK2n DIFFIO_RX_B31n DIFFOUT_B31n T144A VREFB4AN0 IO DIFFIO_TX_B32n DIFFOUT_B32n AB18 DQ4B4A VREFB4AN0 IO CLK2p DIFFIO_RX_B31p DIFFOUT_B31p U134A VREFB4AN0 IO DIFFIO_TX_B32p DIFFOUT_B32p AA18 DQ4B4A VREFB4AN0 IO DIFFIO_TX_B33n DIFFOUT_B33n AA194A VREFB4AN0 IO DIFFIO_RX_B34n DIFFOUT_B34n Y14 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B33p DIFFOUT_B33p Y19 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B34p DIFFOUT_B34p W14 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B35n DIFFOUT_B35n P14 DQSn5B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B36n DIFFOUT_B36n AA20 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B35p DIFFOUT_B35p R14 DQS5B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B36p DIFFOUT_B36p Y204A VREFB4AN0 IO DIFFIO_TX_B37n DIFFOUT_B37n AA15 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B38n DIFFOUT_B38n U15 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B37p DIFFOUT_B37p Y15 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B38p DIFFOUT_B38p V15 DQ5B DQ1B4A VREFB4AN0 IO CLK3n DIFFIO_RX_B39n DIFFOUT_B39n R154A VREFB4AN0 IO DIFFIO_TX_B40n DIFFOUT_B40n AB20 DQ5B DQ1B4A VREFB4AN0 IO CLK3p DIFFIO_RX_B39p DIFFOUT_B39p T154A VREFB4AN0 IO DIFFIO_TX_B40p DIFFOUT_B40p AB21 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B41n DIFFOUT_B41n AB224A VREFB4AN0 IO DIFFIO_RX_B42n DIFFOUT_B42n Y16 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B41p DIFFOUT_B41p AA22 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B42p DIFFOUT_B42p Y17 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B43n DIFFOUT_B43n U16 DQSn6B DQSn1B4A VREFB4AN0 IO DIFFIO_TX_B44n DIFFOUT_B44n AA17 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B43p DIFFOUT_B43p U17 DQS6B DQS1B4A VREFB4AN0 IO DIFFIO_TX_B44p DIFFOUT_B44p AB174A VREFB4AN0 IO DIFFIO_TX_B45n DIFFOUT_B45n Y22 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B46n DIFFOUT_B46n V18 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B45p DIFFOUT_B45p Y21 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B46p DIFFOUT_B46p W18 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B47n DIFFOUT_B47n W164A VREFB4AN0 IO DIFFIO_TX_B48n DIFFOUT_B48n W21 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B47p DIFFOUT_B47p W174A VREFB4AN0 IO DIFFIO_TX_B48p DIFFOUT_B48p W22 DQ6B DQ1B5A VREFB5AN0 IO RZQ_1 DIFFIO_TX_R1p DIFFOUT_R1p U22 DQ1R5A VREFB5AN0 IO INIT_DONE DIFFIO_RX_R2p DIFFOUT_R2p V205A VREFB5AN0 IO PR_REQUEST DIFFIO_TX_R1n DIFFOUT_R1n U21 DQ1R5A VREFB5AN0 IO CRC_ERROR DIFFIO_RX_R2n DIFFOUT_R2n V195A VREFB5AN0 IO nCEO DIFFIO_TX_R3p DIFFOUT_R3p T19 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R4p DIFFOUT_R4p T17 DQ1R5A VREFB5AN0 IO CvP_CONFDONE DIFFIO_TX_R3n DIFFOUT_R3n T20 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R4n DIFFOUT_R4n T18 DQ1R5A VREFB5AN0 IO DEV_OE DIFFIO_TX_R5p DIFFOUT_R5p T225A VREFB5AN0 IO DIFFIO_RX_R6p DIFFOUT_R6p R16 DQS1R5A VREFB5AN0 IO DEV_CLRn DIFFIO_TX_R5n DIFFOUT_R5n R22 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R6n DIFFOUT_R6n R17 DQSn1R5A VREFB5AN0 IO DIFFIO_TX_R7p DIFFOUT_R7p R20 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R8p DIFFOUT_R8p R19 DQ1R5A VREFB5AN0 IO DIFFIO_TX_R7n DIFFOUT_R7n R215A VREFB5AN0 IO DIFFIO_RX_R8n DIFFOUT_R8n P19 DQ1R5B VREFB5BN0 IO CLK6p DIFFIO_RX_R9p DIFFOUT_R9p L175B VREFB5BN0 IO DIFFIO_TX_R10p DIFFOUT_R10p E20 DQ2R5B VREFB5BN0 IO CLK6n DIFFIO_RX_R9n DIFFOUT_R9n K175B VREFB5BN0 IO DIFFIO_TX_R10n DIFFOUT_R10n F20 DQ2R

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U19 Page 9 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U484 DQS for X8 DQS for X16

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

5B VREFB5BN0 IO DIFFIO_RX_R11p DIFFOUT_R11p H20 DQ2R5B VREFB5BN0 IO FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB DIFFIO_TX_R12p DIFFOUT_R12p G18 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R11n DIFFOUT_R11n H19 DQ2R5B VREFB5BN0 IO FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn DIFFIO_TX_R12n DIFFOUT_R12n G17 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R13p DIFFOUT_R13p K16 DQS2R5B VREFB5BN0 IO DIFFIO_TX_R14p DIFFOUT_R14p F195B VREFB5BN0 IO DIFFIO_RX_R13n DIFFOUT_R13n J16 DQSn2R5B VREFB5BN0 IO DIFFIO_TX_R14n DIFFOUT_R14n F18 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R15p DIFFOUT_R15p J17 DQ2R5B VREFB5BN0 IO DIFFIO_TX_R16p DIFFOUT_R16p J19 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R15n DIFFOUT_R15n J18 DQ2R5B VREFB5BN0 IO DIFFIO_TX_R16n DIFFOUT_R16n H187A GND F177A VREFB7AN0 IO DIFFIO_RX_T1p DIFFOUT_T1p H167A VREFB7AN0 IO DIFFIO_TX_T2p DIFFOUT_T2p C21 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T1n DIFFOUT_T1n G167A VREFB7AN0 IO DIFFIO_TX_T2n DIFFOUT_T2n C20 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T3p DIFFOUT_T3p D18 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T4p DIFFOUT_T4p B20 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T3n DIFFOUT_T3n E17 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T4n DIFFOUT_T4n B21 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T5p DIFFOUT_T5p G15 DQS1T DQS1T7A VREFB7AN0 IO DIFFIO_TX_T6p DIFFOUT_T6p B227A VREFB7AN0 IO DIFFIO_RX_T5n DIFFOUT_T5n G14 DQSn1T DQSn1T7A VREFB7AN0 IO DIFFIO_TX_T6n DIFFOUT_T6n A22 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T7p DIFFOUT_T7p E16 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T8p DIFFOUT_T8p A20 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T7n DIFFOUT_T7n D17 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T8n DIFFOUT_T8n A197A VREFB7AN0 IO CLK11p DIFFIO_RX_T9p DIFFOUT_T9p G137A VREFB7AN0 IO DIFFIO_TX_T10p DIFFOUT_T10p C19 DQ2T DQ1T7A VREFB7AN0 IO CLK11n DIFFIO_RX_T9n DIFFOUT_T9n F147A VREFB7AN0 IO DIFFIO_TX_T10n DIFFOUT_T10n C18 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T11p DIFFOUT_T11p C16 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T12p DIFFOUT_T12p B16 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T11n DIFFOUT_T11n C15 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T12n DIFFOUT_T12n B15 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T13p DIFFOUT_T13p G12 DQS2T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T14p DIFFOUT_T14p A187A VREFB7AN0 IO DIFFIO_RX_T13n DIFFOUT_T13n H12 DQSn2T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T14n DIFFOUT_T14n A17 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T15p DIFFOUT_T15p F15 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T16p DIFFOUT_T16p B18 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T15n DIFFOUT_T15n E14 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T16n DIFFOUT_T16n B177A VREFB7AN0 IO CLK10p DIFFIO_RX_T17p DIFFOUT_T17p H107A VREFB7AN0 IO DIFFIO_TX_T18p DIFFOUT_T18p A15 DQ3T7A VREFB7AN0 IO CLK10n DIFFIO_RX_T17n DIFFOUT_T17n G117A VREFB7AN0 IO DIFFIO_TX_T18n DIFFOUT_T18n A14 DQ3T7A VREFB7AN0 IO DIFFIO_RX_T19p DIFFOUT_T19p D13 DQ3T7A VREFB7AN0 IO DIFFIO_TX_T20p DIFFOUT_T20p C14 DQ3T7A VREFB7AN0 IO DIFFIO_RX_T19n DIFFOUT_T19n C13 DQ3T7A VREFB7AN0 IO DIFFIO_TX_T20n DIFFOUT_T20n D14 DQ3T7A VREFB7AN0 IO DIFFIO_RX_T21p DIFFOUT_T21p H9 DQS3T7A VREFB7AN0 IO DIFFIO_TX_T22p DIFFOUT_T22p A137A VREFB7AN0 IO DIFFIO_RX_T21n DIFFOUT_T21n G8 DQSn3T7A VREFB7AN0 IO DIFFIO_TX_T22n DIFFOUT_T22n B13 DQ3T7A VREFB7AN0 IO DIFFIO_RX_T23p DIFFOUT_T23p E12 DQ3T7A VREFB7AN0 IO DIFFIO_TX_T24p DIFFOUT_T24p B12 DQ3T7A VREFB7AN0 IO DIFFIO_RX_T23n DIFFOUT_T23n F12 DQ3T7A VREFB7AN0 IO RZQ_2 DIFFIO_TX_T24n DIFFOUT_T24n A128A VREFB8AN0 IO CLK9p DIFFIO_RX_T25p DIFFOUT_T25p G108A VREFB8AN0 IO DIFFIO_TX_T26p DIFFOUT_T26p C11 DQ4T8A VREFB8AN0 IO CLK9n DIFFIO_RX_T25n DIFFOUT_T25n F108A VREFB8AN0 IO DIFFIO_TX_T26n DIFFOUT_T26n B11 DQ4T8A VREFB8AN0 IO DIFFIO_RX_T27p DIFFOUT_T27p D11 DQ4T8A VREFB8AN0 IO FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB DIFFIO_TX_T28p DIFFOUT_T28p A8 DQ4T8A VREFB8AN0 IO DIFFIO_RX_T27n DIFFOUT_T27n E11 DQ4T8A VREFB8AN0 IO FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn DIFFIO_TX_T28n DIFFOUT_T28n A7 DQ4T8A VREFB8AN0 IO DIFFIO_RX_T29p DIFFOUT_T29p J9 DQS4T8A VREFB8AN0 IO DIFFIO_TX_T30p DIFFOUT_T30p F8

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U19 Page 10 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U484 DQS for X8 DQS for X16

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

8A VREFB8AN0 IO DIFFIO_RX_T29n DIFFOUT_T29n J8 DQSn4T8A VREFB8AN0 IO DIFFIO_TX_T30n DIFFOUT_T30n E7 DQ4T8A VREFB8AN0 IO DIFFIO_RX_T31p DIFFOUT_T31p C10 DQ4T8A VREFB8AN0 IO DIFFIO_TX_T32p DIFFOUT_T32p C6 DQ4T8A VREFB8AN0 IO DIFFIO_RX_T31n DIFFOUT_T31n C9 DQ4T8A VREFB8AN0 IO DIFFIO_TX_T32n DIFFOUT_T32n D78A VREFB8AN0 IO CLK8p,FPLL_TL_FBp DIFFIO_RX_T33p DIFFOUT_T33p K78A VREFB8AN0 IO DIFFIO_TX_T34p DIFFOUT_T34p A10 DQ5T8A VREFB8AN0 IO CLK8n,FPLL_TL_FBn DIFFIO_RX_T33n DIFFOUT_T33n J78A VREFB8AN0 IO DIFFIO_TX_T34n DIFFOUT_T34n A9 DQ5T8A VREFB8AN0 IO DIFFIO_RX_T35p DIFFOUT_T35p D9 DQ5T8A VREFB8AN0 IO DIFFIO_TX_T36p DIFFOUT_T36p B6 DQ5T8A VREFB8AN0 IO DIFFIO_RX_T35n DIFFOUT_T35n D8 DQ5T8A VREFB8AN0 IO DIFFIO_TX_T36n DIFFOUT_T36n B5 DQ5T8A VREFB8AN0 IO DIFFIO_RX_T37p DIFFOUT_T37p H8 DQS5T8A VREFB8AN0 IO DIFFIO_TX_T38p DIFFOUT_T38p C88A VREFB8AN0 IO DIFFIO_RX_T37n DIFFOUT_T37n G7 DQSn5T8A VREFB8AN0 IO DIFFIO_TX_T38n DIFFOUT_T38n B8 DQ5T8A VREFB8AN0 IO DIFFIO_RX_T39p DIFFOUT_T39p H6 DQ5T8A VREFB8AN0 IO DIFFIO_TX_T40p DIFFOUT_T40p E6 DQ5T8A VREFB8AN0 IO DIFFIO_RX_T39n DIFFOUT_T39n G6 DQ5T8A VREFB8AN0 IO DIFFIO_TX_T40n DIFFOUT_T40n F79A MSEL0 MSEL0 L69A CONF_DONE CONF_DONE J69A MSEL1 MSEL1 K69A nSTATUS nSTATUS G59A nCE nCE H59A MSEL2 MSEL2 A29A MSEL3 MSEL3 E59A nCONFIG nCONFIG A49A MSEL4 MSEL4 C59A GND F3

GND A21GND AB19GND AB2GND AB1GND AA16GND AA11GND AA4GND AA3GND Y13GND Y8GND Y5GND Y2GND Y1GND W20GND W4GND W3GND V22GND V17GND V4GND V2GND V1GND U19GND U14GND U9GND U5GND U4GND U3GND T11GND T2GND T1GND R13GND R3GND P10GND P4GND P2GND P1GND N22GND N15GND N13

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U19 Page 11 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U484 DQS for X8 DQS for X16

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

GND N11GND N7GND N5GND N3GND M19GND M14GND M12GND M9GND M4GND M2GND M1GND L16GND L13GND L11GND L5GND L3GND K14GND K12GND K10GND K8GND K4GND K2GND K1GND J20GND J15GND J13GND J11GND J5GND J3GND H14GND H4GND H3GND H2GND H1GND G9GND G4GND G3GND F21GND F16GND F11GND F6GND F5GND F2GND F1GND E13GND E4GND E3GND D20GND D10GND D5GND D2GND D1GND C22GND C17GND C7GND C4GND C3GND B14GND B2GND B1GND A11GND A5VCC L4VCC P15VCC P13VCC P11VCC P3VCC N14VCC N12VCC N4VCC M15

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U19 Page 12 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U484 DQS for X8 DQS for X16

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

VCC M13VCC M11VCC L14VCC L12VCC L10VCC K13VCC K11VCC K9VCC K5VCC K3VCC J14VCC J12VCC J10VCC J4VCC H15VCC H13VCC H11DNU B3DNU B4DNU D21DNU E10VCCPGM Y6VCCPGM U20VCCPGM B7VCCBAT A3VCCIO2A D4VCCIO2A Y4VCCIO2A R1VCCIO2A J1VCCIO3A T6VCCIO3A AA6VCCIO3B R8VCCIO3B AB9VCCIO3B W10VCCIO3B V7VCCIO4A T16VCCIO4A AB14VCCIO4A AA21VCCIO4A Y18VCCIO4A W15VCCIO4A V12VCCIO5A T21VCCIO5A R18VCCIO5B G19VCCIO5B P20VCCIO5B N17VCCIO5B L21VCCIO5B K18VCCIO5B H22VCCIO7A B19VCCIO7A H17VCCIO7A E18VCCIO7A D15VCCIO7A C12VCCIO7A A16VCCIO8A B9VCCIO8A H7VCCIO8A E8VCCIO8A A6VCCPD1A2A R2VCCPD1A2A J2VCCPD1A2A E1VCCPD3A V6VCCPD3B4A W9VCCPD3B4A V16VCCPD3B4A V14VCCPD3B4A V10VCCPD5A P17VCCPD5B M18VCCPD5B N19VCCPD7A8A E15

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List U19 Page 13 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel U484 DQS for X8 DQS for X16

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

VCCPD7A8A F13VCCPD7A8A F9VCCPD7A8A E9

2A VREFB2AN0 VREFB2AN0 W13A VREFB3AN0 VREFB3AN0 W63B VREFB3BN0 VREFB3BN0 AB124A VREFB4AN0 VREFB4AN0 AA145A VREFB5AN0 VREFB5AN0 V215B VREFB5BN0 VREFB5BN0 K207A VREFB7AN0 VREFB7AN0 D168A VREFB8AN0 VREFB8AN0 B10

NC AB3NC V11NC P22NC P21NC P18NC P16NC N21NC N20NC N18NC N16NC M22NC M21NC M20NC M17NC M16NC L22NC L20NC L19NC L18NC L15NC K22NC K21NC K19NC K15NC J22NC J21NC H21NC G22NC G21NC G20NC F22NC E22NC E21NC D22RREF_TL A1VCCA_FPLL M3VCCA_FPLL T3VCCA_FPLL T4VCCA_FPLL F4VCCA_FPLL U18VCCA_FPLL E19VCC_AUX D6VCC_AUX D12VCC_AUX D19VCC_AUX W19VCC_AUX AA12VCC_AUX AB5

Note:(1) For more information about pin definition and pin connection guidelines, refer to theCyclone V Device Family Pin Connection Guidelines.

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List F17 Page 14 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel F256 DQS for X8

2A VREFB2AN0 IO DIFFIO_TX_L9n DIFFOUT_L9n F32A VREFB2AN0 IO DIFFIO_RX_L10n DIFFOUT_L10n G3 DQ1L2A VREFB2AN0 IO DIFFIO_TX_L9p DIFFOUT_L9p F4 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L10p DIFFOUT_L10p H3 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L11n DIFFOUT_L11n H4 DQSn1L2A VREFB2AN0 IO DIFFIO_TX_L12n DIFFOUT_L12n E2 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L11p DIFFOUT_L11p H5 DQS1L2A VREFB2AN0 IO DIFFIO_TX_L12p DIFFOUT_L12p F22A VREFB2AN0 IO DIFFIO_TX_L13n DIFFOUT_L13n G1 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L14n DIFFOUT_L14n J2 DQ1L2A VREFB2AN0 IO DIFFIO_TX_L13p DIFFOUT_L13p G2 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L14p DIFFOUT_L14p J3 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L15n DIFFOUT_L15n K42A VREFB2AN0 IO DIFFIO_TX_L16n DIFFOUT_L16n H1 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L15p DIFFOUT_L15p K52A VREFB2AN0 IO DIFFIO_TX_L16p DIFFOUT_L16p J1 DQ1L3A TDO TDO M63A nCSO DATA4 L33A TMS TMS L63A AS_DATA3 DATA3 M23A TCK TCK M33A AS_DATA2 DATA2 L23A TDI TDI L43A AS_DATA1 DATA1 K13A DCLK DCLK M53A AS_DATA0,ASDO DATA0 M13A VREFB3AN0 IO DATA6 DIFFIO_RX_B1n DIFFOUT_B1n N4 DQ1B3A VREFB3AN0 IO DATA5 DIFFIO_TX_B2n DIFFOUT_B2n N13A VREFB3AN0 IO DATA8 DIFFIO_RX_B1p DIFFOUT_B1p P4 DQ1B3A VREFB3AN0 IO DATA7 DIFFIO_TX_B2p DIFFOUT_B2p P1 DQ1B3A VREFB3AN0 IO DATA10 DIFFIO_RX_B3n DIFFOUT_B3n M7 DQSn1B3A VREFB3AN0 IO DATA9 DIFFIO_TX_B4n DIFFOUT_B4n R1 DQ1B3A VREFB3AN0 IO DATA12 DIFFIO_RX_B3p DIFFOUT_B3p L7 DQS1B3A VREFB3AN0 IO DATA11 DIFFIO_TX_B4p DIFFOUT_B4p P23A VREFB3AN0 IO DATA14 DIFFIO_RX_B5n DIFFOUT_B5n P3 DQ1B3A VREFB3AN0 IO DATA13 DIFFIO_TX_B6n DIFFOUT_B6n T2 DQ1B3A VREFB3AN0 IO CLKUSR DIFFIO_RX_B5p DIFFOUT_B5p N3 DQ1B3A VREFB3AN0 IO DATA15 DIFFIO_TX_B6p DIFFOUT_B6p R2 DQ1B3A VREFB3AN0 IO PR_DONE DIFFIO_RX_B7n DIFFOUT_B7n R63A VREFB3AN0 IO PR_READY DIFFIO_TX_B8n DIFFOUT_B8n T3 DQ1B3A VREFB3AN0 IO PR_ERROR DIFFIO_RX_B7p DIFFOUT_B7p P73A VREFB3AN0 IO DIFFIO_TX_B8p DIFFOUT_B8p R4 DQ1B3B VREFB3BN0 IO DIFFIO_TX_B17n DIFFOUT_B17n T53B VREFB3BN0 IO DIFFIO_RX_B18n DIFFOUT_B18n R7 DQ2B3B VREFB3BN0 IO DIFFIO_TX_B17p DIFFOUT_B17p T4 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B18p DIFFOUT_B18p P8 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B19n DIFFOUT_B19n M8 DQSn2B3B VREFB3BN0 IO DIFFIO_TX_B20n DIFFOUT_B20n T7 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B19p DIFFOUT_B19p L9 DQS2B3B VREFB3BN0 IO DIFFIO_TX_B20p DIFFOUT_B20p T83B VREFB3BN0 IO FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn DIFFIO_TX_B21n DIFFOUT_B21n R11 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B22n DIFFOUT_B22n T12 DQ2B3B VREFB3BN0 IO FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB DIFFIO_TX_B21p DIFFOUT_B21p R12 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B22p DIFFOUT_B22p T13 DQ2B

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List F17 Page 15 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel F256 DQS for X8

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

3B VREFB3BN0 IO CLK1n DIFFIO_RX_B23n DIFFOUT_B23n R93B VREFB3BN0 IO DIFFIO_TX_B24n DIFFOUT_B24n T10 DQ2B3B VREFB3BN0 IO CLK1p DIFFIO_RX_B23p DIFFOUT_B23p P93B VREFB3BN0 IO DIFFIO_TX_B24p DIFFOUT_B24p R10 DQ2B4A VREFB4AN0 IO RZQ_0 DIFFIO_TX_B25n DIFFOUT_B25n R154A VREFB4AN0 IO DIFFIO_RX_B26n DIFFOUT_B26n T15 DQ3B4A VREFB4AN0 IO DIFFIO_TX_B25p DIFFOUT_B25p P16 DQ3B4A VREFB4AN0 IO DIFFIO_RX_B26p DIFFOUT_B26p R16 DQ3B4A VREFB4AN0 IO DIFFIO_RX_B27n DIFFOUT_B27n M10 DQSn3B4A VREFB4AN0 IO DIFFIO_TX_B28n DIFFOUT_B28n M13 DQ3B4A VREFB4AN0 IO DIFFIO_RX_B27p DIFFOUT_B27p L10 DQS3B4A VREFB4AN0 IO DIFFIO_TX_B28p DIFFOUT_B28p N144A VREFB4AN0 IO DIFFIO_TX_B29n DIFFOUT_B29n P14 DQ3B4A VREFB4AN0 IO DIFFIO_RX_B30n DIFFOUT_B30n M12 DQ3B4A VREFB4AN0 IO DIFFIO_TX_B29p DIFFOUT_B29p P13 DQ3B4A VREFB4AN0 IO DIFFIO_RX_B30p DIFFOUT_B30p M11 DQ3B4A VREFB4AN0 IO CLK2n DIFFIO_RX_B31n DIFFOUT_B31n P114A VREFB4AN0 IO DIFFIO_TX_B32n DIFFOUT_B32n T14 DQ3B4A VREFB4AN0 IO CLK2p DIFFIO_RX_B31p DIFFOUT_B31p N114A VREFB4AN0 IO DIFFIO_TX_B32p DIFFOUT_B32p R14 DQ3B5A VREFB5AN0 IO RZQ_1 DIFFIO_TX_R1p DIFFOUT_R1p N15 DQ1R5A VREFB5AN0 IO INIT_DONE DIFFIO_RX_R2p DIFFOUT_R2p L135A VREFB5AN0 IO PR_REQUEST DIFFIO_TX_R1n DIFFOUT_R1n N16 DQ1R5A VREFB5AN0 IO CRC_ERROR DIFFIO_RX_R2n DIFFOUT_R2n K145A VREFB5AN0 IO nCEO DIFFIO_TX_R3p DIFFOUT_R3p H16 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R4p DIFFOUT_R4p L14 DQ1R5A VREFB5AN0 IO CvP_CONFDONE DIFFIO_TX_R3n DIFFOUT_R3n J16 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R4n DIFFOUT_R4n L15 DQ1R5A VREFB5AN0 IO DEV_OE DIFFIO_TX_R5p DIFFOUT_R5p G155A VREFB5AN0 IO DIFFIO_RX_R6p DIFFOUT_R6p K12 DQS1R5A VREFB5AN0 IO DEV_CLRn DIFFIO_TX_R5n DIFFOUT_R5n G16 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R6n DIFFOUT_R6n J12 DQSn1R5A VREFB5AN0 IO DIFFIO_TX_R7p DIFFOUT_R7p J14 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R8p DIFFOUT_R8p K15 DQ1R5A VREFB5AN0 IO DIFFIO_TX_R7n DIFFOUT_R7n H155A VREFB5AN0 IO DIFFIO_RX_R8n DIFFOUT_R8n K16 DQ1R5B VREFB5BN0 IO CLK6p DIFFIO_RX_R9p DIFFOUT_R9p F125B VREFB5BN0 IO DIFFIO_TX_R10p DIFFOUT_R10p E16 DQ2R5B VREFB5BN0 IO CLK6n DIFFIO_RX_R9n DIFFOUT_R9n G125B VREFB5BN0 IO DIFFIO_TX_R10n DIFFOUT_R10n D16 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R11p DIFFOUT_R11p E12 DQ2R5B VREFB5BN0 IO FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB DIFFIO_TX_R12p DIFFOUT_R12p B16 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R11n DIFFOUT_R11n D13 DQ2R5B VREFB5BN0 IO FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn DIFFIO_TX_R12n DIFFOUT_R12n C16 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R13p DIFFOUT_R13p H13 DQS2R5B VREFB5BN0 IO DIFFIO_TX_R14p DIFFOUT_R14p B155B VREFB5BN0 IO DIFFIO_RX_R13n DIFFOUT_R13n G13 DQSn2R5B VREFB5BN0 IO DIFFIO_TX_R14n DIFFOUT_R14n C15 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R15p DIFFOUT_R15p F14 DQ2R5B VREFB5BN0 IO DIFFIO_TX_R16p DIFFOUT_R16p D14 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R15n DIFFOUT_R15n F15 DQ2R5B VREFB5BN0 IO DIFFIO_TX_R16n DIFFOUT_R16n E157A GND C147A VREFB7AN0 IO CLK10p DIFFIO_RX_T17p DIFFOUT_T17p F11

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List F17 Page 16 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel F256 DQS for X8

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

7A VREFB7AN0 IO DIFFIO_TX_T18p DIFFOUT_T18p A15 DQ1T7A VREFB7AN0 IO CLK10n DIFFIO_RX_T17n DIFFOUT_T17n F107A VREFB7AN0 IO DIFFIO_TX_T18n DIFFOUT_T18n A14 DQ1T7A VREFB7AN0 IO DIFFIO_RX_T19p DIFFOUT_T19p D11 DQ1T7A VREFB7AN0 IO DIFFIO_TX_T20p DIFFOUT_T20p A13 DQ1T7A VREFB7AN0 IO DIFFIO_RX_T19n DIFFOUT_T19n C11 DQ1T7A VREFB7AN0 IO DIFFIO_TX_T20n DIFFOUT_T20n A12 DQ1T7A VREFB7AN0 IO DIFFIO_RX_T21p DIFFOUT_T21p E10 DQS1T7A VREFB7AN0 IO DIFFIO_TX_T22p DIFFOUT_T22p B127A VREFB7AN0 IO DIFFIO_RX_T21n DIFFOUT_T21n E9 DQSn1T7A VREFB7AN0 IO DIFFIO_TX_T22n DIFFOUT_T22n B11 DQ1T7A VREFB7AN0 IO DIFFIO_RX_T23p DIFFOUT_T23p C10 DQ1T7A VREFB7AN0 IO DIFFIO_TX_T24p DIFFOUT_T24p B10 DQ1T7A VREFB7AN0 IO DIFFIO_RX_T23n DIFFOUT_T23n C9 DQ1T7A VREFB7AN0 IO RZQ_2 DIFFIO_TX_T24n DIFFOUT_T24n A108A VREFB8AN0 IO CLK9p DIFFIO_RX_T25p DIFFOUT_T25p F88A VREFB8AN0 IO DIFFIO_TX_T26p DIFFOUT_T26p A8 DQ2T8A VREFB8AN0 IO CLK9n DIFFIO_RX_T25n DIFFOUT_T25n F78A VREFB8AN0 IO DIFFIO_TX_T26n DIFFOUT_T26n A9 DQ2T8A VREFB8AN0 IO DIFFIO_RX_T27p DIFFOUT_T27p B8 DQ2T8A VREFB8AN0 IO FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB DIFFIO_TX_T28p DIFFOUT_T28p A5 DQ2T8A VREFB8AN0 IO DIFFIO_RX_T27n DIFFOUT_T27n A7 DQ2T8A VREFB8AN0 IO FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn DIFFIO_TX_T28n DIFFOUT_T28n A4 DQ2T8A VREFB8AN0 IO DIFFIO_RX_T29p DIFFOUT_T29p D8 DQS2T8A VREFB8AN0 IO DIFFIO_TX_T30p DIFFOUT_T30p B38A VREFB8AN0 IO DIFFIO_RX_T29n DIFFOUT_T29n D7 DQSn2T8A VREFB8AN0 IO DIFFIO_TX_T30n DIFFOUT_T30n A3 DQ2T8A VREFB8AN0 IO DIFFIO_RX_T31p DIFFOUT_T31p B7 DQ2T8A VREFB8AN0 IO DIFFIO_TX_T32p DIFFOUT_T32p C3 DQ2T8A VREFB8AN0 IO DIFFIO_RX_T31n DIFFOUT_T31n B6 DQ2T8A VREFB8AN0 IO DIFFIO_TX_T32n DIFFOUT_T32n C49A MSEL0 MSEL0 E59A CONF_DONE CONF_DONE C19A MSEL1 MSEL1 E49A nSTATUS nSTATUS D19A nCE nCE E19A MSEL2 MSEL2 D29A MSEL3 MSEL3 E69A nCONFIG nCONFIG D39A MSEL4 MSEL4 F69A GND D4

GND H12GND T16GND T6GND T1GND R13GND P10GND P5GND N2GND M14GND M9GND M4GND L11GND L1

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List F17 Page 17 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel F256 DQS for X8

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

GND K13GND K10GND K8GND K6GND J11GND J9GND J7GND J5GND H10GND H8GND H6GND G11GND G9GND G7GND G4GND F16GND F1GND E13GND E8GND E3GND D10GND D5GND C2GND B9GND B1GND A16GND A11GND A6VCC F9VCC L8VCC K11VCC K9VCC K7VCC J10VCC J8VCC J6VCC H11VCC H9VCC H7VCC G10VCC G8VCC G6DNU B2DNU A2DNU C13DNU C8VCCPGM P6VCCPGM M15VCCPGM C6VCCBAT C5VCCIO2A H2VCCIO2A K3VCCIO3A N7VCCIO3A R3

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List F17 Page 18 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel F256 DQS for X8

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

VCCIO3B R8VCCIO3B T11VCCIO4A N12VCCIO4A P15VCCIO5A J15VCCIO5A L16VCCIO5B D15VCCIO5B G14VCCIO7A B14VCCIO7A C12VCCIO8A C7VCCIO8A B4VCCPD1A2A J4VCCPD3A N6VCCPD3B4A N10VCCPD3B4A N8VCCPD5A J13VCCPD5B H14VCCPD7A8A E7VCCPD7A8A E11

2A VREFB2AN0 VREFB2AN0 K23A VREFB3AN0 VREFB3AN0 R53B VREFB3BN0 VREFB3BN0 T94A VREFB4AN0 VREFB4AN0 P125A VREFB5AN0 VREFB5AN0 M165B VREFB5BN0 VREFB5BN0 E147A VREFB7AN0 VREFB7AN0 B138A VREFB8AN0 VREFB8AN0 B5

RREF_TL A1VCCA_FPLL G5VCCA_FPLL L5VCCA_FPLL F5VCCA_FPLL L12VCCA_FPLL F13VCC_AUX D6VCC_AUX D9VCC_AUX D12VCC_AUX N13VCC_AUX N9VCC_AUX N5

Note:(1) For more information about pin definition and pin connection guidelines, refer to theCyclone V Device Family Pin Connection Guidelines.

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List F23 Page 19 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel F484 DQS for X8 DQS for X16

2A VREFB2AN0 IO DIFFIO_TX_L9n DIFFOUT_L9n C12A VREFB2AN0 IO DIFFIO_RX_L10n DIFFOUT_L10n G1 DQ1L2A VREFB2AN0 IO DIFFIO_TX_L9p DIFFOUT_L9p C2 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L10p DIFFOUT_L10p G2 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L11n DIFFOUT_L11n E2 DQSn1L2A VREFB2AN0 IO DIFFIO_TX_L12n DIFFOUT_L12n L1 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L11p DIFFOUT_L11p D3 DQS1L2A VREFB2AN0 IO DIFFIO_TX_L12p DIFFOUT_L12p L22A VREFB2AN0 IO DIFFIO_TX_L13n DIFFOUT_L13n N1 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L14n DIFFOUT_L14n U1 DQ1L2A VREFB2AN0 IO DIFFIO_TX_L13p DIFFOUT_L13p N2 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L14p DIFFOUT_L14p U2 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L15n DIFFOUT_L15n W22A VREFB2AN0 IO DIFFIO_TX_L16n DIFFOUT_L16n AA1 DQ1L2A VREFB2AN0 IO DIFFIO_RX_L15p DIFFOUT_L15p Y32A VREFB2AN0 IO DIFFIO_TX_L16p DIFFOUT_L16p AA2 DQ1L3A TDO TDO M53A nCSO DATA4 R43A TMS TMS P53A AS_DATA3 DATA3 T43A TCK TCK V53A AS_DATA2 DATA2 AA53A TDI TDI W53A AS_DATA1 DATA1 AB33A DCLK DCLK V33A AS_DATA0,ASDO DATA0 AB43A VREFB3AN0 IO DATA6 DIFFIO_RX_B1n DIFFOUT_B1n R6 DQ1B3A VREFB3AN0 IO DATA5 DIFFIO_TX_B2n DIFFOUT_B2n U73A VREFB3AN0 IO DATA8 DIFFIO_RX_B1p DIFFOUT_B1p R5 DQ1B3A VREFB3AN0 IO DATA7 DIFFIO_TX_B2p DIFFOUT_B2p U8 DQ1B3A VREFB3AN0 IO DATA10 DIFFIO_RX_B3n DIFFOUT_B3n P6 DQSn1B3A VREFB3AN0 IO DATA9 DIFFIO_TX_B4n DIFFOUT_B4n W8 DQ1B3A VREFB3AN0 IO DATA12 DIFFIO_RX_B3p DIFFOUT_B3p N6 DQS1B3A VREFB3AN0 IO DATA11 DIFFIO_TX_B4p DIFFOUT_B4p W93A VREFB3AN0 IO DATA14 DIFFIO_RX_B5n DIFFOUT_B5n T7 DQ1B3A VREFB3AN0 IO DATA13 DIFFIO_TX_B6n DIFFOUT_B6n U6 DQ1B3A VREFB3AN0 IO CLKUSR DIFFIO_RX_B5p DIFFOUT_B5p T8 DQ1B3A VREFB3AN0 IO DATA15 DIFFIO_TX_B6p DIFFOUT_B6p V6 DQ1B3A VREFB3AN0 IO PR_DONE DIFFIO_RX_B7n DIFFOUT_B7n M63A VREFB3AN0 IO PR_READY DIFFIO_TX_B8n DIFFOUT_B8n R7 DQ1B3A VREFB3AN0 IO PR_ERROR DIFFIO_RX_B7p DIFFOUT_B7p M73A VREFB3AN0 IO DIFFIO_TX_B8p DIFFOUT_B8p P7 DQ1B3B VREFB3BN0 IO DIFFIO_TX_B9n DIFFOUT_B9n AB63B VREFB3BN0 IO DIFFIO_RX_B10n DIFFOUT_B10n V9 DQ2B3B VREFB3BN0 IO DIFFIO_TX_B9p DIFFOUT_B9p AB5 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B10p DIFFOUT_B10p V10 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B11n DIFFOUT_B11n P8 DQSn2B3B VREFB3BN0 IO DIFFIO_TX_B12n DIFFOUT_B12n AA7 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B11p DIFFOUT_B11p N8 DQS2B3B VREFB3BN0 IO DIFFIO_TX_B12p DIFFOUT_B12p AB73B VREFB3BN0 IO DIFFIO_TX_B13n DIFFOUT_B13n AA8 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B14n DIFFOUT_B14n T9 DQ2B3B VREFB3BN0 IO DIFFIO_TX_B13p DIFFOUT_B13p AB8 DQ2B3B VREFB3BN0 IO DIFFIO_RX_B14p DIFFOUT_B14p U10 DQ2B3B VREFB3BN0 IO CLK0n,FPLL_BL_FBn DIFFIO_RX_B15n DIFFOUT_B15n M83B VREFB3BN0 IO DIFFIO_TX_B16n DIFFOUT_B16n AA10 DQ2B3B VREFB3BN0 IO CLK0p,FPLL_BL_FBp DIFFIO_RX_B15p DIFFOUT_B15p M93B VREFB3BN0 IO DIFFIO_TX_B16p DIFFOUT_B16p AA9 DQ2B3B VREFB3BN0 IO DIFFIO_TX_B17n DIFFOUT_B17n Y103B VREFB3BN0 IO DIFFIO_RX_B18n DIFFOUT_B18n T10 DQ3B3B VREFB3BN0 IO DIFFIO_TX_B17p DIFFOUT_B17p Y9 DQ3B3B VREFB3BN0 IO DIFFIO_RX_B18p DIFFOUT_B18p R9 DQ3B3B VREFB3BN0 IO DIFFIO_RX_B19n DIFFOUT_B19n U11 DQSn3B3B VREFB3BN0 IO DIFFIO_TX_B20n DIFFOUT_B20n R12 DQ3B3B VREFB3BN0 IO DIFFIO_RX_B19p DIFFOUT_B19p U12 DQS3B3B VREFB3BN0 IO DIFFIO_TX_B20p DIFFOUT_B20p P123B VREFB3BN0 IO FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn DIFFIO_TX_B21n DIFFOUT_B21n AB10 DQ3B3B VREFB3BN0 IO DIFFIO_RX_B22n DIFFOUT_B22n R10 DQ3B3B VREFB3BN0 IO FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB DIFFIO_TX_B21p DIFFOUT_B21p AB11 DQ3B3B VREFB3BN0 IO DIFFIO_RX_B22p DIFFOUT_B22p R11 DQ3B3B VREFB3BN0 IO CLK1n DIFFIO_RX_B23n DIFFOUT_B23n P9

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List F23 Page 20 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel F484 DQS for X8 DQS for X16

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

3B VREFB3BN0 IO DIFFIO_TX_B24n DIFFOUT_B24n Y11 DQ3B3B VREFB3BN0 IO CLK1p DIFFIO_RX_B23p DIFFOUT_B23p N93B VREFB3BN0 IO DIFFIO_TX_B24p DIFFOUT_B24p AA12 DQ3B4A VREFB4AN0 IO RZQ_0 DIFFIO_TX_B25n DIFFOUT_B25n AB134A VREFB4AN0 IO DIFFIO_RX_B26n DIFFOUT_B26n V13 DQ4B4A VREFB4AN0 IO DIFFIO_TX_B25p DIFFOUT_B25p AB12 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B26p DIFFOUT_B26p U13 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B27n DIFFOUT_B27n T12 DQSn4B4A VREFB4AN0 IO DIFFIO_TX_B28n DIFFOUT_B28n AA14 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B27p DIFFOUT_B27p T13 DQS4B4A VREFB4AN0 IO DIFFIO_TX_B28p DIFFOUT_B28p AA134A VREFB4AN0 IO DIFFIO_TX_B29n DIFFOUT_B29n AB15 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B30n DIFFOUT_B30n Y14 DQ4B4A VREFB4AN0 IO DIFFIO_TX_B29p DIFFOUT_B29p AA15 DQ4B4A VREFB4AN0 IO DIFFIO_RX_B30p DIFFOUT_B30p Y15 DQ4B4A VREFB4AN0 IO CLK2n DIFFIO_RX_B31n DIFFOUT_B31n V144A VREFB4AN0 IO DIFFIO_TX_B32n DIFFOUT_B32n AB17 DQ4B4A VREFB4AN0 IO CLK2p DIFFIO_RX_B31p DIFFOUT_B31p V154A VREFB4AN0 IO DIFFIO_TX_B32p DIFFOUT_B32p AB18 DQ4B4A VREFB4AN0 IO DIFFIO_TX_B33n DIFFOUT_B33n AB204A VREFB4AN0 IO DIFFIO_RX_B34n DIFFOUT_B34n Y16 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B33p DIFFOUT_B33p AB21 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B34p DIFFOUT_B34p Y17 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B35n DIFFOUT_B35n T14 DQSn5B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B36n DIFFOUT_B36n AA17 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B35p DIFFOUT_B35p U15 DQS5B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B36p DIFFOUT_B36p AA184A VREFB4AN0 IO DIFFIO_TX_B37n DIFFOUT_B37n AA19 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B38n DIFFOUT_B38n V20 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B37p DIFFOUT_B37p AA20 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B38p DIFFOUT_B38p W19 DQ5B DQ1B4A VREFB4AN0 IO CLK3n DIFFIO_RX_B39n DIFFOUT_B39n V164A VREFB4AN0 IO DIFFIO_TX_B40n DIFFOUT_B40n AB22 DQ5B DQ1B4A VREFB4AN0 IO CLK3p DIFFIO_RX_B39p DIFFOUT_B39p W164A VREFB4AN0 IO DIFFIO_TX_B40p DIFFOUT_B40p AA22 DQ5B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B41n DIFFOUT_B41n Y224A VREFB4AN0 IO DIFFIO_RX_B42n DIFFOUT_B42n Y20 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B41p DIFFOUT_B41p W22 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B42p DIFFOUT_B42p Y19 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B43n DIFFOUT_B43n P14 DQSn6B DQSn1B4A VREFB4AN0 IO DIFFIO_TX_B44n DIFFOUT_B44n Y21 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B43p DIFFOUT_B43p R14 DQS6B DQS1B4A VREFB4AN0 IO DIFFIO_TX_B44p DIFFOUT_B44p W214A VREFB4AN0 IO DIFFIO_TX_B45n DIFFOUT_B45n U22 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B46n DIFFOUT_B46n V19 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_TX_B45p DIFFOUT_B45p V21 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B46p DIFFOUT_B46p V18 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B47n DIFFOUT_B47n U164A VREFB4AN0 IO DIFFIO_TX_B48n DIFFOUT_B48n U21 DQ6B DQ1B4A VREFB4AN0 IO DIFFIO_RX_B47p DIFFOUT_B47p U174A VREFB4AN0 IO DIFFIO_TX_B48p DIFFOUT_B48p U20 DQ6B DQ1B5A VREFB5AN0 IO RZQ_1 DIFFIO_TX_R1p DIFFOUT_R1p T19 DQ1R5A VREFB5AN0 IO INIT_DONE DIFFIO_RX_R2p DIFFOUT_R2p T185A VREFB5AN0 IO PR_REQUEST DIFFIO_TX_R1n DIFFOUT_R1n T20 DQ1R5A VREFB5AN0 IO CRC_ERROR DIFFIO_RX_R2n DIFFOUT_R2n T175A VREFB5AN0 IO nCEO DIFFIO_TX_R3p DIFFOUT_R3p T22 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R4p DIFFOUT_R4p T15 DQ1R5A VREFB5AN0 IO CvP_CONFDONE DIFFIO_TX_R3n DIFFOUT_R3n R22 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R4n DIFFOUT_R4n R15 DQ1R5A VREFB5AN0 IO DEV_OE DIFFIO_TX_R5p DIFFOUT_R5p R215A VREFB5AN0 IO DIFFIO_RX_R6p DIFFOUT_R6p R16 DQS1R5A VREFB5AN0 IO DEV_CLRn DIFFIO_TX_R5n DIFFOUT_R5n P22 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R6n DIFFOUT_R6n R17 DQSn1R5A VREFB5AN0 IO DIFFIO_TX_R7p DIFFOUT_R7p P19 DQ1R5A VREFB5AN0 IO DIFFIO_RX_R8p DIFFOUT_R8p P16 DQ1R5A VREFB5AN0 IO DIFFIO_TX_R7n DIFFOUT_R7n P185A VREFB5AN0 IO DIFFIO_RX_R8n DIFFOUT_R8n P17 DQ1R5B VREFB5BN0 IO CLK6p DIFFIO_RX_R9p DIFFOUT_R9p N165B VREFB5BN0 IO DIFFIO_TX_R10p DIFFOUT_R10p N20 DQ2R5B VREFB5BN0 IO CLK6n DIFFIO_RX_R9n DIFFOUT_R9n M165B VREFB5BN0 IO DIFFIO_TX_R10n DIFFOUT_R10n N21 DQ2R

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List F23 Page 21 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel F484 DQS for X8 DQS for X16

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

5B VREFB5BN0 IO DIFFIO_RX_R11p DIFFOUT_R11p N19 DQ2R5B VREFB5BN0 IO FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB DIFFIO_TX_R12p DIFFOUT_R12p M22 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R11n DIFFOUT_R11n M18 DQ2R5B VREFB5BN0 IO FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn DIFFIO_TX_R12n DIFFOUT_R12n L22 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R13p DIFFOUT_R13p K17 DQS2R5B VREFB5BN0 IO DIFFIO_TX_R14p DIFFOUT_R14p M205B VREFB5BN0 IO DIFFIO_RX_R13n DIFFOUT_R13n L17 DQSn2R5B VREFB5BN0 IO DIFFIO_TX_R14n DIFFOUT_R14n M21 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R15p DIFFOUT_R15p L19 DQ2R5B VREFB5BN0 IO DIFFIO_TX_R16p DIFFOUT_R16p K21 DQ2R5B VREFB5BN0 IO DIFFIO_RX_R15n DIFFOUT_R15n L18 DQ2R5B VREFB5BN0 IO DIFFIO_TX_R16n DIFFOUT_R16n K227A GND F177A VREFB7AN0 IO DIFFIO_RX_T1p DIFFOUT_T1p K207A VREFB7AN0 IO DIFFIO_TX_T2p DIFFOUT_T2p B16 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T1n DIFFOUT_T1n K197A VREFB7AN0 IO DIFFIO_TX_T2n DIFFOUT_T2n C16 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T3p DIFFOUT_T3p D17 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T4p DIFFOUT_T4p G17 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T3n DIFFOUT_T3n E16 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T4n DIFFOUT_T4n G16 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T5p DIFFOUT_T5p G18 DQS1T DQS1T7A VREFB7AN0 IO DIFFIO_TX_T6p DIFFOUT_T6p J197A VREFB7AN0 IO DIFFIO_RX_T5n DIFFOUT_T5n H18 DQSn1T DQSn1T7A VREFB7AN0 IO DIFFIO_TX_T6n DIFFOUT_T6n J18 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T7p DIFFOUT_T7p E15 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T8p DIFFOUT_T8p A15 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T7n DIFFOUT_T7n F15 DQ1T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T8n DIFFOUT_T8n A147A VREFB7AN0 IO CLK11p DIFFIO_RX_T9p DIFFOUT_T9p H167A VREFB7AN0 IO DIFFIO_TX_T10p DIFFOUT_T10p J17 DQ2T DQ1T7A VREFB7AN0 IO CLK11n DIFFIO_RX_T9n DIFFOUT_T9n H157A VREFB7AN0 IO DIFFIO_TX_T10n DIFFOUT_T10n K16 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T11p DIFFOUT_T11p C15 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T12p DIFFOUT_T12p G15 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T11n DIFFOUT_T11n B15 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T12n DIFFOUT_T12n F14 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T13p DIFFOUT_T13p H14 DQS2T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T14p DIFFOUT_T14p B137A VREFB7AN0 IO DIFFIO_RX_T13n DIFFOUT_T13n J13 DQSn2T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T14n DIFFOUT_T14n A13 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T15p DIFFOUT_T15p E14 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T16p DIFFOUT_T16p J11 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_RX_T15n DIFFOUT_T15n F13 DQ2T DQ1T7A VREFB7AN0 IO DIFFIO_TX_T16n DIFFOUT_T16n H107A VREFB7AN0 IO CLK10p DIFFIO_RX_T17p DIFFOUT_T17p H137A VREFB7AN0 IO DIFFIO_TX_T18p DIFFOUT_T18p G11 DQ3T7A VREFB7AN0 IO CLK10n DIFFIO_RX_T17n DIFFOUT_T17n G137A VREFB7AN0 IO DIFFIO_TX_T18n DIFFOUT_T18n F12 DQ3T7A VREFB7AN0 IO DIFFIO_RX_T19p DIFFOUT_T19p D13 DQ3T7A VREFB7AN0 IO DIFFIO_TX_T20p DIFFOUT_T20p B12 DQ3T7A VREFB7AN0 IO DIFFIO_RX_T19n DIFFOUT_T19n C13 DQ3T7A VREFB7AN0 IO DIFFIO_TX_T20n DIFFOUT_T20n A12 DQ3T7A VREFB7AN0 IO DIFFIO_RX_T21p DIFFOUT_T21p H11 DQS3T7A VREFB7AN0 IO DIFFIO_TX_T22p DIFFOUT_T22p L87A VREFB7AN0 IO DIFFIO_RX_T21n DIFFOUT_T21n G12 DQSn3T7A VREFB7AN0 IO DIFFIO_TX_T22n DIFFOUT_T22n K9 DQ3T7A VREFB7AN0 IO DIFFIO_RX_T23p DIFFOUT_T23p D12 DQ3T7A VREFB7AN0 IO DIFFIO_TX_T24p DIFFOUT_T24p C11 DQ3T7A VREFB7AN0 IO DIFFIO_RX_T23n DIFFOUT_T23n E12 DQ3T7A VREFB7AN0 IO RZQ_2 DIFFIO_TX_T24n DIFFOUT_T24n B118A VREFB8AN0 IO CLK9p DIFFIO_RX_T25p DIFFOUT_T25p G108A VREFB8AN0 IO DIFFIO_TX_T26p DIFFOUT_T26p L7 DQ4T8A VREFB8AN0 IO CLK9n DIFFIO_RX_T25n DIFFOUT_T25n F108A VREFB8AN0 IO DIFFIO_TX_T26n DIFFOUT_T26n K7 DQ4T8A VREFB8AN0 IO DIFFIO_RX_T27p DIFFOUT_T27p J7 DQ4T8A VREFB8AN0 IO FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB DIFFIO_TX_T28p DIFFOUT_T28p H8 DQ4T8A VREFB8AN0 IO DIFFIO_RX_T27n DIFFOUT_T27n J8 DQ4T8A VREFB8AN0 IO FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn DIFFIO_TX_T28n DIFFOUT_T28n G8 DQ4T8A VREFB8AN0 IO DIFFIO_RX_T29p DIFFOUT_T29p J9 DQS4T8A VREFB8AN0 IO DIFFIO_TX_T30p DIFFOUT_T30p A10

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List F23 Page 22 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel F484 DQS for X8 DQS for X16

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

8A VREFB8AN0 IO DIFFIO_RX_T29n DIFFOUT_T29n H9 DQSn4T8A VREFB8AN0 IO DIFFIO_TX_T30n DIFFOUT_T30n A9 DQ4T8A VREFB8AN0 IO DIFFIO_RX_T31p DIFFOUT_T31p B10 DQ4T8A VREFB8AN0 IO DIFFIO_TX_T32p DIFFOUT_T32p A5 DQ4T8A VREFB8AN0 IO DIFFIO_RX_T31n DIFFOUT_T31n C9 DQ4T8A VREFB8AN0 IO DIFFIO_TX_T32n DIFFOUT_T32n B58A VREFB8AN0 IO CLK8p,FPLL_TL_FBp DIFFIO_RX_T33p DIFFOUT_T33p E108A VREFB8AN0 IO DIFFIO_TX_T34p DIFFOUT_T34p B6 DQ5T8A VREFB8AN0 IO CLK8n,FPLL_TL_FBn DIFFIO_RX_T33n DIFFOUT_T33n F98A VREFB8AN0 IO DIFFIO_TX_T34n DIFFOUT_T34n B7 DQ5T8A VREFB8AN0 IO DIFFIO_RX_T35p DIFFOUT_T35p A8 DQ5T8A VREFB8AN0 IO DIFFIO_TX_T36p DIFFOUT_T36p C6 DQ5T8A VREFB8AN0 IO DIFFIO_RX_T35n DIFFOUT_T35n A7 DQ5T8A VREFB8AN0 IO DIFFIO_TX_T36n DIFFOUT_T36n D6 DQ5T8A VREFB8AN0 IO DIFFIO_RX_T37p DIFFOUT_T37p E9 DQS5T8A VREFB8AN0 IO DIFFIO_TX_T38p DIFFOUT_T38p D78A VREFB8AN0 IO DIFFIO_RX_T37n DIFFOUT_T37n D9 DQSn5T8A VREFB8AN0 IO DIFFIO_TX_T38n DIFFOUT_T38n C8 DQ5T8A VREFB8AN0 IO DIFFIO_RX_T39p DIFFOUT_T39p G6 DQ5T8A VREFB8AN0 IO DIFFIO_TX_T40p DIFFOUT_T40p F7 DQ5T8A VREFB8AN0 IO DIFFIO_RX_T39n DIFFOUT_T39n H6 DQ5T8A VREFB8AN0 IO DIFFIO_TX_T40n DIFFOUT_T40n E79A MSEL0 MSEL0 L69A CONF_DONE CONF_DONE K69A MSEL1 MSEL1 J69A nSTATUS nSTATUS H59A nCE nCE G59A MSEL2 MSEL2 A29A MSEL3 MSEL3 E59A nCONFIG nCONFIG A49A MSEL4 MSEL4 F39A GND C5

GND P2GND AB19GND AB14GND AB9GND AB2GND AB1GND AA11GND AA6GND AA4GND AA3GND Y18GND Y5GND Y2GND Y1GND W4GND W3GND V22GND V17GND V12GND V7GND V4GND V2GND V1GND U9GND U5GND U4GND U3GND T21GND T16GND T2GND T1GND R13GND R3GND P10GND P4GND P1GND N22GND N17GND N15

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List F23 Page 23 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel F484 DQS for X8 DQS for X16

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

GND N13GND N11GND N7GND N5GND N3GND M14GND M12GND M10GND M4GND M2GND M1GND L21GND L15GND L13GND L11GND L5GND L3GND K14GND K12GND K10GND K8GND K4GND K2GND K1GND J20GND J15GND J5GND J3GND H22GND H12GND H7GND H4GND H3GND H2GND H1GND G19GND G9GND G4GND G3GND F16GND F6GND F5GND F2GND F1GND E13GND E4GND E3GND D20GND D10GND D5GND D2GND D1GND C17GND C4GND C3GND B14GND B9GND B2GND B1GND A21GND A11VCC N4VCC P15VCC P13VCC P11VCC P3VCC N14VCC N12VCC N10VCC M15VCC M13

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List F23 Page 24 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel F484 DQS for X8 DQS for X16

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

VCC M11VCC L16VCC L14VCC L12VCC L10VCC L4VCC K15VCC K13VCC K11VCC K5VCC K3VCC J16VCC J14VCC J12VCC J10VCC J4DNU B3DNU B4DNU E17DNU L9VCCPGM V8VCCPGM R19VCCPGM F8VCCBAT A3VCCIO2A D4VCCIO2A Y4VCCIO2A R1VCCIO2A J1VCCIO3A T6VCCIO3A Y8VCCIO3B T11VCCIO3B Y13VCCIO3B W10VCCIO3B R8VCCIO4A U19VCCIO4A AA21VCCIO4A AA16VCCIO4A W20VCCIO4A W15VCCIO4A U14VCCIO5A P20VCCIO5A R18VCCIO5B M19VCCIO5B K18VCCIO7A A16VCCIO7A H17VCCIO7A G14VCCIO7A F21VCCIO7A F11VCCIO7A E18VCCIO7A D15VCCIO7A C22VCCIO7A C12VCCIO7A B19VCCIO8A A6VCCIO8A G7VCCIO8A E8VCCIO8A C7VCCPD1A2A E1VCCPD1A2A R2VCCPD1A2A J2VCCPD3A W6VCCPD3B4A W17VCCPD3B4A W14VCCPD3B4A W12VCCPD3B4A W11VCCPD5A P21VCCPD5B N18VCCPD5B M17VCCPD7A8A D16VCCPD7A8A E11

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Pin List F23 Page 25 of 26

Bank Number

VREF Pin Name/Function Optional Function(s) Configuration Function Dedicated Tx/Rx Channel

Emulated LVDS Output Channel F484 DQS for X8 DQS for X16

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1

Note (1)

VCCPD7A8A D14VCCPD7A8A D8VCCPD7A8A C10

2A VREFB2AN0 VREFB2AN0 W13A VREFB3AN0 VREFB3AN0 Y73B VREFB3BN0 VREFB3BN0 Y124A VREFB4AN0 VREFB4AN0 AB165A VREFB5AN0 VREFB5AN0 R205B VREFB5BN0 VREFB5BN0 L207A VREFB7AN0 VREFB7AN0 C148A VREFB8AN0 VREFB8AN0 B8

NC Y6NC V11NC J22NC J21NC H21NC H20NC G22NC G21NC G20NC F22NC F20NC F19NC F18NC E22NC E21NC E20NC E19NC D22NC D21NC D19NC C21NC C20NC C19NC C18NC B22NC B21NC B20NC B18NC B17NC A22NC A20NC A19NC A18NC A17RREF_TL A1VCCA_FPLL M3VCCA_FPLL T3VCCA_FPLL T5VCCA_FPLL F4VCCA_FPLL U18VCCA_FPLL H19VCC_AUX E6VCC_AUX D11VCC_AUX D18VCC_AUX W18VCC_AUX W13VCC_AUX W7

Note:(1) For more information about pin definition and pin connection guidelines, refer to theCyclone V Device Family Pin Connection Guidelines.

PT-5CEBA4-1.1Copyright © 2012 Altera Corp. Revision History Page 26 of 26

Version Number Date Changes Made1.0 9/20/2012 Initial release.1.1 10/5/2012 Removed nPERST* pins because Cyclone V E devices do not support PCIe interface.

Pin Information for the Cyclone® V 5CEBA4 DeviceVersion 1.1