Physical stuff (20 mins)C2S2 Workshop 7/28/06

Clive Bittlestone TI FellowNagaraj NS DMTS,

Roger Griesmer SMTSCarl Vickery SMTS

Gopalarao Kadamati MGTS

Texas Instruments

© Texas Instruments 2004,2005,2006

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Introduction

There has been a lot of interesting DFM discussion over the last few years.

EDA vendors are delivering and developing tools/flows Academia is participating.. Designers are working out methodology. Fabs ( physics/equipment vendors) are driving changes in rules

and models to design. Fabs are working very hard on material science. System level designers are starting to wake up as well.

Long distance interconnect on die is struggling to scale Full synchronous chips are going to be a thing of the past.

Everyone seems to be lending a hand…

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Overview

Includes TI material from previous DAC, ISSCC, IEDM, ESSDERC

Thickness Shapes Rules and layout styles Stress Overlay

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Why Fill ?

Manufacturing issues without fill CMP uniformity open, shorts, flakes. Trench fill, seam formation density issues. Mask Chip temp

Design Issues without fill Thickness variation within die can be the full process range and

beyond (open/shorts) Design will have to run CMP model flow and Thickness aware parasitic extracts.

Realistic design will have to use fill…. need to minimize electrical impact Need to minimize parametric yield impact. Need to minimize data volume/runtime.

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Many needs come together

Fill MethodologyFAB

Digital Design

Modeling

FA/Fib

Data explosion

RET-OPC/SRAF

Analog/RF

Runtime explosion

Electrical impact

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How should we Fill ? Array styles, multi-pass/size

Density map, lookup, multi pass.

Fill shape/size variants…

Model based…CMP only may not be enough. Cmp, Etch, Fill, Trench depth ? ILD, IMD…? , do we need Multi-layer film models ?

Hybrid styles of fill.

Via fill variants. , array, common area, pre defined, power connected..

Timing aware ( critical path or sensitive & close to critical) SSTA / VA extract engine inputs.

Power aware ( activity/load aware)

OPC friendly..

Layer to layer cumulative aware…

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No fill = full fab range within die !

Fill methodology 1Timing impactDensity clean

Fill method 14Low impactNot D-clean

PCD range (Thickness)

45nm Metal4 thickness examples

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Timing Impact (non-stat)

Ref AType 1Type 3Type 7

Overkill Density map

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SO…..?

Model based fill may not be needed….yet.

Hybrid fill can meet needs.

Design may not need to run CPM sim an thickness aware parasitic extraction…. yet.

Cmp/etch/fill simulation needs to be used to calibrate hybrid fill.

Analog designers need to own their own fill and become fill aware.

Cell context is critical for thickness analysis. (sparse fill) Nightmare for chip level (which timing model to use..? Better to control context range from day 1.

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FEOL items

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Poly Flare & Active Flare

Poly

Active

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Poly Flare

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Active Flare

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90nm Poly/Active example

Unstructured layout•Wrong way gate•No pitch restrictions•Routing in Active and poly•Many Active jogs•Poly flare•Active flare•No 45 gates.

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Weak structure No pitch control No routing in Active Flare control rules Vertical orientation Jog control

65nm Poly/Active example

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Alternate style 3 Active/Poly example

Semi structured layout•No wrong way gate•Pitch restrictions•No Routing in Active•Significant jogs control•Big flare rules•Line end rules clear.

Semi structured layout•Context becoming more predictable.•Some chip level DFM may be avoided…•Cell level DFM still useful ?•Can we still compose/place without consideration ?

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90nm Metal

Unstructured layoutLow impact Line end rulesLow impact Wide metal rulesLow impact min area rules

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Unstructured Line end rules Min area rules worse Metal bin rules worse. 2 directions

Model based drc , hotspot and fixups

Contour based parasitic extraction ?

Process corner extraction? Nom, +-DOF/ -+Dose (9) Don’t double count in spice

models.

65 nm Metal/cont

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Another alternate style Metal/cont

UnstructuredExtensive use in both directionsLarge line end rules expensiveWide metal rules expensiveSome pitch control ?Min area rules expensiveShape control rules.Cut density….

Difficult to manufacture..OPC Ambit is +- several rows of cells..

Gate level abstraction/composeis in question here…

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Metal …•Pinch/bridge sensitivity must be identified during technology setup•Pushing beyond process window to fail points can indicate margin to fail•Context is important – How to be context insensitive ?

•Change layout for DFM robust…•Modify process ?•Make cells robust without growing them….

•Avoid/minimize need to fix at chip level.

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Scary metal -CMU brick style

Extreme structureUnidirectional metalRestricted pitch.Line end rules very expensiveWide metal rules very expensiveGrid cont, via1 Grid via2Process entitlement scale very difficult

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STRESS

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Active Overlap of Gate (AOG,LOD) stressWhat : Idrive for a fixed gate L varies as a function of active overlap of gate.Why: Physical stress changes mobility in the channel. This type of stress is a function of active overlap of gate..

There are other types of stress to consider as well that are sensitive to gate pitch, poly turns, orthogonal poly, contact type/location, tensile../compressive …..etc…

PMOS NMOSIDSAT

AOG

IDSAT

AOG

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Process Misalignment Modeling

Overlay/misalignment is struggling to scale.

Misalignment between layers in any direction.( stat distribution)

Cells are more sensitive to alignment in certain directions.

Impacts several important parameters.

Rcont, Cgd, AS, AD, Cgs,…

Compound this with LOD , contact stress, liner stress damage as well….

Internal nodes (light load) in asymmetric layout common in ASIC libraries can be sensitive to this.

Also compounds metal pull back (R via)

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Contact misalignment impact on timing. (90nm)Cell Delay vs Contact Misalignment

SR50; FanOut=5; Interconnect Load=5SL; W_125_1.17_maxc

-1.00%

-0.50%

0.00%

0.50%

1.00%

1.50%

2.00%

2.50%

3.00%

-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40

Contact Misalignment in X direction (nm)

Del

ta D

elay

(%)

IV110IV170IV1W0NA210

Asymmetric

Symmetric

Not including stress or active misalignmentmuch worse for small loads, think inside a flop...

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General alignment

Single cell

Mirrored cellL-R misalign = asymmetric skew

Mirrored And flippedcells

L-R/U-D misalign = asymmetric skew