RTL SYNTHESIS

RTL Code Gate-Level Netlist

FLOORPLAN

Die Size, Core Size, Aspect Ratio (H/W), IO Pads placement, Macro placement, IO to Core boundary offset, Std. cell rows orientation, etc.

PARTITION

Divide the design as per their logical hierarchy in the gate-level netlist

CHIP FINISHING Antenna Fixing, Redundant Via Insertion, Filler Cells, Metal Fillers, etc.

ROUTING

Timing and Congestion driven, fixing the DRC violations.

CLOCK TREE SYNTHESIS Check the preCTS clock structure and define the optimum START, EXCLUDE,

IGNORE and STOP pins in the clock network. Then tool does Gate Sizing, relocation, etc. for hold fix….

POWER NETWORK SYNTHESIS Give power constraints and use the tool to make PAD Rings, Core Rings, block

rings, PG Straps and power rails for std. cells.

PLACEMENT Preplace OPT, HFNS, placement of standard cells, IPO, and usage of

techniques and guidelines to have acceptable congestion and SETUP time…

RC EXTRACTION

SIGN OFF

PHYSICAL VERIFICATION

SIGN OFF

FORMAL

VERIFICATION

SIGN OFF

GDSII

Timing Analysis

and SI Analysis

SIGN OFF

WNS

TNS

DRVs

POWER

CONGE-

STION

DRCs

DFM

Design Compiler

I

C

C

O

M

P

I

L

E

R

FORMALITY

ICV

PRIMETIME

S T A R RCXT