phdl presentation oct 2011
TRANSCRIPT
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PHDLPRINTED CIRCUIT BOARD HARDWARE DESCRIPTION
LANGUAGE
Brent Nelson, Brad Riching, Richard Black
Dept. of Electrical and Computer Engineering
Brigham Young University
October 25, 2011
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Acknowledgements
• Pete Dudley – Sandia– Ideas, motivation, and passion for this project
• Wes Landaker - Sandia– Ideas, language design, compiler consulting
• Sandia Management– Funding
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Overview
• Who are we?• What is PHDL? (a very short intro)• Examples of PHDL
– Example board designs• Language and grammar• Tool flow
• What is PHDL? (more in-depth)– Why textual input?
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Who Are We?
• Dr. Brent Nelson– Brigham Young University, Dept. of Electrical
and Computer Engineering
• Brad Riching– MS Student in Computer Engineering– BS in Electrical Engineering, Brigham Young
University, 2010
• Richard Black– Undergraduate in Computer Engineering,
Brigham Young University
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What is PHDL?
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Schematic Capture produces netlist
PCB Layout interprets netlist
Bill of Material,
other ancillary
data
netlist
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What is PHDL?
6
Schematic Capture produces netlist
PCB Layout interprets netlist
PHDL Source Code
PHDL compiler
Bill of Material,
other ancillary
data
netlist
netlis
t
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What is PHDL? (a very short intro)
• An HDL for PC Boards – Hardware Description Language– For schematic entry (not layout)
• Similar to HDLs for IC and FPGA design– Verilog, VHDL, etc.
• Goal == significantly increase:– Productivity– Collaboration– Reuse
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Why PHDL? (the short version)
1. Automation & productivity– Iteration, hierarchy, ERC/DRC
2. Collaboration– SCCS (source code control system)
• Shared repository for designs and part libraries• Design versions, change tracking/documentation• Diff, revert
3. Textual IDEs and tools– Templates, auto-completion, search and
replace, library reuse
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High Pin Count Devices - FPGAs
9
How much of this schematic is meaningful?
• Most circuit context is absent.
• Many pins map to devices on other pages.
• Larger devices mustbe split across multiple pages
• Schematics don’t scale well.
• HDL’s do!
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Trivial Example
• We’ll illustrate some of the features of PHDL with an example:
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Trivial Example
• We’ll illustrate some of the features of PHDL with an example:
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Trivial Example
• We’ll illustrate some of the features of PHDL with an example:
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Trivial Example
• We’ll illustrate some of the features of PHDL with an example:
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Trivial Example
• We’ll illustrate some of the features of PHDL with an example:
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Trivial Example
• We’ll illustrate some of the features of PHDL with an example:
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Trivial Example
• We’ll illustrate some of the features of PHDL with an example:
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Trivial Example
• We’ll illustrate some of the features of PHDL with an example:
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Trivial Example
• We’ll illustrate some of the features of PHDL with an example:
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PHDL Example Design
19
design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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PHDL Example Design
20
design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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PHDL Example Design
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design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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Creating a Design
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device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2};end device;
R? M0805
1
2
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Creating a Design
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device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2};end device;
R? M0805
1
2
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Creating a Design
24
device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2};end device;
R? M0805
1
2
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PHDL Example Design
25
design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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PHDL Example Design
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design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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PHDL Example Design
27
design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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Creating a Design
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device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “SA08-21”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17};end device; 2
15
13
11
5
3
14
10
4
12
17
SA08-21
LD?
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Creating a Design
29
device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “SA08-21”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17};end device; 2
15
13
11
5
3
14
10
4
12
17
SA08-21
LD?
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PHDL Example Design
30
design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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PHDL Example Design
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design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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PHDL Example Design
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design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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Creating a Design
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inst source of Battery is pos = vcc; neg = gnd;end inst;
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Creating a Design
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inst source of Battery is pos = vcc; neg = gnd;end inst;
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Creating a Design
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inst source of Battery is pos = vcc; neg = gnd;end inst;
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PHDL Example Design
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design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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Creating a Design
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inst segment of SevenSeg is segments = segs; anode = <vcc>;end inst;
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Creating a Design
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inst segment of SevenSeg is segments = segs; anode = <vcc>;end inst;
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Creating a Design
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inst segment of SevenSeg is segments = segs; anode = <vcc>;end inst;
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PHDL Example Design
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design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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Creating a Design
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inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs;end inst;
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Creating a Design
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inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs;end inst;
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Creating a Design
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inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs;end inst;
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PHDL Example Design
44
design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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Creating a Design
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inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd;end inst;
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Creating a Design
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inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd;end inst;
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Creating a Design
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inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd;end inst;
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Creating a Design
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inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd;end inst;
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PHDL Example Design
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design ssControl is device Resistor is attr refPrefix = “R”; attr pkg_type = “M0805”; pin a = {1}; pin b = {2}; end device; device Switch is attr refPrefix = “SW”; attr pkg_type = “MS243”; pin a = {1}; pin b = {2}; end device; device Battery is attr refPrefix = “G”; attr pkg_type = “1V60R”; attr value = “9V”; pin pos = {2}; pin neg = {1}; end device; device SevenSeg is attr refPrefix = “LD”; attr pkg_type = “MS243”; pin[1:8] segments = {2,15,13,11, 5,3,14,10}; pin[1:3] anode = {4,12,17}; end device;
net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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PHDL Example Design
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design ssControl is include “parts.phdl”; net gnd, vcc; net[1:8] segs, r2sw;begin inst source of Battery is pos = vcc; neg = gnd; end inst; inst segment of SevenSeg is segments = segs; anode = <vcc>; end inst; inst(1:8) swArray of Switch is combine.a = r2sw; combine.b = segs; end inst; inst(1:8) rArray of Resistor is newattr value = “120”; combine.a = r2sw; each.b = gnd; end inst;end design;
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How PHDL Works
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Lexer ParserPHDL source
Tree Parser
Abstract Syntax Tree (AST)
Analyzer / Generator
Command line switches
Output files
ANTLR framework
• Netlist• Bill of Materials• Component List• Layout Directions• XML• Tool-specific Scripts
~/user/brad/phdl/projects$java phdl.Compile <file_name>.phdl [switches]
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Targeted Design Flows
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EAGLE PCB
Mentor Graphics PADS
AD9739 High Speed DAC FMC board – Pete Dudley
FPGA-based Motor Controller - BYU
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BYU Proof of Concept Board
FPGA-based motor controller (2-axes)– Spartan3 400K 144-pin QFP implements:
• 32-bit position, vel. and accel. registers per axis• Programmable PID filters, sampling intervals• Trapezoidal velocity profile generators• Packet router over RS232 to host PC application
– Supporting hardware• 500+ CPR encoder feedback resolution• PWM brushless and brushed motor drives• The usual JTAG, Flash ROM, GPIO, etc.
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Motor Controller Board
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RS232 Host Application
MOTOR DRIVERS
Single Axis Block Diagram
FPGA VHDL Hardware Outside FPGA
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Motor Controller Board
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Final Layout in EAGLE
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Motor Controller Board
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Back From Manufacturing
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Motor Controller BoardAssembled
Top Bottom
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Motor Controller BoardFirst PCB Built using PHDL
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Motor Controller Board
FPGA / SRAM
Power Supply12VDC IN:To 5V, 3.3V, 2.5V, 1.2V
RS232
JTAG
Motor Power 58VDC MAX
Brushless Drive (x2)
Brushed Drive (x2)
Encoder Feedback
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Motor Controller Board
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Host Application Interface (C#)
PositioningCommands
Reporting Commands
Serial Config
Internal State Registers
Raw Data Monitoring
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Automatic Device Generation
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library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity fpga is
port(
clk : in std_logic;
rst : in std_logic;
-- RS232 serial ports
rxd : in std_logic;
txd : out std_logic;
rxd_a : in std_logic;
txd_a : out std_logic;
-- 12-bit DAC
sclk : out std_logic;
sync : out std_logic;
sdata : out std_logic
data : out std_logic_vector(7 downto 0)
.
.
.);
end entity fpga;
Synthesis, PAR,csv2phdl
#fpga.ucf
LOC “clk” = P52;LOC “rst” = P40:LOC “rxd” = P47;LOC “rxd_a” = P41;...
Location Constraints
FPGA VHDL Design
device fpga isattr refPrefix = "U";attr pkg_type = "tq144";attr mfgr = "XILINX";attr partNumber = "xc3s400-4tq144";
// User I/O pins.pin clk = {P52};pin rst = {P40};pin rxd = {P47};pin rxd_a = {P41};pin txd = {P46};pin txd_a = {P44};pin sclk = {P86};pin sdata = {P87};pin sync = {P85};pin[7:0] data = {P23,P21,P20,P18...};...
end;
PHDL Device Declaration
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Automatic Device Generation
Automated FPGA Device Declaration from HDL
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fpga.vhdlfpga.ucf
Synthesis, PAR
fpga.csv fpga.phdlcsv2phdl
Revisions
design myDes is
include “fpga.phdl”;
begin…end design;
PHDL Source Code
PHDL Device
Declaration
HDL
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Motor Controller Board
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FPGA Instanceinst fpga_inst of fpga is
newattr libName = "xilinx_devices";
partnumber = "122-1717-ND";newattr supplier = "DIGI-
KEY";newattr cost = "21.95";
// Signal pins from FPGA design.
clk = clk;rst = rst;rxd = rxd;rxd_a = rxd_a;txd = txd;txd_a = txd_a;sclk = sclk;sdata = sdata;sync = sync;data = data;
.
.
.
end;
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Motor Controller Board
• ~1200 lines of PHDL (25 pages of code)• 30 device declarations
– 6 library files
• 672 nets
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Motor Controller Board
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QUANTITY NAME REFDES PKG_TYPE COST LIBNAME MFGR PARTNUMBER SUPPLIER1 top_tq144 U1 tq144 21.95 xilinx_devices XILINX 122-1717-ND DIGI-KEY
27 C0603 C1; C2; C3; C4; C5; C6; C7; C8; C9; C10; C11; C12; C21; C22; C23; C24; C36; C37; C38; C39; C40; C41; C42; C43; C45; C46; C47 C0603MP 0.12 rc-master-smd TDK 445-1313-1-ND DIGI-KEY18 C0603 C13; C14; C15; C16; C17; C18; C19; C20; C25; C26; C27; C28; C44; C63; C64; C65; C66; C94 C0603MP 0.08 rc-master-smd TDK 445-1311-1-ND DIGI-KEY11 CP_1206MP/T C29; C30; C31; C32; C33; C34; C35; C85; C86; C87; C92 C1206MP/T 0.47 rc-master-smd AVX 478-1655-1-ND DIGI-KEY
1 dipswitch S1 DS-08 1.14 switch-dil E-Switch 450-1366-ND DIGI-KEY27 R0603 R1; R2; R3; R4; R5; R6; R7; R8; R9; R10; R11; R12; R13; R14; R15; R16; R25; R26; R27; R28; R32; R65; R66; R67; R68; R69; R70 R0603MP 0.02 rc-master-smd Panasonic P4.7KGCT-ND DIGI-KEY
8 LD0603 LD7; LD6; LD5; LD4; LD3; LD2; LD1; LD0 0603MP 0.15 led OSRAM 475-2506-1-ND DIGI-KEY9 R0603 R17; R18; R19; R20; R21; R22; R23; R24; R83 R0603MP 0.02 rc-master-smd Panasonic P390GCT-ND DIGI-KEY2 RAM256KX16 U2; U3 TSOPII44 6.6 memory-issi ISSI 706-1035-ND DIGI-KEY1 OSC_50MHZ X1 SM77H 2.63 crystal Abracon 535-9330-1-ND DIGI-KEY2 TL1105T S2; S3 TL1105T 0.58 switch E-Switch EG1827-ND DIGI-KEY3 HDR_1X6 J1; J2; J7 1X06/90 pinhead
Bill of Materials (CSV)
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The Group Construct
66
group "SWITCHES" isinst fpga_switches of
dipswitch isa = <vcco>;b = sw_res;
end;
inst(7:0) sw_pulldown of R0603 is
value = "4.7k";
partNumber = "P4.7KGCT-ND";
combine.a = sw_res;
each.b = gnd;end;
inst(7:0) sw_lim of R0603 is
value = "4.7k";
partNumber = "P4.7KGCT-ND";
combine.a = sw_res;
combine.b = sw;
end;end;
Group name
Initial Arrayed Layout
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Why PHDL? (the longer version)
• Open format– Any text tools can read and manipulate– Design files do not get corrupted– Easily shared, exchanged, emailed– Design files forward/backward compatible
across tool revisions
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Why PHDL?
• IDEs– Templates and auto completion– Color syntax highlighting– Search, search-and-replace– Scripting
• Example: Eclipse
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Why PHDL?
• SCCS (source code control system)– Shared repository for designs and part
libraries– Design versions, change
tracking/documentation– Diff, revert
• Collaboration• Reusability• Cross probing
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Why PHDL?
• Hierarchy• Focus on functionality rather than looks of
schematic• Easy to mis-wire in graphics
– Rats nests– Missed endpoints– High pin count packages span multiple pages– Dangling wires across schematic pages
• Non-electrical parts trivial to add
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Why PHDL?
• Automation– Higher level constructs– Arrays, hierarchy– Refdes handling– DRC available to user due to open format– Lint-like tools easily written
• Automatic generation of design files– Example: device generation from UCF file for
FPGAs
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What’s Next?
• PHDL 2.0– Hierarchy support– Pin directions and DRC– IDE Eclipse plugin
• Instance template generator• Syntax coloring• Content assist• Hierarchy browser• Refactoring
– Additional tool flows
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