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Phase Noise Simulation and Modeling of ADPLL by Modeling of ADPLL by SystemVerilog Tingjun Wen Integrated Device Technology Tad Kwasniewski Carleton University 1 Sept 2008

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Page 1: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by

SystemVerilogy gTingjun Wen

Integrated Device TechnologyTad Kwasniewski Carleton University

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Sept 2008

Page 2: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Motivations

• Integrate the phase noise behavioral i l ti ith th i it l l d isimulation with the circuit level design

• Find a better random number generator ith d t ti ti l ti t kwith good statistical properties to make

the phase noise simulation more accurateaccurate

• Make the phase noise simulation fasterU th h i b h i l• Use the phase noise behavioral simulation to explore new ADPLL architectures with lower phase noise

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architectures with lower phase noise

Page 3: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Behavioral Simulation LanguagesBehavioral Simulation Languages

LANGUAGE EVENT-DRIVEN

Matlab/Simulink Function callsMatlab/Simulink Function calls

Verilog/VHDL Intrinsic

V il AMS/VHDL AMS i iVerilog-AMS/VHDL-AMS Intrinsic

SystemVerilog Intrinsicy g

SystemC/AMS C++ Class Library

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Page 4: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

SystemVerilog + C Language• Direct programming interface (DPI)

Can call any standard C functions directly– Can call any standard C functions directly– Exporting Verilog tasks and functions to C

• Example• Examplenoise.c:

double flicker(double stddev, double *pflicker);

noise.v:import "DPI-C" function real flicker(input real stddevimport DPI C function real flicker(input real stddev,

output real pflicker);always @(posedge clock) begin

period = period + flicker(flicker stddev pflicker);

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period = period + flicker(flicker_stddev, pflicker);end

Page 5: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Noise TerminologiesNoise Terminologies

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Page 6: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Spectrum vs DistributionSpectrum vs Distribution

FFT Spectrum Distribution

White (0dB/dec) UniformWhite (0dB/dec) UniformWhite (0dB/dec) Normal

Pink (-10dB/dec) ?

Red (-20dB/dec) ?Red ( 20dB/dec) ?

Infrared (-30dB/dec) ?

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Page 7: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Noise Generator Hierarchyy•Mersenne twister*•Ranlux algorithm•Tausworthe•LFSR•GFSRGFSR

Uniform White Noise•Inverse transform•Box-Muller*•Ziggurat

•Filter fitting Voss McCartne *

Normal White Noise Pink Noise

Ziggurat•Marsaglia

•Voss McCartney*

Red Noise Infrared Noise

Integral* Integral*

7* Used by this paper

Red Noise Infrared Noise

Page 8: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Uniform White Noise GeneratorUniform White Noise Generator

• Mersenne twister generator• Mersenne twister generator• have a period of (2^19937−1)• there is negligible serial correlation• Have good statistical randomness• Have good statistical randomness• Source code available

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Page 9: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Normal White Noise GeneratorNormal White Noise Generator

• Central limit theorem• Central limit theorem• Box-Muller algorithm• Generate Gaussian random variable

from uniform distributionfrom uniform distribution• Simple to implement

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Page 10: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Normal White Noise GeneratorNormal White Noise Generator

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Page 11: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Correlated Pink Noise Generator*Correlated Pink Noise Generator

• Stochastic Voss-McCartney variant• Popular in the music industryPopular in the music industry• Each data needs no more than 2

d b tirandom numbers generation operations

• It is very efficient

11*http://home.earthlink.net/%7Eltrammell/tech/newpink.htm

Page 12: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Correlated Pink Noise Generator*Correlated Pink Noise Generator

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Page 13: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Higher Order Noise GeneratorsHigher Order Noise Generators

Si il t th i h i th• Similar to the noise shaping theory developed from Sigma-Delta modulator

∆ Differentiation (+20dB/dec) Σ Integration (- 20dB/dec)

• Σ White noise Red (-20dB/dec) • Σ Pink noise Infrared (-30dB/dec)

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Σ Pink noise Infrared ( 30dB/dec)

Page 14: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Higher Order Noise Generators

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Page 15: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

ADPLL Architecture

module adpll (fref, M, fdiv, fout, rst_n);input fref rst n fdiv;input fref, rst_n, fdiv;input [`div_width-1:0] M;output fout;pfd PFD (.fref(fref), .fdiv(fdiv), .up(up), .dn(dn), .rst_n(rst_n));dco DCO (.up(up), .dn(dn), .fdiv(fdiv), .fout(fout));div DIV (.fin(fout1), .M(M), .fdiv(fdiv), .rst n(rst n));

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div DIV (.fin(fout1), .M(M), .fdiv(fdiv), .rst_n(rst_n));endmodule

Page 16: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Phase Frequency Detectorq y‘ i n c l u d e ” a d p l l . vh ”

d l fd ( f f f d i d t )module pfd ( f r e f , f d i v , up , dn , r s t n ) ;output up , dn ;input f r e f , f d i v , r s t n ;preg up , dn ;wire p f d r s t ;always @( posedge f r e f or posedge p f d r s t) beginalways @( posedge f r e f or posedge p f d r s t) begini f ( p f d r s t ) up <= 0 ; e l s e up <= 1 ;

endl @( d f d i d f d t) b ialways @( posedge f d i v or posedge p f d r s t) begini f ( p f d r s t ) dn <= 0 ; e l s e dn <= 1 ;

end

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a s s i g n p f d r s t = ˜ r s t n | ( up & dn ) ;endmodule

Page 17: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

DCO with Integrated LPFDCO with Integrated LPF

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Page 18: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

DCO with Integrated LPFg

always @( up or dn ) begin case ({ up , dn })2 ’ b01 : I = I − 1 ; 2 ’ b10 : I = I + 1 ; d e f a u l t : ;

endcaseendcaseP [ 0 ] = up ˆ ˜ dn ; P [ 1 ] = up & ˜ dn ;

endalways @( posedge f d i v ) C t r l <= ( ‘Kp P ) + ( ‘Ki I ) ;always @( posedge f d i v ) C t r l <= ( Kp P ) + ( Ki I ) ;always beginp e r i o d = 1 . 0 / ( ‘ f 0 d c o + ‘Kdco C t r l );p e r i o d = p e r i o d + f l i c k e r (s t d d e v , p f l i c k e r ) ;#( p e r i o d / 1 e −12/2) f o u t = ˜ f o u t ;

end

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end

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Step Response without Noise

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Page 20: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Step Response with Noisep p

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Page 21: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Step Response with NoiseStep Response with Noise

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Page 22: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

Simulated Phase Noise

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Page 23: Phase Noise Simulation and Modeling of ADPLL byModeling ...Phase Noise Simulation and Modeling of ADPLL byModeling of ADPLL by SyygstemVerilog Tingjun Wen Integrated Device Technology

ConclusionsConclusions• Mersenne-Twister Uniform white noise• Box Muller Normal white noise• Box-Muller Normal white noise• Stochastic V-M 1/f pink noise• Integral operation higher order noisesIntegral operation higher order noises• SystemVerilog DPI to integrate with the noise

generator functions written in C languagePh i i l ti t h i f ll• Phase noise simulation techniques successfully applied to a new ADPLL architecture

• Event-driven runs less than 1 minute while SpiceEvent driven runs less than 1 minute while Spice runs by hours or by days

• Design parameters extracted for future transistor level circuit design

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level circuit design

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References• [1] K. Kundert. (2006, Aug.) Predicting the phase noise and jitter of pll based

frequency synthesizers. [Online]. Available:http://www.designersguide.org/Analysis/PLLnoise+jitter.pdf

• [2] J. Zhuang, Q. Du, and T. Kwasniewski, “Event-driven modeling and simulation of an digital PLL,” Behavioral Modeling and Simulation Workshop, Proceedings of the 2006 IEEE International, pp. 67–72, Sept. 2006.

• [3] S. Huang, H. Ma, and Z. Wang, “Modeling and simulation to the design of fractional-n frequency synthesizer,” in DATE ’07: Proceedings of the conference onfractional n frequency synthesizer, in DATE 07: Proceedings of the conference on Design, automation and test in Europe. San Jose, CA, USA: EDA Consortium, 2007, pp. 291–296.

• [4] R. Staszewski, C. Fernando, and P. Balsara, “Event-driven simulation and modeling of phase noise of an rf oscillator,” Circuits and Systems I: Regular Papers, IEEE Transactions on [Circuits and Systems I: Fundamental Theory and ApplicationsIEEE Transactions on [Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on], vol. 52, no. 4, pp. 723–733, April 2005.

• [5] M. Matsumoto and T. Nishimura, “Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator,” ACM Trans. Model. Comput. Simul., vol. 8, no. 1, pp. 3–30, 1998.

• [6] L. Tammell. (2006, Jan.) Improvements in the correlated pink noise generator evaluation. [Online]. Available: http://home.earthlink.net/%7Eltrammell/tech/newpink.htm

• [7] J. Zhuang, Q. Du, and T. Kwasniewski, “A 3.3 ghz lc-based digitally controlled oscillator with 5khz frequency resolution,” Solid-State Circuits Conference, 2007.

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oscillator with 5khz frequency resolution, Solid State Circuits Conference, 2007. ASSCC ’07. IEEE Asian, pp. 428–431, Nov. 2007.