perspective on emerging devices and their impact on scaling … · 2010-06-28 · perspective on...

Perspective on Emerging Devices and their Impact on Scaling Technologies

S. Biesemans IMEC, Kapeldreef 75, B-3001 Leuven, Belgium ([email protected])

Abstract

We review and discuss the latest developments in FinFETs as an emerging device and its impact on scaling technologies.

Introduction Transistor scaling has been the major driving force in the semi-

conductor industry for 40 years. The track has been one of many roadblocks and creative solutions. Most FinFET reports focus on devices, here we discuss technology opportunities and challenges.

The microelectronics industry is constantly seeking ways to scale transistor dimensions in order to allow for more transistors on a single chip, to scale down capacitance and to keep the drive current high while the voltage supply is scaled down to reduce power con-sumption. When scaling conventional planar devices below the 65nm node, short-channel effects (SCE) start to dominate over the device performance. Increased gate control is achieved by reducing the gate insulator thickness, by reducing the depth of S/D regions, and by increasing channel doping. All three strategies have major disadvantages: an increase gate leakage, an increase in the parasitic S/D resistance, a compromised carrier mobility and S/D leakage. Another approach to improve gate control over the channel is by using multiple gate devices [1,2]. It is projected that these 3-D de-vice architectures may start to replace planar MOSFETs for specific applications in the 32nm node and beyond [3].

FinFET process Because the 32nm node does not exist yet, FinFETs are built

with existing higher node processes. In this work, we choose to start from a standard 130nm process with an extension towards a 45/32nm seized 6T-SRAM cell.

Fin patterning A typical FinFET process flow is presented in Fig.1. Most of the

work to date is based on SOI substrates [4,5], although bulk FinFETs [6,7] have been reported. An opportunity of SOI substrates is the ability to work with mesa-type active areas due to the insulating nature of the buried oxide (Box) [8]. The opportunity is that one avoids the need for an STI process and enjoys immunity to latch-up. Several challenges exist. A typical test structure for a FinFET is shown in Fig.2. The various fins are connected through the use of a S/D pad. Despite the fact that they are a convenient way of connect-ing the multiple fins, they require sub-resolution resist openings to be printed. The rounding of the resist opening increases the Wfin as Lfin reduces and can be mitigated by advanced illumination condi-tions and OPC (see Fig.3). It can be avoided by strapping the fins with a local interconnect Metal-0 (see Fig.4), at the expense of extra process complexity. From a lithography point of view, the problem of resist corner rounding is the shifted to a fin line shortening, which is believed to be much more manageable by OPC. A second, related issue is the use of advanced illumination conditions, like dipole [9], and their layout restrictions like forbidden pitches and uni-directionality.

As technologies scale sub-45nm, uni-directionality in layout style may be required to help maintaining the lithography process window. FinFETs provide a great opportunity because by nature they favor single direction, CD and pitch, and provide therefore a regular (like DRAM) style layout to make logic circuits. Fig.5 shows a typical 6T-SRAM active areas pattern with 150nm pitch with and w/o OPC correction [9, 10].

Gate patterning The opportunities provided at the fin level create some chal-

lenges at the gate level, mainly due to the extra topography. A first challenge is that, depending on the fin height (Hfin), the process

window for gate etch may shrink significantly. A typical non-optimized process yields poly residues from micro-masking (see Fig.6). One opportunity is the use of the ‘poly etch-back’ process (see Fig.7) leading to a smoother poly-edge preventing any HM micro masking and hence residues.

A second challenge is the CD uniformity as the gate runs over a fin. Fig.8 (top) shows two examples of logic gates indicating the loss of CD control over narrow fins (Wfin<35nm). The opportunity arises from BARC etch optimization combined with ‘topography-dependent OPC’ leading to a much improved process (Fig.8 bottom). A particular challenge is the simultaneous integration of logic and SRAM style circuits in sub-45nm nodes [9], particularly combined with spacer defined fin patterning.

Metal Gate and Vt tuning A major challenge in the case of any narrow active area device,

including multi-gate devices, it the difficulty to tune the threshold voltage by means of channel doping. Extremely high doping concen-trations are needed for narrow-fin devices, exceeding 5e18cm-3, to have any sizeable effect on VT as shown on Fig.9. This raises con-cerns of VT fluctuations due to random dopant distribution, signifi-cant mobility degradation and junction leakage. In addition, the VT of highly doped fins is sensitive to variations in Wfin (Fig.10).

The opportunity lies in effectively making use of double gate ef-fect to control short channel effects (SCE) combined with tune-able metal gates (MG). Undoped channels maximise mobility, sub-threshold slope and Vt control. Ideally one would use a single n-type (or p-type) metal that is selectively tune-able (implant of C, N, F,…) towards p-type (or n-type). Inserted midgap metals like TaN and TiN have been demonstrated on FinFETs [9,11,12,13] as shown in Fig.10. The use of fully silicided (FUSI) gates in FinFETs has been demon-strated [14] and provides MG action with low Vt’s by use of NiSi phase control [15,16] or alloying.

45/32nm circuit aspects FinFETs have been integrated into various SRAM cell seizes

[17,18] down to 0.274um2 [9] using optical litho (Fig.12). The cell concept has been shown to scale below 0.14um2 [19].

For reasons of cell stability and speed, one needs to design proper beta ratios. Opportunities to modulate the beta ratio are choosing different L’s, selectively etching back the Hfin differently over nFET and pFET regions and selecting the right starting sub-strate surface and notch position.

Recently, the use of channel strain to boost drive currents in bulk and SOI technologies have been demonstrated [20,21]. Initial results on FinFETs have been reported [22], but more work is required to match current state-of-the-art CMOS.

Another opportunity, that requires more in depth study, is the po-tential to optimize the technology for [A/um2] rather than the tradi-tional [A/um]. Very high current densities can be achieved by in-creasing the Hfin that may enable different architectures to be opti-mal (eg, BEOL loaded circuits).

References [1] B.Yu, IEDM 2002, p.251 [2] E. Nowak, IEEE Circ&Dev Mag 2004, p.20[3] E. Nowak, IBM J. R&D Vol.46 2002, p.169 [4] F.L. Yang, IEDM 2002, p.255 [5] B. Doyle, Symp.VLSI Tech. 2003, p.133 [6] T. Park, Symp. VLSI Tech. 2003, p.135 [7] S.M. Kim, Symp. VLSI Tech 2005, p.196 [8] F.L. Yang, Symp. VLSI Tech 2004, p.8 [9] L. Witters, Symp. VLSI Tech. 2005, p.106 [10] A. Nackaerts, IEDM 2004, p.269 [11] K. Henson, Symp. VLSI-TSA Tech. 2005, p.136

[12] N. Collaert, Symp. VLSI Tech. 2005, p.108 [13] C. Jahan, Symp. VLSI Tech. 2005, p.112 [14] A. Kottantharayil, Symp. VLSI Tech. 2005, p.198 [15] M. Terai, Symp. VLSI Tech. 2005, p.68 [16] J. Kittl, Symp. VLSI Tech. 2005, p.72 [17] J-H Yang, IEDM 2003, p.23 [18] T. Park, IEDM 2003, p.27 [19] D. Fried, IEDM 2004, p.261 [20] T. Ghani, IEDM 2003, p.978 [21] C.D. Sheraw, Symp. VLSI Tech. 2005, p.12 [22] P. Verheyen, Symp. VLSI Tech. 2005, p.194

• Mesa-type fin pattering • Surface repair + conditioning • Gate deposition + patterning

o 1.4nm HfO2 o 5nm TiN o 100nm polysilicon o 193nm photo, gate etch

• Extension/HALO implant • HDD Spacer • deep S/D implant • Spike anneal • NiSi formation

Fig. 1 Simplified FinFET process flow

Fig. 2 SEM image of a mesa-type active area Fig. 3 Wfin as function of Lfin

Fig. 4 Two different ways of connecting fins, (top) active areas (bottom) local interconnect M0.

Fig. 5 Fin CD for standard process (a) and OPC optimized process (b)

Fig. 6 FinFET after gate etch, (top) with non-optimised etch process, (bottom) with optimized process (etch back)

Fig. 7 Cartoon showing standard (top) and poly etch-back (bottom) process.

Fig. 8 Gate CD variation over fin topography, (top) examples of standard process in logic area, (bottom left and right) optimized process in logic and 0.3um2 SRAM cell

Fig. 9 2D Device simulation result indicating the sentiv-ity of Vt to channel doping for 3 diffferent device archi-tectures and work function.

Fig. 10 Measured nFET Vtlin as function of Wfin for various channel doping levels.

Fig. 11 TEM showing Fin with inserted TiN / HfO2 gate capped with 100nm amorphous-Si.

Fig. 12 Tilted SEM of a 45nm node SRAM cell with FinFETs

© imec 2005

Perspective on Emerging Devicesand

their Impact on Scaling Technologies

S. Biesemans

SSDM 2006

© imec 2005 2SSDM 2005

OutlineOutline

IntroductionIntroduction

Fin patterning, 6TFin patterning, 6T--SRAM cell fabricationSRAM cell fabrication

Gate patterning, MG and Gate patterning, MG and Vt Vt tuningtuning

ConclusionsConclusions

© imec 2005 3SSDM 2005

How it all got started...1947

The Point contact transistorBell Labs

1958The First IC

Texas Insruments

1961The First Planar IC

Fairchild

© imec 2005 4SSDM 2005

MOSFETPlanar processSiN Passivation

LOCOSIon implant

Plasma Etch

SteppersLDD

Silicide

KrF lithoCMP

Extensions / HALO

Cu metal

Spike RTAArF litho

SiONChannel strainLow-k dielectricCo-implant USJImmersion litho

High-KMetal GateMulti-Gate

SEGmsec anneal

‘70 ‘80 ‘90 ‘00

A Few enabling R&D Breakthroughs

‘60

© imec 2005 5SSDM 2005

Scaling Trends

0

50

100

150

200

250

300

350

400

0 50 100 150 200 250 300 350 400

Technology nodeLg [um]

Technology Node

Lgate Tox

0.5

1

1.5

2

2.5

3

3.5

4

0 50 100 150 200 250 300

Tox [um] MPU

Tox [nm] ITRS

Technology Node

Slower

than I

TRSAccela

ration

Slowdown

Introduction of Channel Strain at 90nm and beyond allows to meetchip performance with less aggressive scale of Lg and Tox

© imec 2005 6SSDM 2005

Power - Performance

Increasing VddDecreasing LgDecreasing Vt

Chip package thermal limit

Fast

par

t

Nom

inal

par

t

Slo

w p

art

Lets have a look at the Power-Performance curve !

© imec 2005 7SSDM 2005

Power - Performance

N-1 NN+1

~25%~25%

After investigation :• Performance ~ CV/I• Power (Iddq) ~ Ioff*V

Power 2x/node Objective of scaling

© imec 2005 8SSDM 2005

Power - Performance

N-1 NN+1

~25%~25%

After investigation :• Performance ~ CV/I => need high Idsat• (Static) Power ~ Ioff*V => need low Ioff

© imec 2005 9SSDM 2005

Power - Performance

Traditionally :High Idsat => Thin Tox

However,Thin Tox limited by gate leakage

New paradigm (2003-beyond) :High Idsat =>High mobility

=>Low RS/D

Whats next ?© imec 2005 10SSDM 2005

Scaling Trends

0

50

100

150

200

250

300

350

400

0 50 100 150 200 250 300 350 400

Technology nodeLg [um]

Technology Node

Lgate Tox

0.5

1

1.5

2

2.5

3

3.5

4

0 50 100 150 200 250 300

Tox [um] MPU

Tox [nm] ITRS

Technology Node

??

© imec 2005 11SSDM 2005

Device Design Parameters

Opportunities :1. RS/D -> Strain, USJ & silicide2. µ -> Strain, orientation, Ge..3. Tinv -> Metal Gate, High-K4. Lg -> Architecture5. Cpar -> SOI, Tgate, Spacer

1 23

4

5

Any new CMOS family member isworking on 1 or more of these.

© imec 2005 12SSDM 2005

Feature Size Scaling (Lg)

Raised S/D

© imec 2005 13SSDM 2005

Device Architecture

Improves:- Short channel effect

double gate effect

- Sub-threshold slopestronger gate-channel coupling

- Mobilitylower channel doping

From Bulk to SOI to Multi-Gate

Bulk MOSFET

Thin Body SOI MOSFET

Double Gate MOSFET

-0.2

-0.1

0

0.1

0.2

0.3

0 0.02 0.04 0.06 0.08 0.1

DG-SOI_5nmDG-SOI_10nmFD-SOI_5nmBulk

Lgate [um]

EMER

ALD

© imec 2005 14SSDM 2005

Device scaling

© imec 2005 15SSDM 2005

Bulk scaling+ strain- high doping levels

Device scaling

© imec 2005 16SSDM 2005

Device Architecture

FinFET (DG) fabrication

© imec 2005 17SSDM 2005

Device Architecture

© imec 2005 18SSDM 2005

Device Architecture

Ring Oscillators

© imec 2005 19SSDM 2005

Co-design of TCS

Improved loop: more internal feedback is needed at the various levels, with the adding of the DEVICES (wires and Xtors) at the tech. level

Design strategies

EnergyDelay

IC High Level model

Feed-back

Feed-back

Technology parameters

Keff

w s p=w+s

Cl

Cp

Cp

Cl

h=p/2

h

h

ρeff

Keff

w s p=w+s

Cl

Cp

Cp

Cl

h=p/2

h

h

ρeff

IC System levelRAM

RAM

Data-path

RAM

RAM

RAM

Data-path

RAM

IC circuit level

Technology levelWires + Xtors

R(f) L(f)

C(f) G(f)

LOAD

R(f) L(f)

C(f) G(f)

LOAD

R(f) L(f)

C(f) G(f)

LOAD

IC System levelRAM

RAM

Data-path

RAM

RAM

RAM

Data-path

RAM

IC circuit level


R(f) L(f)

C(f) G(f)

LOAD

R(f) L(f)

C(f) G(f)

LOAD

R(f) L(f)

C(f) G(f)

LOAD

Design strategies

EnergyDelay

IC High Level model

Feed-back

Feed-back


Keff

w s p=w+s

Cl

Cp

Cp

Cl

h=p/2

h

h

ρeff

Keff

w s p=w+s

Cl

Cp

Cp

Cl

h=p/2

h

h

ρeff


Keff

w s p=w+s

Cl

Cp

Cp

Cl

h=p/2

h

h

ρeff

Keff

w s p=w+s

Cl

Cp

Cp

Cl

h=p/2

h

h

ρeff

IC System levelRAM

RAM

Data-path

RAM

RAM

RAM

Data-path

RAM

IC circuit level


R(f) L(f)

C(f) G(f)

LOAD

R(f) L(f)

C(f) G(f)

LOAD

R(f) L(f)

C(f) G(f)

LOAD

IC System levelRAM

RAM

Data-path

RAM

RAM

RAM

Data-path

RAM

IC circuit level


R(f) L(f)

C(f) G(f)

LOAD

R(f) L(f)

C(f) G(f)

LOAD

R(f) L(f)

C(f) G(f)

LOAD

© imec 2005 20SSDM 2005

Conventional scaling

SPICE model

Expectation :Substrate : Si, SOI, Ge, GOI, GaAs, InP,..Gate stack : SiO2, HK, poly, Metal Gate,..Architecture : Bulk, PD-SOI, FD-SOI, finFET,..

Models become more complex capturing thePhysics, but remain abstract for designer

© imec 2005 21SSDM 2005

FinFET benefits

DeviceScaling Lg (improved SCE immunity)Higher IdriveMaintain CV/I improvement 25% per node

Circuit density1 direction1 fin & gate density1 WNo STI isolation issues (stack nFET/pFET closer)

Architectural (high speed)Opportunity to improve V/I wrt bulk (Hfin can be increased)

What is the benefit in case BEOL RC does not scale ?

Process technologyCompatibility with std processing

© imec 2005 22SSDM 2005

© imec 2005 23SSDM 2005 © imec 2005 24SSDM 2005

OutlineOutline





© imec 2005 25SSDM 2005

Process sequence

Mesa-type fin patterning

Sidewall conditioning

Gate deposition + patterning0.4nm chemox1.4nm ALD-HfO25.0nm ALD TiN100nm poly-silicon193nm photogate etch + strip

Extension/HALO

HDD spacer

Deep S/D + spike RTA

Raised S/D epi

NiSiCA/M1

FinFET follows conventionalprocessing, can be donein any Si pilot line.

Process re-useability is higherthan 70%.New steps:

- HK / MG- raised S/D epi(-spacer defined fin)

© imec 2005 26SSDM 2005

Fin patterning

2 approachesResist-defined fin (conventional)Spacer-defined fin

Si finsource drain Si film

buried oxideSi fin

source drain Si film

buried oxide

Box

Fin

HMResist

Recess

Box

Fin

Spacer

Resist-defined Spacer-defined

© imec 2005 27SSDM 2005

Fin patterning



buried oxideSi fin


buried oxide

Box

Fin

HMResist

Recess

Box

Fin

Spacer


© imec 2005 28SSDM 2005

Fin patterningResist-defined

Hard MaskTEOS, SiN or SiON, APF (C-based)Used for CD trimmingIssues:

•Removal creates box recess•Too much trimming creates LER

Photo process193nm, attPSM for optimum process control and resolutionCD control

Etch processModified gate etch process (Hfin=30-60nm)

•X-talline Si instead of poly-Si•Stopping on thick Box

Strip processFin conditioning

2nm oxidationH2 anneal @900C

© imec 2005 29SSDM 2005


Bulk CMOS gate etching know-how can beRe-used to etch fins

© imec 2005 30SSDM 2005


CD 10-20nm

Corner roundingH2 anneal @900C

© imec 2005 31SSDM 2005


70 nm35 nm

Fin length

Fin length

Fin width depends on Fin length

© imec 2005 32SSDM 2005


Wfin

Lfin

90

100

110

120

130

140

150

50 100 150 200 250 300 350 400

Fin Length L-eff (nm)

Fin

Wid

th W

(nm

)

conv NA0.63 conv NA0.75 annular NA0.75quasar NA0.63 quasar NA0.75

Diff. in W for L-long to L-short :* NA0.63, conv. = 48.2nm* NA0.75, conv. = 32.9nm* NA0.75, ann. = 38.6nm* NA0.63, quas. = 12.9nm* NA0.75, quas. = 17.7nm

130n

m

90nm

65nm

45nm

32nm

Need for advanced litho settings & OPC

© imec 2005 33SSDM 2005

373.5

101.2

400.4

103.7

351.8

100.1FIN_Lexp

FIN_W


719.5

91.4

226

121.9NO OPC

281.8

99.9

OPC 1

761.9

96.4

OPC 2

270

97.9

737.9

95.5

60

70

80

90

100

110

120

130

200 400 600 800 1000 1200Lexp (nm)

W (nm) NO OPC - NA0.63 sigma 0.89OPC1 - NA0.63 sigma 0.89OPC2 - NA0.63 sigma 0.89

© imec 2005 34SSDM 2005


400.4

103.7

281.8

99.9

761.9

96.4

Dry 193, conventional illumination, No OPC

Wet 193, Quasar illumination, OPC

© imec 2005 35SSDM 2005


Extract more data out of the image : LER

Meas 1Meas 2

LWR Accuracy

0.1

1

10

1 10 100 1000

r (nm)

G(r)

(a.u

.)

σ = 2.6nm

ξ = 35nmα = 0.5

correlation function

[P. Leunissen et al., Proc SPIE 2005]

0

0.2

0.4

0.6

0.8

1

1.2

0 2 4 6 8 10

LWR (nm)

Prob

abili

ty D

ensi

ty (a

.u.)

LS2LS8

© imec 2005 36SSDM 2005

Fin patterning



buried oxideSi fin


buried oxide

Box

Fin

HMResist

Recess

Box

Fin

Spacer


© imec 2005 37SSDM 2005

Fin patterningSpacer-defined

Spacer defined patterning looks promising in this phase of device development because:1. Less LER expected

- pattern defined by spacer not by resist2. Fin density is doubled

- relaxes requirements on lithography- or more Idsat per unit area (V/I instead of CV/I)

3. Less CD variation expected over the wafer- spacer material & deposition parameters can be easily optimized (no dopants in place yet)- allows to optimize for the fin etch and surface smoothness (no trimming needed)

© imec 2005 38SSDM 2005


Si

BOX

Si

BOX

Si

BOX

BOX

BOX

TEOSnitrideSi

CD=15 +/- 3nm

© imec 2005 39SSDM 2005


Si

BOX

resistspacer Need for wider fins !

BOX

Resist based patternSpacer defined pattern

Spacer-defiend fins always come in closed loops© imec 2005 40SSDM 2005

Fin patterning

2 approachesResist definedSpacer defined

Circuit aspects (resist-based)Typical device test layoutSRAM cellLogic library elements (NAND,…)

© imec 2005 41SSDM 2005


Active Area Contact

Gate

Typical device test layout- fins are connected bya fin pad

- 1 contact would be OK

Typical 6T-SRAM layout- stand-alone fins- each fin need a contact

+ fin width independent of fin length- line end shortening (manageable ?)0 need for metal-0 to connect fins and

maintain density (M1 routing)© imec 2005 42SSDM 2005


Optimised process

© imec 2005 43SSDM 2005


0.186um2 cellpitch = 124nmASML /1250i, NA=0.85immersion

© imec 2005 44SSDM 2005


0.134um2 cellpitch = 112nmASML /1400, NA=0.93

Fin process shows excellentscalability

© imec 2005 45SSDM 2005

0.1

1

2000 2001 2002 2003 2004 2005 2006 2007 2008

TSMCIBMNECIFXToshibaSamsungMotorolaIntelSonySTLSI LogicHitachiFujitsuImecTexas Instruments

Year of publication [IEDM, VLSI]

130

9065

SRAM patterningResist-defined

SRAM cell size roadmap

3245

E-beam

0.2

0.3

0.5

2

Optical trend line

0.186um2

0.134um2

© imec 2005 46SSDM 2005

SC45 (22/06/2004)

Cross-section of FIN

SRAM array after poly-Si patterning

SRAM array after spacer etch

SNM = 170mV @ 0.6V VDD

SNM = 240mV @ 1.0V VDD

45nm SRAMX=730nmY=430nm0.314um2

© imec 2005 47SSDM 2005

Cell cross-sections

© imec 2005 48SSDM 2005


Active Area Contact

Gate

Metal-0

Typical logic library element- stand-alone fins- each fin need a contact

Typical device test layout- fins are connected bya fin pad

- 1 contact would be OK

Modified logic library element- stand-alone fins- Metal-0 local interconnect- only 1 contact needed

© imec 2005 49SSDM 2005

OutlineOutline





© imec 2005 50SSDM 2005

Gate patterning

Poly-SiSiONSi-fin

MuGFETBulk FET

© imec 2005 51SSDM 2005

Gate patterning

BOX

POLY

Active Area

TEOS HM

POLY

Active Area

BOX

POLY

Active Area

BOXBOX

Active AreaActive Area

BOX

Active Area

BOX

High topography gate formation

Ex. Micro masking by HM

© imec 2005 52SSDM 2005

Gate patterningEtch-back approach

BOX

POLY

Active Area

BOX

Active Area

POLY

• deposit 200nm poly• anisotropic etchback to 100nm• litho + gate etch

• deposit 100nm poly• anisotropic• idem (same recipes)

+• less over-etch for removal of poly residues • larger process window for hard mask trimming• better CD uniformity • nitride spacer etch: less residual nitride on top of gate-• extra non-uniformity

© imec 2005 53SSDM 2005

Threshold Voltage control

Wfin_design (um)

No fin doping

various fin doping

Line

ar th

resh

old

volta

ge

No fin dopingN+ poly gate

various fin dopingN+/poly gate

Target Vt range

Line

ar th

resh

old

volta

ge

Wfin [um]

0.0350.050

0.0700.100

Undoped fin

Doped fin

© imec 2005 54SSDM 2005

Threshold Voltage control

Wfin_design (um)

No fin doping

various fin doping

Line

ar th

resh

old

volta

ge

No fin dopingN+ poly gate

various fin dopingN+/poly gate

Target Vt range

Line

ar th

resh

old

volta

ge

Wfin [um]

0.0350.050

0.0700.100

Undoped fin

Doped fin

Need MG (midgap +/- 200mV ?)

© imec 2005 55SSDM 2005

Gate patterningMetal Gate

Poly-SiSiONSi-fin

MuGFETBulk FET

Poly-SiTaN, TiN, W, Mo,…SiON, HfO2Si-fin

© imec 2005 56SSDM 2005

poly

TiN

HfO2

TiN

/ HfO

2

Fin

Box


© imec 2005 57SSDM 2005

PMOS (VDD=-1V)

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

100 150 200 250 300 350 400 450 500Ion [uA/um]

Ioff

[A/u

m]

poly/SiON bulk results (C065)ARTEMIS targetITRSMUGFET (Wfin=20nm)


For Narrow FIN (~20nm):Excellent PMOS demonstrated on (HfO2/TiN/poly)Ion uncertainty from in-line Wfin measurements evaluated to be ~ +/- 7%

Poly/SiON IBMTSMC

HITACHIEuropeanpartners

Jg ~ 60A/cm2

Jg=4mA/cm2

Poly/TiN/HfO2_2nm

265uA/um @ 20pA/um, Vdd=1.0V

© imec 2005 58SSDM 2005

NMOS (VDD=1V)

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

300 400 500 600 700 800 900 1000Ion [uA/um]

Ioff

[A/u

m]

poly/SiON bulk results (C065)ARTEMIS targetITRSMUGFET (Wfin=20nm)MUGFET (Wfin=40nm)HK/MG bulk results


For Narrow FIN (~20nm):NMOS is fairly weak, in regards to this gate stackMore characterization on going to better quantify drive loss from such narrow FIN (Rext)

Poly/TiN/HfO2_2nm

Europeanpartners

IBMTSMC

HITACHI

Poly/SiON

Poly/SiONJg ~ 60A/cm2

Jg=20mA/cm2

© imec 2005 59SSDM 2005

Mobility improvement

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

200 300 400 500 600 700

referencetensilecompressive

I off [A

/µm

] @ V

gs=-

0.3

V

Ion

[µA/µm] @ Vgs

=0.7 V

Vds

=1 V

15%-30%

NMOS with CESL

10-10

10-9

10-8

10-7

10-6

10-5

10-4

200 300 400 500 600 700

SiGe S/DReferenceI O

FF[A

/µm

] @ V

GS=0

.2V

ION

[µΑ/µm] @ VGS

=-0.8V

25%

10-15% improvement in drive current from implementation

of CESL with strain

implementation of SiGe SD into MUGFET increases 25% PMOS

performance (Rs reduction + compressive strain)

poly

SiGe SiGe

SiGe

-20

-10

0

10

20

30

40

50

0 200 400 600 800 1000

100 nm 800 MPa

100 nm 1.4 GPa

Mob

ility

gai

n ∆µ

/µ [%

]

Lg [nm]

open symbols: top channelclosed symbols: sidewalls

pMOS

nMOS

© imec 2005 60SSDM 2005

Conformal junctions

20nm reduction in Lmin in NMOS and PMOS devices with PLAD

PLAD proved to form conformation junctions*

*) As data

Transistors with PLAD junctions demonstrated

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-1 -0.5 0 0.5 1Vg (V)

Id (A

)

NMOSPMOS

Vd=-1V Vd=1V

Vd=-0.1VVd=0.1V

Lpoly=46nm Fin Width=21nm

© imec 2005 61SSDM 2005

OutlineOutline





© imec 2005 62SSDM 2005

Summary

FinFETs can be made with conventional processingShow excellent scalability, devices & circuit densityRemaining issues

Idsat improvementIntroduction of strainJunction engineering w/o defects

© imec 2005

Back up

© imec 2005

Back up

© imec 2005

Back up

© imec 2005

Back up

© imec 2005 67SSDM 2005

Metal gate for 3D-SOI devices

Poly silicon5nm TiN

Poly

TiNSi fins

Gate profileNOTCH

© imec 2005 68SSDM 2005

Gate & Fin patterning

Si fins

Poly-SiSiONSi-fin

MuGFETBulk FET

CDCDU1D Profile1D Notch/FootDefects

CDCDU2D Profile2D Notch / FootDefects

© imec 2005 69SSDM 2005


Si fins

Active

FieldOxide

Poly

HM

TaN

Active

FieldOxide

Poly

HM

TaN

Poly-SiTaN, TiN, W, Mo,…SiON, HfO2Si-fin

45nm FETBulk FET

+

© imec 2005 70SSDM 2005

Observation : GIDL

Ioff could be reduced by up to 2-3 orders of magnitude if we can fix GIDL

GIDL determines Ioff

*) As data

GIDL in SOI FETs

n+ n+

N-type0V

Vg < 0V

VDD

BOX

h e

GIDL

10-12

10-10

10-8

10-6

10-4

0.01

-0.5 0 0.5 1 1.5

Ids

versus Vg at V

ds=0.02V and V

ds=1.3V, W=20nm

(HfO2/ALD TiN - NMOS)

Lg=1um @Vd=1.3VLg=5um @Vd=1.3VLg=10um @Vd=1.3VLg=1um @Vd=0.02VLg=5um @Vd=0.02VLg=10um @Vd=0.02V

Dra

in c

urre

nt (A

/um

)

Vg (V)

Ioff

GIDL

© imec 2005 71SSDM 2005

HARMONY++, BS20

BS200.186um2 cellPC pitch = 150nm/1250i

Poly

© imec 2005 72SSDM 2005

Fin

Gate

Poly residue

© imec 2005 73SSDM 2005

Poly etch back for smooth topography

BOX

POLY

Active Area

BOX

Active Area

POLY

Etch back

BOX

POLY

Active Area

© imec 2005 74SSDM 2005

© imec 2005 75SSDM 2005

2D Simulation study (Lg=25nm)

1E16 1E17 1E18 1E190

200

400

600

800

1000

1200

DIB

L (m

V/V

)

Bulk FDSOI (TSi) DGFET (WFIN) 15 nm 15 nm

10 nm 10 nm 5 nm 5 nm

Channel doping (cm-3)

1E16 1E17 1E18 1E19

100

200

300

400

500

600


10 nm 10 nm 5 nm 5 nm

Sub

thre

shol

d sw

ing

(mV

/dec

.) @

VD

S= 1

V

Channel doping (cm-3)1E16 1E17 1E18 1E19

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

ΦM= 4.17 V

ΦM= 4.0 V

ΦM= 4.6 V

Bulk FDSOI DGFET

Thre

shol

d V

olta

ge (V

)

Channel doping (cm-3)

0.00 0.02 0.04 0.06 0.08 0.100

200

400

600

800

1000

DIB

L (m

V/V

)


5 nm 5 nm

LG (µm)0.00 0.02 0.04 0.06 0.08 0.10

50

100

150

200

250

300 Bulk FDSOI (TSi) DGFET (WFIN)

10 nm 10 nm 5 nm 5 nm

S SAT

(mV

/dec

.)

LG (µm)0.01 0.02 0.03 0.04 0.05

-0.2

0.0

0.2

0.4

0.6

0.8


5 nm 5 nm

V T,LI

N (V

)

LG (µm)

LG= 25 nmWfin/Tsi=15nm

LG= 25 nm LG= 25 nm

© imec 2005 76SSDM 2005

0.1

1

2000 2001 2002 2003 2004 2005 2006 2007 2008

TSMCIBMNECIFXToshibaSamsungMotorolaIntelSonySTLSI LogicHitachiFujitsuImecTexas Instruments


130

9065

Status 6T-SRAM cell developmentSRAM cell size roadmap

3245

E-beam

0.2

0.3

0.5

2

Optical trend line

200mm (1100)

300mm(1250i)

(1700)

© imec 2005 77SSDM 2005

SOI MuGFET Device Roadmap

Dual silicideDual silicideNiSiSilicide engineering

W or betterW or betternoneM0

TBITBICESLStrain engineering

LOCOSFETCompound channel

LOCOSFETFinFETArchitecture

SBFETPLAD + laserEPI-style + laserSEG

Implant + spikeSEG

USJ engineering

HK / Dual MGMore WF tuningNotch free MG

(SiON+,HfO2)/OtherMore WF tuningNotch free MG

(SiON,HfO2)/TiNWF tuningNotched MG

Gate engineering

100nm15nm20nm

80nm18nm30nm

60nm25nm45nm

HfinWfinLg

22 nm32 nm45 nm

© imec 2005 78SSDM 2005

Program Status

We have a established baseline process

We have demonstrated 45nm node devices

We have demonstrated 45nm node circuits (SRAM cell)

© imec 2005 79SSDM 2005

Program Status

We have a established baseline processRoute availableDraft Design Rule manual availableV0.1 SPICE model available (HW based)

We have demonstrated 45nm node devices


© imec 2005 80SSDM 2005

Highlights: baseline process

before:

Objective: open up the window for gate etch optimization

Now in POR: polySi etch back

BOX

poly-Si

Active Area

BOX

Active Area

poly-Si

Residue free etch back

BOX

POLY

Active Area

poly-Si residues parallel to active area

© imec 2005 81SSDM 2005

Program Status & Highlights

Nano-scale CD

© imec 2005 82SSDM 2005


BLUES (preliminary floor plan)XSEM

XS

EM

HPLHPL

TDROMTDRAMDevice arrays

RO

AdderLogic Library SRAM cells

Loco

sfet

ACLV

ACLV

ACLV

ACLV

ACLV

ACLV

ACLVRO

Small circuits

OPC, SEM ESD IPC box

Charac. Charac.DevicesTdaamatching

© imec 2005 83SSDM 2005


We have a established baseline processRoute availableDraft Design Rule manual availableV0.1 SPICE model available

We have demonstrated 45nm node devicesContain all the gismos : HK/MG/Strain/Conformal USJ/…pFET OK, nFET low on Idsat


© imec 2005 84SSDM 2005



We have demonstrated 45nm node deviceswith HK/MG/Strain/Conformal USJ/…pFET OK, nFET low on Idsat

Actions in place to get improved performance


© imec 2005 85SSDM 2005

Short term Plan (2H05)

nFET Idsat improvements Gate process

EOT scaling from 2.1nm towards 1.3nm -> 1.1nm -> …0-notch gate TiN processVt tuning strategy (implant, anneal)Other MG candidates (Mo-based, W-based, WSi,…)

Junction processConformal junctions by Plasma Doping, density scalingLaser annealRaised S/D by SEG

Improved PECVD spacerMobility

High stress CESLDifferent orientationsubstrates

SilicideNiSi -> PtSi, YbSi

1000uA

750uA

© imec 2005 86SSDM 2005



We have demonstrated 45nm node deviceswith HK/MG/Strain/Conformal USJ/…pFET OK, nFET low on Idsat

Actions in place to get improved performance

We have demonstrated 45nm node circuits (SRAM cell)Demonstrated 0.274um2 cell with TaN/SiON

In progress 0.245 um2 with TiN/HfO2 : 200mmPlan for 0.180 um2 in place (193i) : 300mm

Printed (optical) Active Area (AF,RX) consistent with 0.13um2

© imec 2005 87SSDM 2005

SC45-SC32 Status

1Q04 2Q04 3Q04 4Q04 1Q05 2Q05 3Q05 4Q05

SC32-1100

SC45-MG

SC45-Logic

SC32-1250i

SC45-MGLogic0.245um2

HARMONY HARMONY+ BLUES28/01/2005

HA++

0.180um2

SC45_Base

0.274um2

0.314um2

© imec 2005 88SSDM 2005

SC45+MG (23/12/2004)

0.2

0.3

0.4

0.50.60.70.80.9

1

2

3

1999 2000 2001 2002 2003 2004 2005 2006

TSMCIBMNECIFXToshibaSamsungMotorolaIntelSonySTLSI LogicHitachiFujitsuImec


130

9065

3245

E-beam

Box

Poly-SiInserted-TaxNy

SiONSi-fin

Optical Litho trend line

SC45+MG

SC45

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

10.274 µm2

Node 1 (V)

Nod

e 2

(V)

0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 10

50

100

150

200

250

VDD (V)

SNM

(mV

)

10% VDD

Metal Gate

Poly Gate

Cell: 0.274um2

X=720nmY=380nm0.274um2

© imec 2005 89SSDM 2005

SC32-1100 (15/12/2004)

X=720nmY=340nm0.245um2

Process can be extendedto aggressive pitches on/1100 due to aggressive OPC

Purpose of this work is to prepare the 1250i work

© imec 2005 90SSDM 2005

SC32-1400 (20/1/2005)

Active area printed on /1400 (NA=0.93, 300mm)Active Pitch 112nmCell pitch compatible with 0.134um2 cell

DemoHighest NA possible

© imec 2005

EMERALDprocess learning

© imec 2005 92SSDM 2005

Highlights: Baseline process

FIN scaled down to 20nm without loss in FIN height

Objective: reduce SCE in MUGFET transistor

2.4 nm

15 nm

63 nm

Si- Fin

BOX

Gate Oxide

Poly-Si

2.4 nm

15 nm

63 nm

Si- Fin

BOX

Gate Oxide

Poly-SiResults:

• Better S• Reduced DIBL

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0 0.2 0.4 0.6 0.8 1Lpoly (um)

DIB

L (m

V) Width=1umWidth=60nmWidth=25nm

© imec 2005 93SSDM 2005

Surface smoothening (H2 anneal)

900ºC 5 min (POR)

900ºC 2 min

950ºC 1 min

850ºC 5 min

POR condition is on the edge

looks more rough

© imec 2005 94SSDM 2005

Surface smoothening

H2 anneal vs no H2 annealI of

f[A

/µm

]

Ion [µA/µm]

90 nm10% increase2 orders

© imec 2005 95SSDM 2005

Highlights: baseline process

Physical sputtering+ 2nm dry oxidation Radius 10nm for 2nm SSE

Objective: find a crystal-orientation independent technique of corner rounding

900ºC 2 min

POR: Corner rounding achieved by H2 anneal only

© imec 2005 96SSDM 2005

Highlights: Baseline process

Small CD (14-17nm)CD variations

Objective: Increase FIN density for higher current /area

Spacer defined FIN patterning: feasibility proven for FIN doubling

BOX

Ldummy

© imec 2005 97SSDM 2005

Gate & Fin patterning (193nm resist)

Si fins

Poly-SiSiONSi-fin

MuGFETBulk FET

© imec 2005 98SSDM 2005

Gate & Fin patterning (193nm resist)

Poly resisduesRemaining HM BARC planarisation

Optimised processOptimised process

High topography gate formation

© imec 2005 99SSDM 2005


Si fins

MuGFET withMG

Active

FieldOxide

Poly

HM

TaN

Active

FieldOxide

Poly

HM

TaN

Poly-SiTaN, TiN, W, MoSiON, HfO2Si-fin

45nm FETBulk FET

+

© imec 2005 100SSDM 2005

Solution: Berkeley approach with Si SEG

Si SEG on S/D after parasitic spacer recess (Hgate > Hfin)

Si SEG

© imec 2005 101SSDM 2005

Source/Drain Resistance … (contd.)

Measurements on fabricated devices are shown Narrow fin MuGFETs show high S/D resistance (RSD)

10 102 103

0

2

4

6

8

Par

asiti

c S

/D R

esis

tanc

e (k

Ohm

)

Fin Width (nm)

© imec 2005 102SSDM 2005

T1.1: SEG for MuGFET — faceting

SEG on MuGFET (no poly present):• 45 nm grown on 60 nm heigh fins• Facets are orientation dependent due to the difference in growth rate• Epi overgrowth

single fin

multiple fins

© imec 2005 103SSDM 2005

Box

Si Sub

Si

Box

Si Sub

Si

Highlights: Conformal junctions

Study on compatibility of different conformal USJ formation techniques with MUGFET structure started

(PLAD, VPD, Solid Source, Epi tip, Schottky barrier….)

VPD

Box

Si Sub

Si

Carrier Gas

Box

Si Sub

Si

Carrier Gas

Solid Source diffusionEpi tip

Doped Epi

Suitability and compatibility of alternative annealing techniques (Flash, Laser) initiated

© imec 2005 104SSDM 2005

Novel Architectures

65nm GP & LP

Novel Architectures

Shottky Barrier FET

Tunnel FET

Bulk MuGFET

The Ultimate USJ

High Ion/Ioff ratio: Low Power applications

If SOI is too expensive

Choices: Open for discussion based on partner feedback

Other structures not yet on radar screen?

LOCOS FETLitho friendly FET

2004 2005 2006 2007 2008 32nm 45nm 22nm

© imec 2005 105SSDM 2005

Poly 170 pitch, 6%AttPSM/1100, 0.75NA dry, CD in resist@BF

69.9072.8072.874.074.0

CQUA300.89/0.65

70.0072.7072.772.271.7

CQUA200.92/0.72

QUAS300.89/0.65

QUAS200.92/0.72

75.574.9XY0573.986.6XY0670.170XY07

73.984.6XY0475.574.9XY0377.277.8XY0277.077.8XY01

ANN0.92/0.72

ANN0.89/0.65

© imec 2005 106SSDM 2005

OPCGap=50nm

© imec 2005 107SSDM 2005

OPCGap=80nm

© imec 2005 108SSDM 2005

STI process with flat topography

© imec 2005 109SSDM 2005

Contact after litho

© imec 2005 110SSDM 2005

© imec 2005 111SSDM 2005

Gate & Fin patterning

Residue ?Left over poly?

© imec 2005 112SSDM 2005

Logic: 30nm

SRAM1: 55nm SRAM2: 51nm SRAM3: 48nm

SRAM1 bridging

SRAM1: 55nm

SRAM3: 46nm SRAM3: 38nm

SRAM2: 30-37nm SRAM3: 31-40nm

Gate patterning

50 nm

After stack etch After silicidation

Fin height reductionin small lines

perspective on emerging devices and their impact on scaling … · 2010-06-28 · perspective on...

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