Performed by: Gidi Getter,Shir Borenstein

Supervised by: Ina Rivkin

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל

Technion - Israel institute of technologydepartment of Electrical Engineering

Space Wire Core for LEON3 System

Project Definition

• Design a Space Wire core.• Connect core to LEON3 system.• Load system to FPGA and test point to

point SW connection via Space Wire Bridge.

What is Space Wire?

• Space Wire is a spacecraft communication network. It is coordinated by the European Space Agency (ESA).

• Components are connected through low-cost, low-latency, full-duplex, point-to-point serial links.

• Uses data strobe encoding - differential ended signaling (DS-DE).

• Space Wire utilizes asynchronous communication and allows speeds between 2Mb/s and 400Mb/s.

• The protocol describes routing, flow control and error detection in hardware, with little need for software.

The Protocol

• Consists of Data characters and Control characters.

• Data characters are 10 bits long – 1 parity bit,1 flag bit set to ‘0’ and 8 data bits.

The Protocol

• Control characters are 4 bits long – 1 parity bit,1 flag bit set to ‘1’ and 2 control characters.

• Control codes is built with the ESC character following a FCT character / Data character.

Flow Control

• NULL is transmitted whenever a link is not sending data or control tokens.

• Data flow across a link is controlled using FCT’s sent from one end of the link to the other end to signify that the sender is ready to receive some more data.

• The receiver of the FCT’s needs to keep count of N-Chars sent and FCT’s received by the ratio of: 1 FCT = 8 N-Chars.

Space Wire Usage

SW

SW Router

Component A

(Computer, Device, etc)

Satellite

Component B

LEON3 System

LEON3 Processor

AMBA Bus

AHBController

JTAG Dbg Link

MemoryController

SERIAL Dbg Link

JTAG RS232

Space Wire Link

LVDS

RAM

SRAM, DRAM etc.

Space Wire Core

Transmitter

Receiver

TransmitFIFO

ReceiveFIFO

State Machine

AM

BA

Bus

AMBA Controller

32 bit

32 bit

32 bit

Space W

ire Link

Data

Strobe

Data

Strobe

StatusRegister

8 bit

8 bit

LEON3-Core Communication

• SW core will be implemented as a slave on AHB Bus.

• Implement status register for flow control between LEON3 processor and SW core.

• To write data, LEON3 first checks if there is room in the transmit FIFO, if so puts the data on AHB Bus.

• To read new data we use pulling: The LEON3 samples the status register to check for new data, and reads from the receive FIFO if new data arrived.

Development Steps

• Learn Space Wire Protocol.• Design a block diagram for SW core.• Learn how to connect core to AMBA Bus and

adapt the SW core for LEON3 use.• Implement the Core in VHDL.• Simulate the design with loopback.• Write C program and Simulate the design on

LEON3 system.• Load the system to GR-RASTA board.• Transfer data via SW connection from board to

SW bridge.

Time Line

• Learn Space Wire Algorithm and checking possible implementations – 2 weeks

• Characterization Presentation – 19/11/07• Design a detailed block diagram for SW

core ~ 2-3 weeks• Find solution for connecting core to AMBA

Bus ~ 1-2 weeks• Mid term presentation