performed by: or rozenboim gilad shterenshis instructor: ina rivkin המעבדה למערכות...
DESCRIPTION
Abstract (cont.) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Our Product: Simple calculator –4 basic operations (expandable) –16 bit number (up to 65k) –Supporting Integer numbers only Interfaces –Input: Keyboard Keypad - Numbers & Operations. –Output: 7 Segment display, 5 digit result.TRANSCRIPT
Performed by: Or RozenboimGilad Shterenshis
Instructor: Ina Rivkin
מהירות ספרתיות למערכות High speed digital systems laboratoryהמעבדה
הטכניון - מכון טכנולוגי לישראל
הפקולטה להנדסת חשמל
Technion - Israel institute of technologydepartment of Electrical Engineering
פרויקט” סיכום סופי ח דוSubject:
Mini Controller
2007אביב 1
Abstractמהירות ספרתיות למערכות High speed digital systems laboratoryהמעבדה
2
Project Goals:• Intensive Learning of Development Tools
– Design Using Graphic Editor and VHDL Editor (Including T.B. Design)
– Simulations– Synthesis– Implementation
• Creating an Example Design Demonstrating all Design Stages (Calculator)
Abstract (cont.)High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
2
Our Product:• Simple calculator
– 4 basic operations (expandable)– 16 bit number (up to 65k)– Supporting Integer numbers only
• Interfaces– Input: Keyboard Keypad - Numbers & Operations.– Output: 7 Segment display, 5 digit result.
System descriptionמהירות ספרתיות למערכות High speed digital systems laboratoryהמעבדה
3
Input Proc.Main Proc.
State Machines
Comm.
Protocol
KB Display:
7 segment
TB
SYSTEM
Output Proc.
Specificationמהירות ספרתיות למערכות High speed digital systems laboratoryהמעבדה
4
• Hardware– Altera DE2 Board
• FPGA: Cyclone II EP2C35F672C6• Eight 7-segment displays• 1 debounced pushbutton switch• Red/Green LEDs• 50-MHz oscillator
– PS/2 Keyboard (Keypad only)• Development Software
– ALTERA Quartus II V.7.2 / 8.0 Web Edition– ModelSim ALTERA 6.1g Web Edition
System Block Diagramמהירות ספרתיות למערכות High speed digital systems laboratoryהמעבדה
5
Test -Bench Input from keyboard
Processing
Output to 7_Segment X5
TestBench
Keyboard
Simulator
FF
8bit
Reg 16 bit
KbDecoder
Digit to Number
FSM
16-bit
to 4-bit
Section
+ Sign
7 Seg
Module
7447
Clk Clk
Clk
Clk rst
rst
rstClk
Opcode [3:0]
Number [15:0]
result [15:0]
7_Seg_en
7_Seg_en
result [15:0]
New number
New opcode
Ps2_data
Ps2_clock
Key
Data
[7:0]
seg0 [3:0] Hex 0 [6:0]
InputsResult_sampled [15:0]
FF
8bit
Digit [3:0]
Opcode
[3:0]
Hex
to
Digit
FF
8bit
FF
8bit
Clk
Clk
result _sign
result _signseg1 [3:0]
seg3 [3:0]
seg2 [3:0]
sign
Hex 1 [6:0]
Hex 2 [6:0]
Hex 3 [6:0]
Hex 4 [6:0]
Sign
[15:0] Result{
FPGA Block Diagram• Input Block:
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
6
FPGA Block Diagram• Process Block:
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
6
FPGA Block Diagram• Output Block:
High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות
6