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Performance-oriented Peephole Optimisation of Balsa

Dual-Rail Circuits

Performance-oriented Peephole Optimisation of Balsa

Dual-Rail Circuits

Luis Tarazona and Doug Edwards

Advanced Processor Technologies Group

School of Computer Science

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Syntax-directed compilationSyntax-directed compilation

• Used in Tangram and Balsa

• One-to-one mapping of each language construct into a network of handshake components (HCs)

• Benefits:

– Transparency and flexibility to the designer

• Drawback: medium-low performance

• Solutions to this have been proposed using:

– Control resynthesis

– Peephole optimisation

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Related workRelated work

• Tangram and Balsa compilers perform some peephole optimisations as a post processing step

• T. Chelcea has proposed resynthesis and peephole optimisations for Balsa, targeting a burst-mode back-end

• Plana et al. have proposed some optimised HCs for Balsa targeting single rail and dual-rail back-ends

Main interest of this work is on dual-rail back-ends due to its potential immunity to process variability.

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The optimisationsThe optimisations

1. Eliminating redundant FalseVariable components

2. New Concurrent RTZ Fetch component

3. Conditional parallel/sequencer component: ParSeq

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Eliminating redundant FVsEliminating redundant FVs

• Targets active input control

• Single access, single read-port FalseVariable or eagerFalseVariable HCs

i -> then

CMD

end

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Eliminating redundant FVs - ExampleEliminating redundant FVs - Example

• Latency and area reduction

• Preserves external behaviour

a, b -> then

o <- a + b

end

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Concurrent RTZ Fetch Concurrent RTZ Fetch

Wires-only dual-rail Fetch and its STG

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Concurrent RTZ Fetch Concurrent RTZ Fetch

New concurrent RTZ Fetch and its STG

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The ParSeqThe ParSeq

• Acts conditionally as a Concur (parallel) or as a Sequencer HC

• Few opportunities to apply it in the design examples available

– Perhaps caused by its inexistence at that time?

• Interesting increase in performance, though.

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Handshake circuit implementationHandshake circuit implementation

||

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Optimised ParSeq SchematicsOptimised ParSeq Schematics

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Simulation ResultsSimulation Results

Pre-layout, transistor-level simulations, 180nm technology

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Conclusions and Future WorkConclusions and Future Work

Future work:

• To incorporate the optimisations into the Balsa design flow

• ParSeq as a construct or as a peephole optimisation?

• To evaluate other peephole and HCs optimisations currently under study

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Thank you very much!

Questions?

Acknowledgement

• Thanks to Luis Plana, Andrew, Charlie and Will for their suggestions and comments.

• This work and PhD are supported by EPSCR and UoM School of Computer Science scholarships.