performance analysis of amd multi-core processor and graphical...

Performance Analysis of AMD Multi-core Processor and Graphical Processing Units

Mohammad Ashraf BhuiyanMelissa C. SmithVivek K. Pallipuram

June 2011

This work supported in part by NSF Grant No. CCF-0916387

Motivation

The recent trend of computingMulticore and many-core processorsMany-core GPUs

Various types of Accelerators availableNumber of cores, threadsMemory hierarchyProgramming modelsCode optimization techniques

Parallel program development requires knowledge ofAcceleration techniques and optimizationsApplication characteristics

This calls forPerformance analysis of Accelerators for ApplicationsUnderstanding the match between Accelerators and Applications

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Outline

Experimental SystemAMD 8 core and 32 core CPUAMD 1600 core GPU

Spiking Neural NetworkBiological ModelsNetwork Design

Preliminary ResultsEffect of problem sizeEffect of optimizationsEffect of threads/cores

Future Work

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Experimental Systems

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Utilizing several leading architecturesAMD 8-core (Opteron 2356)AMD 32-core (Opteron 6134)AMD 1600-core GPU (Radeon 5870)

Case Study: Neuron Models & Network

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Two Layer Network:

SNN Model FLOPs per neuron update

Memory Accessper Neuron (Byte)

FLOP/ByteRatio

Izhikevich 13 20 0.65

Wilson 38 44 0.86

Morris-Lecar 132 28 4.71

Hodgkin-Huxley 246 44 6.02

Image

Level 1 neurons

Level 2 neurons

Network (Problem Size) Scaling

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Image Size Level 1Neurons

Level 2 Neurons

Total Neurons

96×96 9216 48 9264

192×192 36864 48 36912

240×240 57600 48 57648

…… …… …… ……

2400×2400 5,760,000 48 5,760,048

3120×3120 9,734,400 48 9,734,448

Preliminary Results

Accelerator performance studyProblem sizeOptimization techniquesAccelerator configuration

Number of threads for CPULocal work group size for GPU

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Problem Size Variation

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Izhikevich Wilson

Speedup over a serial implementation on Intel core 2 quad, 2.66 GHz, using all compiler optimizations

Problem Size Variation Cont.

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Morris-Lecar Hodgkin-Huxley

Optimization Techniques Used

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AMD Multi-core

1. pth: POSIX thread, 2. SSE: Streaming SIMD

Extension 3, 3. SP: Software Prefetching

AMD Radeon GPU

1. MT: Multithread 2. SP: Software Prefetching3. LM: Local Memory4. MW: Memory Write 5. MAT: Unsafe Math and

Native Math 6. RCS: Reducing

Conditional Statement7. VEC: Vector Calculation

Optimization: AMD 8 core

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Izhikevich Wilson

pth: POSIX thread, SSE: Streaming SIMD Extension 3, SP: Software Prefetching

Optimization : AMD 8 core Cont.

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Optimization: AMD 32 core

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Izhikevich Wilson


Optimization : AMD 32 core Cont.

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Optimization : AMD 1600 core GPU

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Izhikevich Wilson

MT: multithread, SP: software prefetching, LM: local memory, MW: memory write, RCS: reducing conditional statement, MAT: Unsafe and Native math, VEC: Vector Calculation

Optimization: AMD 1600 core GPU

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MT: multithread, SP: software prefetching, LM: local memory, MW: memory write, RCS: reducing conditional statement, MAT: Unsafe and Native math VEC: Vector Calculation

Thread Effect: AMD 8 core

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Thread Effect: AMD 32 core

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Thread Effect: AMD 1600 core GPU

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Performance Observations

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Problem Size EffectGenerally performance improves with problem sizeIzhikevich model on AMD 8 core CPU

Speedup of 9x for 9000 neurons; 16x for 9.7 million neurons

HH model on AMD 1600 core GPUSpeedup of 11x for 9000 neurons;603x for 9.7 million neurons

Flop:byte Ratio EffectsHigher value provides better performanceIzhikevich (0.65): 12xHH (6.02) : 603x

Performance Observations

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Architecture Specific Optimizations Generally performance improves with optimizationsAlso depends on

Problem sizeFlop:byte ratio

Threading EffectGenerally performance improves with threadsAlso depends on

Problem sizeOverhead for Intra-processor communications

Future Work

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Extend the experimentHeterogeneous architecture (multi-core + GPU)Multi-node accelerators (Supercomputers)Accelerators from other vendorsOther application kernels such as

BioinformaticsMolecular DynamicsOptimization problems (Simulated Annealing)

Related Publications

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JournalMohammad Bhuiyan, Melissa C. Smith, Vivek K. Pallipuram, “Performance, Optimization and Fitness: Connecting Applications to Architectures”, in Journal of Concurrency and Computation: Practice and Experience, Wiley, December 2010, DOI: 10.1002/cpe.1688Vivek K. Pallipuram, Mohammad Bhuiyan, and Melissa C. Smith, “A Comparative Study of GPU Programming Models and Architectures”, in Journal of Supercomputing, Springer, May 2011, DOI: 10.1007/s11227-011-0631-3

ConferenceMohammad Bhuiyan, Ananth Nallamuthu, Melissa C. Smith, and Vivek K. Pallipuram, “Optimization and Performance Study of Large-scale Biological Networks For Reconfigurable Computing,” in proceedings of HPRCTA, SC 10, New Orleans, April 2010Mohammad Bhuiyan, Vivek K. Pallipuram and Melissa C. Smith, “Acceleration of Spiking Neural Networks in Emerging Multi-core and GPU Architectures,” in IEEE proceedings HiCOMB, IPDPS, Atlanta, GA, April 2010Kenneth Rice, Mohammad Bhuiyan, Tarek M. Taha, Christopher N. Vutsinas, Melissa C Smith, “FPGA Implementation of Izhikevich Spiking Neural Networks for Character Recognition,” in proceedings ReConFig09, pp. 451 – 456, Dec. 2009

Thank you

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