PCIe 2.0 Base PCIe 2.0 Base Specification Protocol Specification Protocol And Software OverviewAnd Software Overview

Dave Harriman and Joe CowanDave Harriman and Joe CowanPCIe Protocol and Software PCIe Protocol and Software WorkgroupsWorkgroups

Today’s TopicsToday’s Topics

IntroductionIntroduction

Overview of changesOverview of changes

Completion Timeout ECNCompletion Timeout ECN

Function Level Reset ECRFunction Level Reset ECR

2.0 base spec link speed controls2.0 base spec link speed controls

Link Bandwidth Notification ECRLink Bandwidth Notification ECR

Access Control Services ECRAccess Control Services ECR

Trusted Config Space ECNTrusted Config Space ECN

IntroductionIntroduction

PCI-SIG updating PCI Express (PCIe) PCI-SIG updating PCI Express (PCIe) specifications this yearspecifications this year

Single largest change – Single largest change – 5gigabit/second (Gb/s) signaling speed5gigabit/second (Gb/s) signaling speed

Optional new capabilityOptional new capability

Several other improvementsSeveral other improvements

BaseBase .7.7 .9.9 2.02.0

Q1 06Q1 06 Q2 06Q2 06 Q3 06Q3 06

Today’s focusToday’s focus

Overview Of ChangesOverview Of Changes

Engineering Change Requests (ECRs),Engineering Change Requests (ECRs),Engineering Change Notices (ECNs), and ErrataEngineering Change Notices (ECNs), and Errata

ECRs become ECNs after review/approvalECRs become ECNs after review/approval

All ECNs and Errata included in 2.0 publicationAll ECNs and Errata included in 2.0 publication

Errata – highlightsErrata – highlightsRoot Complex Event Collector Base Class Code conflictRoot Complex Event Collector Base Class Code conflict

Clarifications of uncommon error casesClarifications of uncommon error cases

Register bit clarifications on defaults, Register bit clarifications on defaults, implementation requirementsimplementation requirements

Interrupt disable bit consistency with conventional PCI Interrupt disable bit consistency with conventional PCI

5Gb/s signaling speed not an ECN5Gb/s signaling speed not an ECNIncluded only in 2.0Included only in 2.0

Completion Timeout ECNCompletion Timeout ECN

Required: Architected disable bitRequired: Architected disable bit““Turns off” timeoutTurns off” timeout

Not to be used in normal operationNot to be used in normal operation

Optional Completion Timeout Optional Completion Timeout time value programmability time value programmability

Devices indicate supported ranges Devices indicate supported ranges from the four bins definedfrom the four bins defined

Two selectable ranges for each binTwo selectable ranges for each bin

4s to 64s

250ms to 4s

10ms to 250ms

50us to 10ms

Function Level Reset Function Level Reset (FLR) ECR(FLR) ECR

Background: New Background: New type of resettype of reset

Existing resets may Existing resets may (but not required to) (but not required to) reset function internalsreset function internals

FLR definition FLR definition requiresrequires function internal resetfunction internal reset

General concept: General concept: SW initiated SW initiated function-specific resetfunction-specific reset

RESET “FAMILY TREE”

FLRConventional

Cold / Warm(PERST#)

HotS.B.R.

Function Level Reset Function Level Reset (FLR) ECR(FLR) ECR

Endpoints onlyEndpoints onlyAll types: Legacy, All types: Legacy, Native, IntegratedNative, Integrated

Register interface simpleRegister interface simpleImplementation and effects Implementation and effects potentially complexpotentially complex

Resets internal Resets internal function-specific statefunction-specific state

Not all architected registers Not all architected registers are resetare reset

Hardware Initialized (HwInit), Hardware Initialized (HwInit), BIOS set, etc.BIOS set, etc.

F0F0 F1F1 F2F2PCIe PCIe EndpointEndpoint

FunctionFunctionResetReset

2.0 Base Link Speed Controls2.0 Base Link Speed ControlsExternal link speed management modelExternal link speed management model

By default, hardware automatically trains to the By default, hardware automatically trains to the greatest common speedgreatest common speed

Software can set an upper bound on the speedSoftware can set an upper bound on the speed

Hardware can always limit speed for Link reliabilityHardware can always limit speed for Link reliability

By default, hardware is permitted to change the By default, hardware is permitted to change the speed autonomously for other purposes, suchspeed autonomously for other purposes, suchas power managementas power management

Software can disable thisSoftware can disable this

There is a new mechanism supporting software There is a new mechanism supporting software control for entering/exiting Compliance Modecontrol for entering/exiting Compliance Mode

2.0 Base Link Speed Controls2.0 Base Link Speed ControlsNew/modified regs for external linksNew/modified regs for external links

Link capability registerLink capability registerMaximum Link SpeedMaximum Link Speed field renamed to field renamed to Supported Link SpeedsSupported Link Speeds

Link Status registerLink Status registerLink SpeedLink Speed field renamed to field renamed to Current Link SpeedCurrent Link Speed

(new) Link Control 2 register(new) Link Control 2 registerTarget Link SpeedTarget Link Speed field field

Hardware Autonomous Speed DisableHardware Autonomous Speed Disable bit bit

Enter ComplianceEnter Compliance bit bit

2.0 Base Link Speed Controls2.0 Base Link Speed ControlsRoot complex internal linksRoot complex internal links

Can report their supported and current Can report their supported and current speeds via similar changes to their speeds via similar changes to their Capability and Status registersCapability and Status registers

Speed is not controllable via Speed is not controllable via architected mechanismsarchitected mechanisms

Bandwidth Notification ECRBandwidth Notification ECRGeneralGeneral

MotivationMotivationNeed mech for PCIe-aware software to be notified whenNeed mech for PCIe-aware software to be notified whenLink bandwidth (speed or width) changes, due to hardware-Link bandwidth (speed or width) changes, due to hardware-autonomous link retrainingautonomous link retrainingCan help reduce vendor support costs by having software notify Can help reduce vendor support costs by having software notify users if marginal links retrain to a lower bandwidth, impacting users if marginal links retrain to a lower bandwidth, impacting system performancesystem performanceWant it available ASAP for all new PCIe components, not just Want it available ASAP for all new PCIe components, not just those supporting 5 Gb signalingthose supporting 5 Gb signaling

Though specified in separate document, still logically Though specified in separate document, still logically coupled with link speed controlscoupled with link speed controlsECR timing is somewhat tied to link speed ECR timing is somewhat tied to link speed controls stabilizingcontrols stabilizingPlan to make this a mandatory featurePlan to make this a mandatory featurefor PCIe Base 2.0 (optional for 1.1)for PCIe Base 2.0 (optional for 1.1)

Bandwidth Notification ECRBandwidth Notification ECRMechanism detailsMechanism details

Link capability registerLink capability registerLink Bandwidth Notification CapabilityLink Bandwidth Notification Capability bit bit

Link control registerLink control registerHardware Autonomous Width DisableHardware Autonomous Width Disable bit bit

Link Bandwidth Management Interrupt EnableLink Bandwidth Management Interrupt Enable bit bit

Link Autonomous Bandwidth Interrupt EnableLink Autonomous Bandwidth Interrupt Enable bit bit

Link status registerLink status registerLink Bandwidth Management StatusLink Bandwidth Management Status bit bit

Link Autonomous Bandwidth StatusLink Autonomous Bandwidth Status bit bit

Access Control Services (ECR)Access Control Services (ECR)GeneralGeneral

Set of access control services for downstream portsSet of access control services for downstream portsand functions in multi-function devicesand functions in multi-function devicesNew extended capability and status/mask/severityNew extended capability and status/mask/severitybits in AERbits in AERSource validation – downstream Ports range check Source validation – downstream Ports range check Requester ID BusNum in upstream Request TLPsRequester ID BusNum in upstream Request TLPsPeer-to-peer controls determine whether to forward Peer-to-peer controls determine whether to forward directly, block, or redirect peer-to-peer Request TLPsdirectly, block, or redirect peer-to-peer Request TLPsto the RC for access validationto the RC for access validationControls being considered for functionality definedControls being considered for functionality definedby the Address Translation Services ECRby the Address Translation Services ECR

Access Control Services ECRAccess Control Services ECRDetailsDetails

Applicable toApplicable toRoot ComplexesRoot Complexes

SwitchesSwitches

Multi-function devicesMulti-function devices

Planned servicesPlanned servicesSource ValidationSource Validation

P2P Redirect & P2P Redirect & Upstream ForwardingUpstream Forwarding

P2P Egress ControlsP2P Egress Controls

Translation Blocking (ATS)Translation Blocking (ATS)

Direct Translated P2P (ATS)Direct Translated P2P (ATS)

CPU

Root Complex

MFD 1MFD 1 EndEnd

pointpoint

22

EndEnd

pointpoint

33

Switch

Memory

EndEnd

pointpoint

44Fn0Fn0 Fn1Fn1

Trusted Config Space ECNTrusted Config Space ECN

ECR presented in detail ECR presented in detail at WinHEC 2005at WinHEC 2005

Final ECN completed in Final ECN completed in July 2005July 2005

No significant changes No significant changes before finalizedbefore finalized

Call To ActionCall To Action

Comprehend Upcoming PCIe 2.0 Base Comprehend Upcoming PCIe 2.0 Base spec improvementsspec improvements

Many enhancements in 2.0 besides 5 Gb/s Many enhancements in 2.0 besides 5 Gb/s signaling speed signaling speed

Start planning your 2.0 product nowStart planning your 2.0 product now

Keep in-sync with PCI-SIG for Keep in-sync with PCI-SIG for further updatesfurther updates

Additional ResourcesAdditional Resources

Web resources: Web resources: http://www.pcisig.comhttp://www.pcisig.comSpecs, white papers, and moreSpecs, white papers, and more