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The Executive and ProgramCommittees of the ElectronicComponents and TechnologyConference (ECTC) welcome youto our 54th meeting at CaesarsPalace in Las Vegas.
This premier internationalconference continues to bringtogether the best in packaging,components and microelectronic
systems science, technology and education in an environment ofcooperation and technical exchange.The technical sessions focuson leading-edge developments and technical innovations in severalareas, including: optoelectronics, advanced packaging technologies,high-performance package design, simulation and manufacturinginterconnections and reliability.
The 54th ECTC provides a wealth of opportunities for education,discussion and networking. In 2004, we will provide 16professional development courses, taught by leaders from industryand academia.This year’s conference has more than 325 papersorganized into 39 oral presentation sessions, plus two postersessions, which provide the opportunity to exchange ideas andinformation with today’s packaging technology leaders.This year,we are especially pleased to highlight papers in two special topicareas – MEMS and nanotechnology – as part of our ongoing effortto bring emerging technologies that have great future potentialtogether with key established packaging technologies. Formalsessions are complemented by informal evening sessions on avariety of topics of interest to packaging technologists.Thesesessions allow for extensive interaction with presenters and otherattendees.The Technology Corner offers companies theopportunity to exhibit their products and services in anenvironment that fosters discussion and interactions withengineers and managers attending the ECTC.
The ECTC depends on literally hundreds of skilled and dedicatedpersons each year for continued success.We extend our sincerestthanks to ECTC authors, speakers, instructors and exhibitors foryour contributions and participation.We are most grateful to theProgram Committee, Session Chairs and Co-chairs, those whomade the conference arrangements and handled the publicity andpublications.We thank the corporate coffee break and receptionsponsors for their generous contributions which allow us to offera high-quality technical program.
Finally we offer this conference program with pride andanticipation to all conference attendees. You are the reason forthe ECTC, and we look forward to your comments on whatwe’ve done well and where we can improve to raise the qualityand value of future conferences.
Patrick Thompson54th ECTC Program Chair
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IndexECTC Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Technology Corner Exhibits . . . . . . . . . . . . . . . . . . . . . . . . .4NEMI Tin Whisker Workshop . . . . . . . . . . . . . . . . . . . . . . . .4Plenary Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Luncheons and Receptions . . . . . . . . . . . . . . . . . . . . . . . . . .5Hotel Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Attractions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Executive & Program Committees . . . . . . . . . . . . . . . . . . .6,7Professional Development Courses . . . . . . . . . . . . . . . . .8-13Program Sessions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-27Hotel Registration Form. . . . . . . . . . . . . . . . . . . . . . . . . . . .28Corpora te Conference Sponsors . . . . . . . . . . . . . . . . . . . .28Conference Registration Form. . . . . . . . . . . . . . . . . . . . . . .29Conference Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Introduction from the 54th ECTC Program Chair Patrick Thompson
The 54th Electronic Components and Technology Conference (ECTC)Caesars Palace, Las Vegas, Nevada, June 1-4, 2004
Photograph courtesy of Las Vegas News Bureau
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Advance RegistrationTo register in advance for the 54th ECTC, your applicationand payment check/credit card information must be receivedno later than May 15, 2004. Complete and submit the onlineregistration form (preferred registration) at:www.ectc.net/reg.htm, mail to the address on the AdvanceRegistration Form on page 31, or fax your form with paymentinformation to (703) 875-8908.
Register early … save $100. All applications received afterMay 15, 2004 will be considered Door Registrations. Thosewho register in advance can pick up their registration packetsat the ECTC Registration Desk in the Prefunction Area, 4thFloor at Caesars Palace. Additional Advance Programs areavailable from:
Jim Bruorton, Publicity Chairman 54th Electronic Components & Technology Conference c/o KEMET Electronics CorporationP.O. Box 5928Greenville, SC 29606Phone: (864) 963-6621 Fax: (864) 963-6444Email: [email protected]
DO NOT SEND ADVANCE REGISTRATIONS TOTHE ABOVE ADDRESS. SEE REGISTRATION FORMON PAGE 29.
Registration FeesAdvance Registration with proceedings (CD or printed),
CTC, CPMT and Program Chair Luncheons . . . . . .*$600Door Registration with proceedings (CD or printed),
ECTC, CPMT and Program Chair Luncheons . . . . .*$700One Day Registration . . . . . . . . . . . . . . . . . . . . . . . . .$375Speaker/Session Chair (Door Rate $500) . . . . . . . . . .$400Speaker/One Day . . . . . . . . . . . . . . . . . . . . . . . . . . . .$250Student Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$150Student (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$150Tuesday Single AM or PM Courses with Luncheon . .#$350Tuesday AM & PM Courses with Luncheon . . . . . . . .#$550 Student Tuesday All-Day Courses . . . . . . . . . . . . . . . . .$75Joint ECTC/ITHERM Advance . . . . . . . . . . . . . . . . . . .$750Joint ECTC/ITHERM Door . . . . . . . . . . . . . . . . . . . . .$800NEMI Workshop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$75Proceedings only, U.S. Postpaid . . . . . . . . . . . . . . . . . .$300
Foreign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$350
* IEEE Member - Advance/$500, Door/$600# Door rate will be an additional $50(1) Students receive CD Rom.
Note: There will be no refunds on cancellations madeafter May 15, 2004.
At Door Registration ScheduleRegistration will be held at the Prefunction Area (4th Floor) asfollows:
Monday, May 31, 2004 – 3:00 to 5:00 PM (PD Courses & Conference)Tuesday, June 1, 2004 – 6:45 to 8:00 AM (AM PD Courses Only)Tuesday, June 1, 2004 – 11:00 AM to 1:15 PM (PM PD Courses Only)Tuesday, June 1, 2004 – 1:15 to 5:00 PM (Conference)Wednesday, June 2, 2004 – 6:45 AM to 4:00 PMThursday, June 3, 2004 – 7:30 AM to 4:00 PMFriday, June 4, 2004 – 7:30 AM to 12:00 PM
General InformationConference organizers reserve the right to cancel or changethe program without prior notice.
Loss Due to TheftConference management is not responsible for loss or theftof personal belongings. Security for each individual’sbelongings is the individual’s responsibility.
Coffee Break SponsorsSponsorships are available for companies that would like toparticipate in the 2004 Electronic Components andTechnology Conference by assisting in sponsoring theconference breaks. Your company’s name will be included inthe conference final program and will be displayed on a sign inthe refreshments area. A table will be provided nearby todisplay limited promotional/informational material about thecompanies sponsoring breaks. To sign up to sponsor a coffeebreak, simply indicate your interest on the ConferenceAdvance Registration form (page 29) and enclose the $350sponsorship fee, payable to the 54th Electronic Componentsand Technology Conference.
Please note: Sponsorships must be prepaid, and must be received atleast four weeks before the conference in order to be listed in theFinal Program. For further information, call EIA (703) 907-8027.
54th ECTC Advance Registration
55th Electronic Componentsand Technology Conference
Wyndham PalaceLake Buena Vista, Florida
May 31 - June 3, 2005Make plans now to join us!
The above schedule for Tuesday will be rigorously enforcedto prevent students from being late for their courses.
Although the current economic climate in theelectronics industry is improving, companies are stillbeing selective in choosing the conference and tradeshows where they will exhibit their products andservices. Each year more companies havedetermined that ECTC provides them theopportunity to identify superior prospects. Theprimary reason is that the engineers and managerswho attend ECTC hold decision-making positions atthe world’s leading electronics industry’s equipmentand components manufacturers. The attendees areattracted by ECTC’s strong technical program.Authors in the field believe that ECTC offers the bestforum for presenting their work.
Exhibit hours will be from 1:30 to 6:30 PM onWednesday, June 2 and 9:00 AM to Noon and 1:30to 6:00 PM on Thursday, June 3. Exhibit spaces arestill available. Following is a list of exhibitors as ofFebruary 2, 2004. The exhibit application, a currentexhibitor list and the booth layout showing theavailable booths can be found on the ECTC web siteat www.ectc.net under Technology Corner Exhibits.If you need additional information or have questions,call Bill Moody at (302) 478-4143, or [email protected].
3M Electronics Markets Materials Div.3M Microinterconnect Systems Div.
Advanced Packaging MagazineAnsoft Corporation
ANSYS, Inc.Asymtek
Bergquist Company (The)Ceramics Process Systems Corp.
Chip Scale ReviewChip Supply, Inc.
Dow Chemical Co., (The)Dow Corning Corporation
Electronics Cooling MagazineEmerson & CumingEnerdyne Solutions
ENGENT, Inc.Epoxy Technology, Inc.ESPEC Corporation
Fluent Inc.HD Microsystems
Henkel Loctite CorporationHitachi Cable America, Inc.
Indium Corporation of AmericaInnovative Research, Inc.
Interconnect Systems Inc.KEMET Electronics Corporation
Kyocera America, Inc.Matec Micro Electronics
Mini-Systems, Inc.Mitsui Chemicals America, Inc.
NAMICS Technologies, Inc.National Semiconductor Die Products
Optimal CorporationPac Tech Gmbh
PRC (Georgia Tech)Rotys, Inc.
Semi Dice, Inc.Semiconductor International
SIGRITY, Inc.Sony Chemical Corp. of America
SUSS MicroTecTechSearch International, Inc.
Temptronic CorporationThermagon, Inc.
Toray Engineering Co., Ltd.Unitive, Inc.
Vishay Intertechnology, Inc.Zymet, Inc.
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ECTC NEMI Tin Whisker Workshop Tuesday, June 1, 2004 –8:30AM - 5:00PMCourse Director: Ron Gedney
With the move toward Pb-free electronics, a popular finish forcomponent terminations is 100% tin (Sn). However, pure Sncoatings have a tendency to grow small filaments, popularlycalled “whiskers,” that can bridge adjacent terminals, causingsystem failures. The National Electronics ManufacturingInitiative (NEMI) formed three projects to work on thisphenomenon:Accelerated Test (to develop accelerated tests topredict tin whiskers); Modeling (to understand basic cause ofwhiskers); and User Group (to determine how high-reliability,long-life systems can be protected with today’s knowledge).This workshop will provide an overview of more than threeyears’ work investigating all aspects of tin whiskers from allthree projects. Attendees will get a good overview of tinwhiskers, a set of tests recommended to JEDEC, basic theoriesbehind whisker formation, and how to protect system reliabilitygiven what we know today.
Technology Corner Exhibits
ECTC Plenary SessionHigh-Density InterconnectionWednesday, June 2, 2004 – 7:00 - 9:00 PM
Chair: Yoshitake Fukuoka – WeistiCochair: Kishio Yokouchi –
Fujitsu Laboratories of America, Inc.
1. Recent Advances in Materials, Processes and High-Density Structures at GT-PRCVenky Sundaram and Rao R.Tummala – Georgia Institute of Technology
2. Dielectric Materials for High-Density Interconnect TechnologyMasahiro Ito and Shunsuke Yokotsuka – Asahi Glass Co., Ltd.
3. Recent Advances in Materials, Processes and High-Density Structures at GT-PRCVenky Sundaram and Rao R.Tummala – Georgia Institute of Technology
4. Advanced Technology for High-Density Substrate and BoardsYasuhito Takahashi – Fujitsu Microelectronics America, Inc.
5. High-Density and High-Frequency Silicon Substrate Technology for SiPAtsushi Takano – Dai Nippon and Yoshitake Fukuoka – Weisti
6. Passive and Active Components Embedding Technology for High-Density SubstrateMasaaski Katsumata – Matsushita Electronic Components Co., Ltd.
7. A consideration for Total Mechanical Stress in Flip-Chip Packaging Utilizing Buildup Substrate TechnologyYutaka Tsukada – Kyocera SLC Technologies Corporation
Photograph courtesy of Las Vegas News Bureau
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LuncheonsProfessional Development Course and NEMI Workshop LuncheonThe Electronic Components and Technology Conference willsponsor a luncheon on Tuesday, June 1st, for all ProfessionalDevelopment and NEMI Workshop attendees.
ECTC LuncheonThe Electronic Components and Technology Conference willsponsor a luncheon on Wednesday, June 2nd, for conferenceattendees.
CPMT LuncheonThe IEEE Components, Packaging and ManufacturingTechnology Society will sponsor a luncheon for conferenceattendees on Thursday, June 3rd.
Program Chair LuncheonOn Friday, June 4th, the Program Chair will sponsor aluncheon for conference attendees.
Hotel AccommodationsRooms for ECTC attendees have been reserved at CaesarsPalace.The special conference rate is $165 for Run of Houseand $199 for Palace Tower Rooms.There are 2,500 roomsand suites, three spacious casinos, four lounges, nineteenrestaurants, a health spa, a fitness center, three swimmingpools, an Omnimax theatre, and the Appian Way and ForumShops available to you for greater luxury and comfort duringyour stay.
Room reservations must be made directly with the hotel byApril 29, 2004 to ensure special convention rates. If you needto change or cancel your reservation, please do so prior to
three (3) days or 72 hours before arrival date to avoidforfeiture of deposit. Check-in time is 3:00 PM and check-outtime is 12:00 PM. Most major credit cards are accepted. Callfor booking assistance today at (702) 731-7222 or 800-634-6661 and mention ECTC for discounted rates or fax (702)731-7172.
Area AttractionsThere is plenty to see and do in Las Vegas.You can start atone end of the strip and stop at every hotel to do somethingdifferent.Adventuredome Theme Park is located at CircusCircus offering 21 rides and attractions. Free circus acts areperformed daily inside.The Eiffel Tower located at the ParisHotel offers the 50-story tower to take a panoramic view ofthe Las Vegas Valley. Shopping has not been forgotten either.The Forum Shops and the Appian Way are located at CaesarsPalace along with the famous Roman statues that come tolife at the Festival Fountains.The Bellagio Hotel is the placeto see dancing fountains that are choreographed to music byartists such as Frank Sinatra, Elton John, Henry Mancini andmore. If you want to go to the beach in the middle of thedesert, stop at Mandalay Bay. Enjoy a swim, then visit theaquarium.Treasure Island and the pirates are great fun foreveryone.The Mirage’s 54-foot volcano eruption every 15minutes from dusk to midnight is always exciting.
Just 30 miles from Las Vegas on Highway 93 is the HooverDam and Power Plant that was built in 1937.The VisitorCenter is open from 9:00AM to 5:00PM. Close to 1,000,000visitors a year visit this National Historic Landmark.Ticketsare $10 each for adults ($8 Seniors), children 7 - 16 are $5and children 6 and under are free.What a great family trip!
54th ECTC Gala ReceptionAll badged attendees and guests are invited to
attend a reception hosted by AVX Corporation,KEMET Electronics Corporation,
KOA Speer Electronics, Inc., Murata ElectronicsNorth America, ROHM Electronics USA,
and Vishay Intertechnology, Inc.on Thursday, June 3rd at 6:30 PM.
General Chair’s SpeakersReception
Tuesday, June 1, 20046:00 PM - 7:00 PM(by invitation only)
Photograph courtesy of Caesars Palace
ExecutiveCommittee
Steve BezukGeneral ChairKyocera America, Inc.+1-858-576-2651
Donna NoctorVice-General ChairECTC Consultant+1-208-978-9425
Patrick ThompsonProgram ChairTexas Instruments, Inc.+1-972-995-7660
Eric PerfectoAsst. Program ChairIBM Microelectronics+1-845-894-4400
Peter J.WalshArrangements ChairEIA/ECA+1-703-907-8028
Michael B. McShaneSr. Past General ChairMotorola, Inc.+1-512-996-6175
Wayne J. HowellJr. Past General ChairIBM Corporation+1-845-892-5360
Thomas G. Reynolds, III Finance ChairMurata Electronics NA, Inc.+1-850-897-7323
Glyndwr Smith,EIA/ECA RepresentativeVishay Intertechnology, Inc.+1-610-251-5274
C. P.WongIEEE/CPMT RepresentativeGeorgia Institute of Technology+1-404-894-8391
Albert PuttlitzProfessional Development Course ChairMechanical Engineering Consultant+1-802-899-4692
James A. BruortonPublicity ChairKEMET Electronics Corporation+1-864-963-6621
John H. LauPublications ChairAglient Technologies, Inc.+1-408-553-2358
Advanced Packaging Jeffrey A. Knight, ChairIBM Corporation +1-607-757-1105
Sudipta K. Ray, Co-ChairIBM Microelectronics+1-845-894-6240
Daniel BaldwinGeorgia Institute of Technology+1-404-894-4135
Karla Y. CarichnerConexant Systems+1-949-483-9151
Tim ChenIntel Corporation+1-480-552-8712
Altaf HasanIntel Corporation+1-430-554-3427
Douglas HopkinsSUNY Buffalo Energy Systems Institute+1-607-729-9949
Satoshi ItoNitto Denko Corporation+81-532-43-1802
Beth KeserMotorola, Inc.+1-480-413-8022
Young-Gon KimTessera+1-408-383-3685
Yee L. LowLucent Technologies+1-908-582-2718
Raj N. MasterAMD+1-408-982-7023
Gary MorrisonTexas Instruments, Inc.+1-972-995-4851
Luu T. NguyenNational Semiconductor Corp.+1-408-721-4786
Thomas NollDow Corning Corporation+1-989-496-1506
Raj PendseChipPAC, Inc.+1-510-979-8330
Sudipta K. RayIBM Microelectronics+1-845-894-6240
Joseph W. SoucyDraper Laboratory, Pkg. Group+1-617-258-2953
E. Jan VardamanTechSearch International, Inc.+1-512-372-8887
Tiao ZhouTexas Instruments, Inc.+1-214-567-2736
Components & RF Leonard W. Schaper, ChairUniversity of Arkansas+1-479-575-8408
Eric Michelson, Co-ChairVishay Intertechnology, Inc.+1-610-251-5279
Amit P.AgrawalBroadcom Corporation+1-408-922-7332
Rao BondaMotorola, Inc.+1-480-413-6121
Craig GawMotorola, Inc.+1-480-413-5920
Lih-Tyng HwangMotorola, Inc.+1-847-576-5182
Mahadevan K. IyerInst. of Microelectronics+65-770-5424
Timothy G. LenihanConsultant+1-847-599-4100
Li LiMotorola, Inc.+1-480-413-6653
Albert F. PuttlitzMechanical Engineering Consultant+1-802-899-4692
Thomas G. Reynolds, IIIMurata Electronics NA, Inc.+1-850-897-7323
Manos M.TentzerisGeorgia Institute of Technology+1-404-385-0378
Education Paul Wesling, ChairConsultant+1-408-252-9051
Leyla Conrad, Co-ChairGeorgia Institute of Technology+1-404-385-0439
Avram Bar-CohenUniversity of Maryland+1-301-405-3173
William BrownUniversity of Arkansas+1-479-575-6045
Jim MorrisPortland State University+1-503-725-9588
Albert F. PuttlitzMechanical Engineering Consultant+1-802-899-4692
Andrew A. O.TayNational University of Singapore+65-6874-2207
Klaus-Jurgen WolterTechnische Universitat Dresden+49-351-46336345
Interconnections Rajen Dias, ChairIntel Corporation+1-480-554-5202
David McCann, Co-ChairAmkor Technology, Inc.+1-480-821-5000, x5029
Haluk BalkanKulicke and Soffa+1-602-431-6020 x464
Mark V. BrillhartCisco Systems Inc.+1-408-525-7466
William ChenASE-US Inc.+1-408-986-6505
Yifan GuoSkyworks Solutions, Inc.+1-949-231-4796
Dev GuptaAdvanced Packaging & SystemsTechnology+1-480-540-3232
Christine KallmayerTechnical University of Berlin+49-30-46403-228
Sung K. KangIBM - TJ Watson Res. Center+1-914-945-3932
Corey KoehlerAmkor Technology, Inc.+1-480-821-2408 x5373
Charles LeeInfineon Technologies AP+65-6840-0448
Jong-Kai LinMotorola, Inc.+1-480-413-3254
Voya MarkovichEndicott Interconnect Technologies+1-607-755-1978
Goran MatijasevicUniveristy of California, Irvine+1-949-824-9830
Lei L. MercadoMotorola, Inc.+1-480-552-1383
Dennis OlsenConsultant+1-480-994-9926
Kanji OtsukaMeisei University+81-428-25-5214
Prema PalaniappanEricsson Inc.+1-919-472-1922
Senol PekinLSI Logic+1-408-552-4898
Wolfgang SauterIBM Microelectronics+1-802-769-3634
Lei ShanIBM T. J.Watson Research Center+1-914-945-2304
Sue TengCisco Systems, Inc.+1-408-853-2527
Jin YuKorea Advanced Institute of Science andTechnology+82-42-869-8841
Manufacturing Technology Tom Swirbel, ChairMotorola, Inc.+1-954-723-5671
Tom Poulin, Co-ChairAerie Engineering+1-909-248-1237
Sharad BhattShanta Systems Inc.+1-814-362-6996
6
7
Douglas E. ChrzanowskiIBM Corporation+1-607-755-1403
David KeezerGeorgia Institute of Technology+1-404-894-4741
Claude LadouceurIBM Canada, Ltd.+1-450-534-7314
Kitty PearsallIBM Corporation+1-512-838-7004
Shawn ShiIntel Corporation+1-480-554-2155
Jie XueCisco Systems, Inc.+1-603-896-5337
Materials & Processing Chin C. Lee, ChairUniversity of California, Irvine+1-949-824-7462
Ceferino Gonzalez, Co-ChairDuPont Advanced Fibers Sys.+1-919-248-5062
Rajen ChanchaniSandia National Labs+1-505-844-3482
Phil GarrouDOW at MCNC+1-919-248-9261
Chandra JayaramIntel Products (M) Sdn. Bhd.+604-253-5289
Vaidyanathan KripeshInstitute of Microelectronics+65-6770-5592
Yeong J. LeeDow Corning +1-989-496-7032
Ming LiThe Chinese Unviersity of Hong Kong+852-31634129
Kwang-Lung LinNational Cheng Kung University+886-6-2762709
Johan LiuChalmers Univ. of Technology+46-31-706-6294
Daoqiang (DQ) LuIntel Corporation+1-480-552-2909
Jim MorrisPortland State University+1-503-725-9588
Kyung-Wook PaikKorean Advance Institute of Science andTechnology+82-42-869-3335
Eric PerfectoIBM Microelectronics+1-845-894-4400
Mark PoliksEndicott Interconnect Technologies+1-607-755-2064
C.P.WongGeorgia Institute of Technology+1-404-894-8391
Modeling & Simulation Suresh K. Sitaraman, ChairGeorgia Institute of Technology+1-404-894-3405
Michael Lamson, Co-ChairTexas Instruments+1-972-995-2490
W. Scott BurtonAgilent Technologies, Inc.+1-970-288-1186
Andreas CangellarisU. of Ilinois at Urbana-Champaign+1-217-333-6037
Moises CasesIBM Corporation+1-512-838-6225
Steve DvorakUniversity of Arizona+1-520-621-6170
L. J. ErnstDelft University of Technology+31-15-278-6519
George A. KatopisIBM Corporation+1-914-435-6719
Ravi KawAgilent Technologies, Inc.+1-408-345-8893
Bruce KimArizona State University+1-480-965-3749
Pradeep LallMotorola, Inc.+1-847-538-9885
Erdogan MadenciUniversity of Arizona+1-520-621-6113
Tony MakDallas Semiconductor Corporation+1-972-371-4364
John L. PrinceUniversity of Arizona+1-520-621-6187
Tawfik Rahal-ArabiIntel Corporation+1-503-613-5903
Madhavan SwaminathanGeorgia Institute of Technology+1-404-894-3340
G.Q. (Kouchi) ZhangPhilips+31-40-273-3825
OptoelectronicsJames E.Watson, Chair3M Company+1-651-733-3890
Torsten Wipiejewski, Co-Chair (N.Am.)ASTRI+852-3406-2894
Yasuhiro Ando, Co-Chair (Asia)Sigma-Links Inc.+81-426-62-0853
Sue Law, Co-Chair (Australia)Australian Photonics/OFTC +61-2-9351-1960
Mario DagenaisUniversity of Maryland+1-301-405-3684
Mino F. DautartasConsultant+1-540-953-2160
Jon HallBookham+44-1327356737
Randy HeylerNewport Corporation+1-949-253-1657
Masataka ItoInterIntelligence, Inc.+1-310-768-2900
Soon JangNewport Corporation+1-949-253-1625
Harry G. KellziTeledyne Electronic Technologies+1-310-574-2097
Michael LebbyIgnis Optics, Inc.+1-408-896-8484
Graeme MaxwellConsultant+44-1473-278258
Alan J. MorrowBinOptics Corporation+1-607-257-3200 X236
Bill RingTyco Electronics - Fiber OpticBusiness Unit+1-908-704-6605
Andrew ShapiroUniversity of California, Irvine+1-949-824-8086
Dariusz SieniawskiAchray Photonics+1-613-823-2211
Ephraim SuhirUniv. of IL at Chicago and ERS +1-650-969-1530
Christopher D.TheisAgere Systems+1-484-397-2964
Jean TrewhellaIBM T. J.Watson Research Center+1-914-945-2786
Ping ZhouGeneral Optoelectronic Devices, Inc.+1-818-735-7823
Posters Michael Caggiano, ChairRutgers Univ. Dept. of Elec. & ComputerEngineering+1-732-445-0678
Swapan Bhattacharya, Co-ChairGeorgia Institute of Technology+1-404-385-0708
Gerry CaggianoConsultant+1-928-704-1613
Mark EblenKyocera America, Inc.+1-858-614-2537
Lara MartinMotorola, Inc.+1-954-723-6959
Professional Development CoursesRonald E. Scotti, ChairConsultant+1-908-534-2039
Albert F. Puttlitz, Co-ChairMechanical Eng. Consultant+1-802-899-4692
Rao Bonda, Co-ChairMotorola, Inc.+1-480-413-6121
Quality & Reliability Charles Zhang, ChairIntel Corporation+1-480-552-0453
Darvin R. Edwards, Co-ChairTexas Instruments, Inc.+1-972-995-3569
Jo CaersPhilips Electronics Singapore +65-6357-9370
Sridhar CanumallaNokia Mobile Phones+1-469-767-9808
Harry K. CharlesThe Johns Hopkins Univ APL+1-443-778-8050
George HarmanNIST+1-301-975-2097
Xiaoling HeUniversity of Wisconsin, Milwaukee+1-414-229-6772
Donna M. NoctorConsultant+1-208-978-9425
John H. L. PangNanyang Technological University+65-6790-5514
Jeffrey SuhlingAuburn University+1-334-844-3332
Patrick ThompsonTexas Instruments, Inc.+1-972-995-7660
Charles UmeGeorgia Institute of Technology+1-404-894-7411
Dongji XieFlextronics International+1-408-576-7597
Special TopicsErik JungFraunhofer Institute for Reliability andMicrointegration+49-30-46403-230
S.W. Ricky LeeHong Kong University of Science &Technology+852-2358-7203
Michael B. McShaneMotorola, Inc.+1-512-996-6175
Rao R.TummalaGeorgia Institute of Technology+1-404-894-9097
C.P.WongGeorgia Institute of Technology+1-404-894-8391
ProfessionalDevelopment CoursesJune 1, 2004Albert F. Puttlitz, ChairConsultantPhone: (802) 899-4692Fax: (802) 899-4692Email: [email protected]
Ronald E. Scotti, Co-ChairConsultantPhone: (908) 534-2039Email: [email protected]
Rao Bonda, Co-ChairMotorola, Inc.Phone: (480) 413-6121Email: rao.bonda@motorola. com
MORNING COURSES8:15 AM – 12:00 PM
1. OPTOELECTRONICSCOMPONENTS AND MODULES FOR
COMMUNICATION NETWORKSInstructor: Bill Ring
Tyco Electronics
Course Objectives:Optoelectronics components and modules forthe communications industry and networks arecontinuously advancing in terms of speed, lowercost and design for high volume manufacture.The objectives of this course are to provide abackground on the current industry activecomponents and packaging approaches andreview the direction of active devices andpackaging technology for discrete componentsand data network modules. The course willcover the fundamentals of active III-V devices,manufacturing of components and transceiversfor the communications industry.
Course Outline:• Overview of communication requirements• Brief overview of semiconductor devices for
active communications devices• FP and DFB directly moduled lasers• VCSEL device for datacommunications• Packaging technology for communication
components• Low-cost plastic optics based packaging• TO-style packaging & high-speed
RF packaging• Reliability of components• Silicon optical bench technology• Modules for datacom
• SFF and SFP datacom modules• 10 Gigabit ethernet transceivers• Parallel module technology
Who Should Attend:This course is intended for engineers andmanagers who are involved in the design ofcomponents and modules for communicationnetworks. It will be beneficial for those whorequire a fundamental understanding and broadperspective on active components for LAN, SANOI connection and telecom modules, specificallytechnology, and manufacturing issues.
2. ADVANCED ORGANIC SUBSTRATEPACKAGE DESIGN &
MANUFACTURING FOR RF ANDBROADBAND
Instructor: Hassan Hashemi Mindspeed Technologies, Inc.
Course Objectives:The objectives of this course are to reviewdesign and manufacturing practices and tradeoffsaffecting current and next-generation wirelessand broadband IC packaging using laminatesubstrate technologies in single or multiple dieformat.The course material is based upon theinstructor's experience in current micro-modules designed for GHz IC packaging forwireless and wireline communication andstorage area networking applications.
Course Outline:• Review design and manufacturing practices
and tradeoffs• Ceramic versus laminate substrate-based
packaging- Micro-module design features with
chip-on-board and surface mount technologies
- Design tradeoffs for high volume manufacturing
- Laminate module electrical, thermal,and mechanical design features
- Laminate package materials• Example package design considering
performance, cost & manufacturing - Embedded passives in laminate substrates
• Organic substrate package assembly overview- Die attach, wire bond, overmold,
saw & singulation- Process tolerances and their
effects on performance• Conclusions
Who Should Attend:Engineers and technical managers who areinvolved in the design and manufacturing ofelectronic components and modules for wirelessand broadband networking or storage
applications. Attendees will learn aboutmaterials, processes, and design practices usedfor wirebond ICs, SMDs, and organic substratemodules used in high volume RF/GHz IC andsystem packaging.
3. INTEGRATED PASSIVETECHNOLOGY AND
COMMERCIALIZATIONInstructor: Richard Ulrich
University of Arkansas
Course Objectives:This course will be a comprehensive review ofpotential applications, commercializedtechnology, and possible future directions inintegrated passive components and processingfor organic boards. The organization of thecourse centers on the benefits and problemswith their implementation in order to helppotential users make decisions about theirapplicability in a given situation. Considerabletime will also be spent on the candidatematerials and processes for integrated resistors,capacitors and inductors in order to help thepotential user decide what processes canprovide the needed electrical performance whilebeing compatible with their existing substratesand fabrication technology. Emphasis will also beplaced on electrical testing, since users ofintegrated passives will find themselves in thebusiness of producing passive components, notjust buying them, since the electricalperformance characteristics of integratedpassives can be very different from their surface-mount counterparts, possibly providing significantcompetitive advantages. Several currentpotential applications will be described, withparticular emphasis on decoupling. The courseemphasizes applicability to manufacturedmicroelectronic systems and includes theoreticalmaterial necessary to support that purpose.
Course Outline:• Why use IPs?• Substrates of interest• Integrated resistors• Integrated capacitors• Integrated inductors• Electrical measurement of integrated
passives• Applications favorable for integrated
passives• Economics of IPs• Tolerance, repeatability and yield issues• Commercialized systems• Where are integrated passives going?
Who Should Attend:Engineers and scientists involved in electronicspackaging, circuit board manufacture, electricaldesign and passive component technologies.
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4. POLYMERS FOR ELECTRONICPACKAGING
Instructor: C. P. WongGeorgia Institute of Technology
Course Objectives:Polymers are widely used in electronic packagingas adhesives, encapsulants, insulators, dielectrics,molding compounds and conducting elementsfor interconnects. These materials also play acritical role in the recent advances of low-cost,high performance novel no flow underfills,reworkable underfills for ball grid array (BGA),chip scale packaging (CSP), system on a package(SOP), direct chip attach (DCA), flip chip (FC),paper-thin IC and 3D packaging, conductiveadhesives (both ICA and ACA), embeddedpassives and nano-functional materials. It isimperative that material suppliers, formulatorsand their users have a thorough understandingof polymeric materials and their importance inthe advances of the electronic packaging andinterconnect technologies.
Course Outline:• Overview of semiconductor packaging
technology• Next generation of electronic packaging• Common electronic packaging materials:
conformal coating, glob-top, potting and casting
• Novel no-flow, advanced and reworkable underfills for flip-chip applications
• Conductive adhesives for lead-free interconnects – fundamentals and recent advances
• Low-cost high-performance embedded passives materials and processes
• Recent advances on nano photonic and low dielectric (k) materials and nano-functional materials
Who Should Attend:Engineers, scientists and managers involved in thedesign, process and manufacturing of ICelectronic components and hybrid packaging,electronic material suppliers involved in materialsmanufacturing and research and development.
5. SYSTEM-ON-PACKAGE (SOP) VS.SYSTEM-IN-PACKAGE (SIP),AND
SYSTEM-ON-CHIP (SOC)New Paradigms in Electronics
Instructor: Rao TummalaGeorgia Institute of Technology -
Packaging Research Center
Course Objectives:This course presents an overview of the GeorgiaTech Packaging Research Center's SOP (System-on-Package) vision for highly integrated andmicrominiaturized convergent systems with
consumer, computer, communication and bio-medical functions implementing an integratedapproach to digital, analog, RF, optical and sensingtechnologies. The SOP paradigm changes thecurrent chip-centric SOC methodology to acheaper, faster-to-market IC-package co-design-centric microsystems packaging design andtechnology flow. The advantages of the SOPparadigm over SOC appear overwhelming dueto SOP's design simplicity, lower cost, and higherelectrical performance, and without theintellectual property issues that dominate SOC.To realize these enormous advantages, new SOPsub-technology paradigms are required. Theseinclude mixed-signal design, ultra high-densityembedded digital, embedded optoelectronics andembedded RF component integration as well aswafer level packaging (WLP) and assembly, testand burn-in, thermal management and systemreliability. A key technology paradigm, whichGeorgia Tech has been developing with theNational University of Singapore, is the conceptof nanoscale WLP, testing and burn-in, whichpromises ultimate size miniaturization, andvirtually unlimited interconnections by means ofnanoscale interconnections. This course makes acompelling case for and presents the status ofSOP R&D around the world and compares andcontrasts with SOC, SIP and MCM.
Course Outline:• System trends to convergent systems• Semiconductor trends to SOC• IC and systems packaging evolution• Five approaches to convergent systems• What is SOP, and why?• Global developments of SOP• Comparison of SOC, SIP, MCM and SOP• Status of SOP technologies• What next after SOP?
Who Should Attend:This course is an overview course and is suitablefor all levels of R&D management, seniorengineers and executives involved in technicalstrategy, R&D, design, manufacturing, process andproduct development of electronic packagingand systems in automotive, consumer,communication, computer, biomedical, andaerospace industries.
6. "NANO" - THE NEXTTECHNOLOGY?
Overview of Nano-TechnologyInstructors: Walter Trybula
International SEMATECH and Deb Newberry
Newberry Technologies
Course Objectives:Nano is the catchall phrase that is used to implysome super advanced technology. Everyone has
a different idea of what it means. Thisintroduction to nano-technology will provide anoverview of various aspects of nano includingbio-tech and electronics. Nano-technologystarted with the carbon Buckyballs, which consistof 60 carbon atoms formed in a sphere.Stretching the Buckyballs creates carbonnanotubes. Nanotubes have low resistance,which has given rise to some predictions of gridsof nanotubes for carrying electrical signals.Starting with the Buckyballs more than 20 yearsago, the technology has grown exponentially.The explosion of new applications has occurredin the last few years and has become the centerof businesses’ attention in a search for new areasof expansion. There is a need to understandwhat this new technology really is. This courseprovides an explanation of basics of nano-technology. The purpose is to give the attendeesan overview of potential applications and anunderstanding of some of the complexities ofdeveloping nano-technology products.
Course Outline:• Introduction to nano (including
what is nano?) • An overview of nano-bio • Specific benefits • Business requirements • Packaging potential• Economics and world competition• The future and the challenges• Where do we go from here?
Who Should Attend:This introductory course is focused on peoplewho desire a better understanding of thedeveloping field of nano-technology. It will alsobe of interest to people who need to becomeinvolved in business dealing with nano-technology.
7. MICROELECTRONIC AND MEMS SENSORS
Instructors: Gábor Harsányi andZsolt Illyefalvi-Vitez
Budapest University of Technology andEconomics
Course Objectives:The course provides participants with anoverview of microsensors, i.e. miniature devicesfor measuring physical and chemical quantitiessuch as pressure, acceleration, speed, chemicalconcentration, etc. Microsensors fabricated bysolid-state and MEMS technology, from ceramics,thin and thick films, polymer films, as well as byoptical fiber technology are described andcharacterized.The different sensor structures inuse, the most important sensing effects, as wellas the principles of sensing various parametersare presented.The overview of application fieldsincludes industrial process control, automotive
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and household case studies, with a special focuson environmental monitoring and biomedicalapplications. Advances in sensor packaging,modeling, design and fabrication are alsodescribed shortly. The presentation will use themagnificent virtual tools of SensEdu andMEMSEdu, which are tools developed as a CPMTinitiative in the frame of IEEE/NSF facultyfellowship program.
Course Outline:• Sensor technologies and materials:
- Solid-state semiconductor and ceramic technologies
- Thin and thick film, polymer film, and optical fiber based sensor technologies
• Sensor structures, basic models of sensor operations:- Impedance type sensors, semi-
conductor devices, calorimetric sensors, electrochemical cells
- Sensors based on acoustic wave propagation, sensors with optical waveguides
• Sensing effects, basic principles of microsensors:- Thermoresistive, thermoelectric,
piezoelectric, pyroelectric,piezoresistive, Hall effect
- The principle of adsorption and the absorption of chemical species;selective molecular receptors
- Permeation through membranes,ion-selective membranes, chemical-optical transduction effects
• Sensing various parameters:- Sensors for mechanical parameters,
such as pressure, force, acceleration,angular displacement
- Thermal, acoustic, radiation, magnetic field, chemical sensors and biosensors
• Application fields: overview and case studies- Industrial process control,
automotive, household- Environmental monitoring and
biomedical applications
Who Should Attend:The course is designed for electrical, mechanicaland chemical engineers, physicists, technicalmanagers, salesmen and students who wish toget a comprehensive overview of microsensors’operation principles and characteristics, and tolearn more about their applications. The coursefocuses on practical aspects and addresses fieldengineers and technicians from companies aswell.
8. MICROELECTRONICS PACKAGINGAND INTERCONNECTION - AWORLDWIDE PERSPECTIVE
Instructor: E. Jan Vardaman TechSearch International Inc.
Course Objectives:This course will cover developments and trendsin area array packages. Ball grid array (BGA)packages are increasingly found in productsincluding personal computers, portablecommunications devices, workstations/servers,mid-range and high-end computers, network andtelecommunications systems, and evenautomotive applications. Package trends andnew developments are described. Driven by thedemand for smaller, lighter, thinner portableproducts has come the development of chipscale packages (CSPs). Discussed are the varioustypes of CSPs in volume production and newdevelopments such as wafer level packages. Flipchip's advantage over wire bond interconnectionincludes higher density mounting, improvedelectrical performance, and improved reliabilityfor many applications. New applications for flipchip are described. Also included are trends,such as bump pitch, bump metallurgy, andsubstrate feature sizes.
Course Outline:• Overview and trends in micro-electronics
packaging and interconnect technology• BGA - definition, package constructions,
major volume applications by package type,new developments by package type, and new developments especially in high-performance packaging
• CSP - definition, package constructions,major volume applications by package type,new developments by package type, and new developments including wafer-level packages
• Flip chip related technologies - definition,flip chip in-package (FCIP) and flip chip on board (FCOB) applications, drivers for expansion, and future trends
• In addition, samples of packages/substrates/ modules will be used during this course to illustrate the topics described above.Photos of products using advanced packageswill also be included in this course.
Who Should Attend:This course will be beneficial to all managers andindividual contributors from the electronicsindustry who need fundamental understandingand broad perspective on microelectronicspackaging and interconnect technology, especiallyin technology trends and key developmentalareas such as BGA, CSP, and flip chip.
AFTERNOON COURSES 1:15 – 5:00 PM
9. RF/WIRELESS PACKAGINGInstructors: Joy Laskar and
Emmanouil (Manos) M.Tentzeris Georgia Institute of Technology
Course Objectives:Review the latest developments in the area ofnext-generation RF/ microwave packaging.Investigate different materials and topologies.Present integrated solutions for wirelesstransceivers incorporating packaging adaptiveantennas. Discuss possible solutions for RF-MEMS packaging problems. Provide easy-to-usedesign rules using CAD tools. Present integratedmodules for WiFi and 60 GHz broadbandcommunication/sensor applications.Course Outline:• Vertical interconnects (flip chip, BGA, PGA)• Embedded components in organics and
ceramics (LTCC) and LCP materials• Integrated inductors, filters, duplexers in
3D configurations• Packaging adaptive ultracompact and
multiband antennas• Integrated wireless transceivers for WiFi and
mm-wave applications• RF-MEMS• Practical designs using modeling CAD tools• Discussion of the challenges for the
extension of designs in UWB
Who Should Attend:Engineers and technical managers who would liketo get familiar with the challenges and problemsencountered in RF/Wireless packaging.
10. WAFER LEVEL - CHIP SCALEPACKAGING
Instructor: Luu T. NguyenNational Semiconductor Corporation
Course Objectives:Wafer level-chip scale packaging (WL-CSP) hasgained momentum in the small chip arena lately,driven by needs for cost reduction, form factorshrinkage, and enhanced performance. Thiscourse will provide an overview of the WL-CSPtechnology. The market drivers, benefits, andchallenges facing industry-wide adoption will bediscussed. The current WL-CSP configurations
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IMPORTANT NOTICEIt is extremely important to register
in advance to prevent delays atdoor registration. Course sizes
are limited.
will be reviewed in terms of their construction,manufacturing process and publishedelectrical/thermal performance, together withpackage and board level reliability. Since thetechnology marks the convergence of fab,assembly and test, discussion will also addresssome fundamental issues such as: Where wouldit fit best (front end or back end)? Will it beapplicable and cost-effective for complex devicessuch as microprocessors? Are current standards(design rules, outline, reliability, etc.) applicable?
Course Outline:• Wafer level-chip scale packaging
(WL-CSP) - definition• Market drivers for WL-CSPs• Benefits of WL-CSPs• Barriers and challenges for WL-CSPs• Review of current WL-CSPs in the industry• Wafer level testing - status and challenges• Infrastructure service providers• Future trends: lead-free, large die size, wafer
level underfill
Who Should Attend:The course will be useful to the following threegroups of engineers and scientists:1. Newcomers to the field who would like toobtain a general overview of WL-CSP; 2.Thosewho are already practicing research anddevelopment of IC packaging and would like tolearn new methods for solving CSP problems;and, 3. Those who are currently consideringWL-CSP as a potential CSP alternative for theirinterconnect systems.
11. MICROVIAS & HIGH-DENSITYINTERCONNECTS FOR ADVANCED
PACKAGINGInstructor: Ricky Lee,Hong Kong University
of Science and Technology
Course Objectives:This course will introduce the cutting-edgeinformation on the most important developmentand latest research results in applying microviasand high-density interconnect technologies toadvanced packaging. For professionals active inmicroelectronic packaging research anddevelopment, those who wish to master highdensity interconnect technologies, and thosewho need to choose a cost-effective design andhigh-yield manufacturing process for theirelectronic systems, this is a timely summary ofprogress in all aspects of this fascinating field.The lecture contents are based on theinstructor's books on electronic packaging, hisrecent research results, and interactions with thepackaging and assembly industries. The scope ofcourse covers flip chip and CSP technologies,wafer-level packaging, microvias and build-upsubstrates, and emerging high-density
interconnect technologies. With the informationprovided in this lecture, the attendees willacquire a practical understanding in the design,materials, processes, analysis, and reliability issuesof high-density interconnection technologies.
Course Outline:• Overview of area array and high-density
interconnect technologies• Solder-bumped flip chip & wafer level chip
scale packages• Formation of microvias on silicon wafer• Formation of microvias on organic substrate• Copper-plated and conductive
paste/ink-filled microvias• Special high-density interconnect
technologies • PCB/substrate with sequential build-up layers• Reliability issues of high-density
interconnects
Who Should Attend:This short course is intended for researchscientists, professional engineers and technicalmanagers who are involved in IC packaging,component assembly, materials and processing,contract manufacturing and marketing.
12. INTERCONNECT ANDPACKAGING TECHNOLOGIES
FOR 10 AND 40GBPS TELECOM AND DATACOM
Protocols, Design, and Case StudiesInstructors: Roberto Coccioli,
Inphi Corporation andHassan Hashemi
Mindspeed Technologies, Inc.
Course Objectives:The objectives of this course are to reviewchallenges in 10G and 40G IC packagingconsidering requirements posed by mixed ICtechnologies and system architecture as definedin industry Multi Source Agreements. Moreover,it is intended to review the technologies availableto realize package and board interconnectsassessing their relative performance and theirimpact on signal integrity on high-speed digitalsignaling.The course material is based upon theinstructors' experience on current practices used for GHz IC packaging for telecom, storage,and datacom applications.
Course Outline:• Review of 10G & 40G system features &
packaging challenges• OE systems requirements and protocols• Standards for 10Gbps and 40Gbps
transponders• Substrate technologies for 10Gpbs and
40Gbps applications• Ceramic: thick-film, thin-film, HTCC,
LTCC, low resistance multilayer alumina
• Organic: high Tg FR4/BT, PTFE glass fiber,PTFE ceramic
• Leadframe based chip-scale packages• Effects of interconnects on signal integrity• First level interconnect: wirebonds, ribbons
and flip-chip• Transmission lines: CPW, microstrip,
stripline• Second level interconnect: BGA, LGA,
QFP, QFN• Connectorized packages for 10Gbps and
40Gbps ICs• Connector types: threaded & push-on• 10Gbps and 40Gbps IC package design
examples• Manufacturing tolerances and their effects
on performance• Conclusions
Who Should Attend:The course is designed for engineers orengineering managers who want to understandmore about technical challenges of high-speedpackaging, trends, and the unique requirementsposed on technology selection and design toassure the achievement of stringent electricaland thermal performance in cost-performanceefficient manufacturing.
13. PACKAGE FAILURE ANALYSIS -FAILURE MECHANISMS AND
ANALYTICAL TOOLSInstructors: Deepak Goyal
and Rajen DiasIntel Corporation
Course Objectives:The seminar will provide an overview of thefailure modes and mechanisms observed in theplastic packages. A brief introduction to themethodology of failure analysis of these packageswill be described. Emphasis will be paid to thetools and techniques currently used and thefuture direction for the tools and techniquesrequired for successful and timely failure analysisof next generation package technologies.
Course Outline:• Package technology; trends, drivers &
challenges• Failure analysis challenges offered by package
technology roadmap• Overview of the failure modes and
mechanisms observed in the organic packages
• Introduction to the methodology of failure analysis of organic packages
• Current analytical capabilities for package fault isolation and failure analysis
• Analytical capabilities to support next generation packaging
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Who Should Attend:Engineers and technical managers who areinvolved in package technology development,reliability assessment of packages and failureanalysis.
14. ADVANCED THERMALMANAGEMENT MATERIALS
Instructor: Carl ZwebenAdvanced Thermal Management
Course Objectives:This PDC presents an in-depth overview of theincreasing number of advanced thermalmanagement materials that are continuallyemerging to solve critical design problems: heatdissipation, thermal stresses, size, weight andelectromagnetic emissions. Advantages include:thermal conductivities up to four times that ofcopper; low, tailorable coefficients of thermalexpansion; tailorable electrical conductivity; highstrengths and stiffnesses; low densities; net shapefabrication processes. Payoffs include: increasedreliability; reduced thermal stresses and warpage;reduced electromagnetic emissions; simplifiedthermal design; weight savings up to 90%; sizereductions up to 65%; increased manufacturingyield; potential cost reductions. Advancedmaterials are now being used in high-volumecommercial and aerospace productionapplications, including hybrid vehicles, trains, windturbine generators, servers, cellular telephonebase stations, cellular telephones, laptops, high-power radars, spacecraft electronics, avionics, etc.Components include IGBT packages, heatspreaders, heat sinks, microprocessor unit lids,solid and flow-through PCB cold plates,microwave modules, optoelectronic packages,etc. This PDC compares traditional packagingmaterials with the large and increasing numberof advanced thermal management materials,which include: diamond particle-reinforcedcopper, aluminum, cobalt and silicon carbide;silicon-carbide-particle-reinforced aluminum(Al/SiC) and copper; carbon-fiber-reinforcedpolymers, aluminum and copper; beryllia-particle-reinforced beryllium; carbon/carbon composites;natural and highly oriented pyrolitic graphite;"ThermalGraph", etc. Topics include properties,processes, applications, costs, increasingmanufacturing yield and future directions.
Course Outline:• Introduction: design drivers;
material requirements; example of successfuladvanced materials - Al/SiC
• Material property and test method issues• Traditional packaging materials• Advanced materials overview:
monolithic materials; classes of composites• Monolithic carbonaceous materials
• Reinforcements: carbon fibers;diamond particles; carbon nanotubes
• Metal matrix composites - Part 1• Metal matrix composites - Part 2 • Metal/metal alloys-composites• Carbon, polymer matrix and ceramic matrix
composites• Manufacturing processes• Solving manufacturing problems and increase
yield with composites• Cost issues • System applications: servers, laptops, avionics,
base stations, hybrid vehicles etc.• Component applications: modules, heat
spreaders and sinks, cold plates, enclosures,optoelectronics, etc.
• Future trends
Who Should Attend:Engineers and managers involved in electronicpackaging design, production and R&D. Packagingmaterial suppliers. Since many of the materialscovered are new and not widely known, thePDC will benefit both novice and experiencedpersonnel.
15. INTRODUCTION TO NANOSCALEPACKAGING AND SYSTEMS
Instructors: Rao Tummala, GeorgiaInstitute of Technology - Packaging
Research Center and Zhong L. 'ZL' Wang,Georgia Institute of Technology - Center
for Nanoscience and Nanotechnology
Course Objectives:This course introduces nanoscale packaging asan important emerging technology. As thesemiconductor industry approaches an historictransition toward nanoscales of 100nm, and withmore than 10,000 I/Os and 150 watts/chip, it isbecoming clear that nano-packaging is necessary.Nano-packaging comes at two levels: IC andsystems, together leading to nano-systems in adecade. Wafer-level packaging, with materialssuch as solders at 20 micron pitch, fail due topoor fatigue resistance. Compliant structures,on the other hand, are expensive and have toohigh an inductance and electrical resistance.However, nano-interconnections provide anopportunity to have the best of both electricaland mechanical properties, in addition to lowcost and at-speed test and burn-in benefits notpresently available. Today's systems packagingconsists of bulk dielectrics, conductors formultilayer wiring; capacitors, resistors, inductors,filters for RF; and waveguides and detectors foroptoelectronics interconnections, high thermalconductivity materials and designs for heattransfer, solders with underfills for assembly. Canthese be scaled down to nano-dimensions withimproved properties so as to end up withsystems paradigms? This course reviews the
status of and presents potential opportunitiesthat nanoscience and packaging technologyprovide in each of the above.
Course Outline:• Nanotechnology, what is it?• Nanotechnology, why now?• What is nano-packaging? Why now?• Some research directions in nanopackaging:
Nano devices- CMOS and its nanoroadmapNanotubes and nanointerconnects- Materials growth- Self-assembly techniques- Property measurements- Integration with devicesNano IC packaging
• Nanosensors- Quantom dots- Bioapplications of quantum dot- Wireless and electric signal based sensors- Integration of sensors with microsystems- Cantilever based sensors
• Nanowires and nanobelts-based devices- Field effect transistors- Biosensing- Piezoelectric nanobelts- Resonators- Cantilevers- Transducers and sensors
• Nanobioelectronics and fluidics• Summary and outlook
Who Should Attend:This course is an overview and introductorycourse and is suitable for all levels of R&Dmanagement, senior engineers and executivesinvolved in technical strategy, future R&Dinvestments, assembly manufacturing processesand product development of electronicpackaging and systems in automotive, consumer,communication, computer, biomedical, andaerospace industries.
16. LEAD-FREE SOLDERS FORROBUST IC ELECTRONIC AND
OPTOELECTRONIC PACKAGINGInstructor: John H. LauAgilent Technologies, Inc.
Course Objectives:Since February 13, 2003, lead-free has been a lawin EU (European Union). The implementationdate is July 1, 2006. That means, after July 1st, allthe electronic products (except those withexemptions) cannot be made in and shipped toEU. At the time being, China is considering toadopt this law. Recently, packages such as PBGA(plastic ball grid array), CSP (chip scale package),and especially WLCSP (wafer level chip scalepackage) have been very popular for consumer,computer, communication, optoelectronic, and
optical MEMS (micro-electro-mechanical system)products. Most of these packages use solders astheir interconnects, thus they are affected by thelead-free regulations. In this course, some criticalissues of lead-free soldering (such as cost,regulations, definitions, design, materials, forward-and backward-process incompatibility, andreliability of components, PCBs, tin whiskers, andsolder joints) will be presented. Also, somecritical issues of PBGA, CSP, WLCSP,optoelectronic, and optical MEMS will bediscussed. The impacts of lead-free on PBGA,CSP,WLCSP, optoelectronic, and optical MEMSare examined. Most of the materials are basedon the instructor's and his co-authors’ (C. P.Wong, Ricky Lee, N. C. Lee, John Prince,Yi-HsinPao and Wataru Nakayama) recently publishedtextbooks, "Solder Joint Reliability of BGA, CSP,Flip Chip, and Fine Pitch SMT Assemblies","Electronics Packaging", "Chip Scale Packages","Low-Cost Flip Chip Technologies for DCA,WLCSP, and PBGA Assemblies", "Microvias forLow-Cost High-Density Inter-connects", and"Electronics Manufacturing with Lead-Free,Halogen-Free, and Conductive AdhesiveMaterials". (McGraw-Hill publishes all thesebooks.) Each participant will receive acomprehensive set of handout notes. Aftercompleting this course, you will be able to:Understand all important aspects and criticalissues of lead-free soldering; Have a head-start oflead-free soldering for your green products;Understand all important aspects of BGA,WLCSP, and flip chip technologies; Understandall important aspects of optoelectronic andMEMS technologies; Understand the realmeaning of reliability; Identify key parametersthat impact the lead-free solder joint reliability ofyour products; Avoid potential reliabilityproblems due to lead-free soldering of yourhigh-density products; Choose a cost-effectivedesign of your high-density electronic andoptoelectronic assemblies; Establish a high-yieldmanufacturing process.
Course Outline:• Introduction • IC trends and IC packaging technology
update• Optoelectronic and optical MEMS packaging• Lead-free soldering• Printed Circuit Boards (PCBs)• Wave soldering technology • Surface mount technology • Flip-chip WLCSP technologies with solders • Flip-chip WLCSP technologies with
conductive adhesives • Optoelectronic with lead-free technology• Optical MEMS with lead-free technology• Discussions
Who Should Attend:If you are involved with any aspect of theelectronics industry, you should attend thiscourse. The content is recommended forcomponent, packaging, design, material, process,
equipment, reliability, product assurance, qualitycontrol, manufacturing, vendor, marketing, andsales engineers and managers. It is equally suitedfor R&D engineers and scientists.
Continuing Education Units
The IEEE Components, Packaging and Manufacturing Technology Society (CPMT)has been authorized to offer Continuing Education Units (CEUs) by theInternational Association for Continuing Education and Training (IACET) for allShort Courses that will be presented at the 54th ECTC. CEUs are recognized byemployers for continuing professional development as a formal measure ofparticipation and attendance in “non-credit” self-study courses, tutorials, symposiaand workshops. IEEE CPMT CEUs can be applied towards the newly created“IEEE CPMT Professional Development Certificate.” Complete details, includingvoluntary enrollment forms, will be available at the conference. All costsassociated with ECTC Professional Development Courses CEUs will beunderwritten by the conference, i.e. there are no additional costs for ProfessionalDevelopment Courses attendees to obtain CEU credit.
IMPORTANT NOTICEAM Short Courses 1 through 8 or PM Short Courses 9 through 16 run
concurrently. Make sure you indicate specific course numbers you plan toattend on page 31.The cost of each session (AM or PM) is $350. If you plan
to attend both AM and PM courses, registrationfor all-day is $550.The student all-day course registration fee is $75.
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Photograph courtesy of Las Vegas News Bureau
Wednesday, June 2Session 1: SIP/SOP8:00 – 11:40 AMCommittee:AdvancedPackaging
Session Co-Chairs:Jeffrey A. Knight - EndicottInterconnect Technogies, INC.Tel: +1-607-755-1105Fax: +1-607-755-6400Email: [email protected]
Gary Morrison - TexasInstruments, Inc.Tel: +1-972-995-4851Email: [email protected]
High Density and Compliant Wafer-Level Electrical and OpticalPolymer Pilar Chip I/OInterconnectionsMuhannad Bakir and James Meindl -Georgia Institute of Technology
MAP (Mobile AGP Processor) - AHigh- Performance IntegratedGraphics ModuleRaj Pendse, M.Yee, J. S.Yun and BretZahn - ChipPAC Inc.; Bob Jafari,TimLau, Mihalis Michael, Inderjit Singh andOrion Starr - NVIDIA Corp.
System-on-a-Package (SOP)Substrate and Module with Digital,RF and Optical IntegrationVenky Sundaram, Rao Tummala, GeorgeWhite, Kyutae Lim, Lixi Wan, DanielGuidotti, Fuhan Liu, Ravi Doraiswami,Joy Laskar, G. K. Chang, ManosTentzeris and Madhavan Swaminathan -Georgia Institute of Technology
Process Development and Reliabilityfor System-in-a-Package UsingLiquid Crystal PolymerLiu Chen and Johan Liu - ChalmersUniversity of Technology; XinzhongDuo - Royal Institute of Technology
Physical Design of OptoelectronicSystem-on-a-Package Using OpticalWaveguide InterconnectsChung-Seok (Andy) Seo and AbhijitChatterjee - Georgia Institute ofTechnology; Nan M. Jokerst - DukeUniversity
Thermal Limits of Fine PitchExposed Pad TQFP SIP for HardDisc Drive ApplicationsTiao Zhou - Texas Instruments; BillRugg - Seagate
Physical Layout Automation forSystem-On-PackagesRamprasad Ravichandran, Jacob Minz,Mohit Pathak, Siddharth Easwar andSung Kyu Lim - Georgia Institute ofTechnology
Wednesday, June 2Session 2: Pb-Free Flip-ChipInterconnections I8:00 – 11:40 AMCommittee:Interconnections
Session Co-Chairs:Dev Gupta - Advanced Packaging& Systems TechnologyTel: +1-480-540-3232Email: [email protected]
Jong-Kai Lin - Motorola, Inc.Tel: +1-480-413-3254Fax: +1-480-413-4511Email: [email protected]
Assembly and Reliability of FlipChip Solder Joints UsingMiniaturized Au/Sn BumpsMatthias Hutter, Florian Hohnke,Hermann Oppermann, Matthias Kleinand Gunter Engelmann - FraunhoferIZM
A Low-Cost Plated Column BumpFlip Chip Technology for Sub-100umPitch and WLP ApplicationsDev Gupta, C. Holland and M. Fria -APSTL
FCOB (Flip Chip on Board)Reliability Study for MobileApplicationsSe-Young Jang, Soon-Min Hong, Hyun-Wook Nam, Min-Young Park, Sang-Hoon Roh and Young-Joon Moon -Samsung Electronics Co., Ltd.; Dong-Ok Kwak - Samsung AdvancedInstitute of Technology
Effect of Intermetallic Compoundson Reliability in Sn-Ag-Cu Flip ChipSolder Bumps for Different UBMsand Substrate Pad FinishesPiyush Gupta, Ravi Doraiswami andRao Tummala - Georgia Institute ofTechnology; Kensuke Nakanishi -Harima Chemicals
Study of Spalling Behavior ofIntermetallic Compounds Duringthe Reaction between ElectrolessNi(P) Metallization and Lead-FreeSoldersYoon-Chul Sohn and Jin Yu - KoreaAdvanced Institute of Science andTechnology; Sung K. Kang and Da-YuanShih - IBM T. J.Watson ResearchCenter;Taek-Yeong Lee - HanbatNational University
Reliability of Lead-Free CopperColumns in Comparison with Tin-Lead Solder Column InterconnectsRahul Joshi and Seungbae Park - StateUniversity of New York, Binghamton;Lewis Goldmann - IBM Corporation
Experimental Characterization andMechanical Behavior Analysis onIntermetallic Compounds of 96.5Sn-3.5Ag and 63Sn-37Pb Solder Bumpwith Ti-Cu-Ni UBM on Copper ChipChih-Tang Peng, Chia-Tai Kuo and Kuo-Ning Chiang - National Tsing HuaUniversity;Terry Ku and Kenny Chang -VIA Technology Corporation
Wednesday, June 2Session 3: Innovative TestingMethods8:00 – 11:40 AMCommittee: Quality &Reliability
Session Co-Chairs:Charles Ume - Georgia TechTel: +1-404-894-7411Fax: +1-404-894-9342Email:[email protected]
Dongji Xie - FlextronicsInternationalTel: +1-408-576-7597Fax: +1-408-576-7988Email:[email protected]
Prediction of Process-InducedWarpage of IC PackagesEncapsulated with ThermosettingPolymersD. G.Yang, K. M. B. Jansen and L. J. Ernst- Delft University of Technology; G. Q.Zhang - Philips-CFT;W. D. van Drieland H. J. L. Bressers - PhilipsSemiconductors; X. J. Fan - Philips
Towards a Predictive Behavior ofNon-Conductive AdhesiveInterconnects in MoistureEnvironmentJo Caers, Xiujuan Zhao and Hansen G.Sy - Philips Electronics Singapore; EeHua Wong - Institute ofMicroelectronics (IME), Singapore;Subodh Mhaisalkar - NTU, Singapore
Detection of Flip Chip Solder JointCracks Using CorrelationCoefficient Analysis of LaserUltrasound SignalsLizheng Zhang and I. Charles Ume -Georgia Institute of Technology;Juergen Gamalski and Klaus-PeterGaluschki - Siemens AG
Mechanical Characterization of Sn-Ag-Based Lead Free SoldersMasazumi Amagai - Texas Instruments,Inc.
Microstructural andMicromechanical Characterisationof Sn-Ag-Cu Solder FCOBInterconnects at Ambient andElevated TemperaturesChangqing Liu, Dezhi Li and PaulConway - Loughborough University
In-Process Measurement of theInterfacial Fracture Toughness for aSub-Micron Titanium Thin Film andSilicon Interface Using a Single StripDecohesion TestJiantao Zheng and Suresh K. Sitaraman- Georgia Institute of Technology
Determination of FractureToughness of Underfill/ChipInterface with Digital Image SpeckleCorrelation TechniqueZhang Yanlie and Zhou Wei - NanyangTechnological University; Shi Xunqing -Singapore Institute of ManufacturingTechnology
Wednesday, June 2Session 4: Adhesives andEncapsulants8:00 – 11:40 AMCommittee: Materials &Processing
Session Co-Chairs:Johan Liu - Chalmers Universityof TechnologyTel: +46-31-706-6294Fax: +46-31-706-6289Email: [email protected]
Chandra Jayaram - IntelTechnology Sdn. Bhd.Tel: +604 253 5289Fax: +604 253 6507Email:[email protected]
Electrical and ThermalConductivities of PolymerComposites Containing Nano-SizedParticlesLianhua Fan, Bin Su, Jianmin Qu and C.P.Wong - Georgia Institute ofTechnology
Development on Wafer LevelAnisotropic Conductive Film forFlip-Chip InterconnectionJean-Charles Souriau, Jean Brun, RemiFraniatte and Gasse Adrien - CEA-Grenoble-LETI
Anisotropic Conductive Adhesiveswith Enhanced ThermalConductivity for Flip-Chip ApplicationsMyung Jin Yim, Jin Sang Hwang and JinGu Kim - Telephus, Inc.;WoonseongKwon, Kyung Woon Jang and Kyung-Wook Paik - Korea Advanced Instituteof Science and Technology
Reliability Enhancement ofElectrically Conductive Adhesives inThermal Shock EnvironmentHaiying Li, Kyoung-Sik Moon,Yi Li andC. P.Wong - Georgia Institute ofTechnology
Integration of Low StressPhotopatternable Silicones into aWafer Level PackageGeoff Gardner, Brian Harkness andHerman Meynen - Dow Corning;Mario Gonzales, Mathieu VandenBulcke, Bart Vandevelde and Eric Beyne- IMEC
Emerging Challenges of Underfill for Flip-Chip ApplicationTim Chen - Intel Corp.
Hygro-Thermo-MechanicalBehavior of Mold CompoundMaterials at Elevated EnvironmentSung Yi and Zeyan Yu - Portland StateUniversity; Raynard Neo - Micron;Yeong Lee - Dow Corning
Program Sessions
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Wednesday, June 2Session 5: Low CostOptoelectronic PackagingTechnology8:00 – 11:40 AMCommittee:Optoelectronics
Session Co-Chairs:Alan J. Morrow - BinOpticsCorporationTel: +1-607-257-3200 x236Fax: +1-607-257-9753Email: [email protected]
Andrew Shapiro - University ofCalifornia, IrvineTel: +1-949-824-8086Fax: +1-949-824-2541Email: [email protected]
Reliability Concerns and PackagingIssues of Non-Hermetic VCSEL- andLED-Based Transceivers for theEnterprise MarketWilliam Ring, Peter Thambinayagam,Wayne Hobson, Henry Meehan, MingLiang and Peter Silbermann - TycoElectronics, Inc.
Optical SMT-Packaging for HighlyEfficient and Reliable Fiber OpticComponents Including 1300nmVCSELsHans L.Althaus, Marco Melinde,Gunther Steinle, Martin Weigert andHelmut Wietschorke - InfineonTechnologies AG
A Low-Cost Plastic Package for2.5Gbps Optical TransceiverModules with High ElectromagneticShieldingTzong-Lin Wu,Wen-Chi Hung, Chien-Hui Lee, Cheng-Wei Lin and Wood-HiCheng - National Sun Yat-senUniversity; Wern-Shiarng Jou -National Kaohsiung University ofApplied Sciences
Low-Cost Optical Subassemblies forMetro Access ApplicationsWilliam Hogan, Robert Wolf,AnandShulka and Phil Deane - JDS UniphaseCorp.
Unique 1 TO Structure Low-CostOptical SubassemblyMasahiko Tsumori, Sun Hyoung Pyo,Joong Hee Lee,Young kwon Yoon andTaeil Kim - Samsung Electronics Co.,Ltd.
Packaging of a High-Speed OpticalModulator Using Flip-ChipInterconnectsYuvaraja Visagathilagar,Wayne Roweand Arnan Mitchell - RMIT University
Ultra Compact OpticalSubassembly Using Integrated LaserDiode and Silicon Microlens forLow-Cost Optical ComponentsDaisuke Shimura, Masahiro Uekawa,Ryo Sekikawa, Kyoko Kotani,YoshinoriMaeno, Hironori Sasaki and TakeshiTakamori - Oki Electric Industry Co.,Ltd.
Wednesday, June 2Session 6: ElectricalModeling8:00 – 11:40 AMCommittee: Modeling &Simulation
Session Co-Chairs:George A. Katopis - IBMCorporationTel: +1-914-435-6719Fax: +1-914-435-1593Email: [email protected]
Bruce Kim - Arizona StateUniversityTel: +1-480-965-3749Fax: +1-480-965-3837Email: [email protected]
A Fast Full-Wave ModelingMethodology for StriplineStructures with VerticalInterconnects in Multi-LayerDielectricsKonstantinos Nikellis - Helic S.A. -National Technical University of Athens;Yorgos Koutsoyannopoulos and SotirisBantas - Helic S.A.; Nikolaos Uzunoglu- National Technical University ofAthens
An Efficient Finite Element-BasedElectromagnetic Field ModelingMethodology for InterconnectStructures Including Lumped CircuitElementsHong Wu and Andreas Cangellaris -University of Illinois at Urbana-Champaign
An Efficient Full-Wave LayeredInterconnect Simulator (UA-FWLIS)Xing Wang, Zhaohui Zhu, StevenDvorak and John Prince - University ofArizona
Very High-FrequencyCharacterization of High-Density 3-D ModuleMatti Mäntysalo, Jarmo Tanskanen andEero O. Ristolainen - TampereUniversity of Technology
Modeling and Optimization ofMultilayer LTCC Inductors forRF/Wireless Applications UsingNeural Networks and GeneticAlgorithmsRana Pratap, Saikat Sarkar, StephanePinel, Joy Laskar and Gary May -Georgia Institute of Technology
A Simplified Cross Coupling Modelfor Multiple Balanced TransmissionLinesDavid Quint, Karl Bois and Yong Wang- Hewlett Packard Company
Characterization of DiscreteDecoupling Capacitors for High-Speed Digital SystemsJoong-Ho Kim, Dan Jiao, Jiangqi He,Kaladhar Radhakrishnan andChanghong Dai - Intel Corporation
Wednesday, June 2Session 7: IntegratedCapacitor and ResistorTechnology8:00 – 11:40 AMCommittee: Components& RF
Session Co-Chairs:Leonard W. Schaper - Universityof ArkansasTel: +1-479-575-8408Fax: +1-479-575-2719Email: [email protected]
Li Li - Motorola, Inc.Tel: +1-480-413-6653Fax: +1-480-413-4511Email: [email protected]
Advanced Decoupling in High-Performance IC PackagingDeepa Mannath, Leonard Schaper andRichard Ulrich - University of Arkansas
Novel Flexible and Thin Capacitorswith Mn-Doped SrTiO3 Thin Filmson Polyimide FilmsShintaro Yamamichi and AkinobuShibuya - NEC Corporation
Thin-Film Low InductanceDecoupling Device for High SpeedDigital CircuitsJunya Takafuji, Shigeo Konushi, HisashiNakashima, Seiji Ueda, FumioFukumaru and Shinji Nambu - KyoceraCorporation
Simultaneous Switching NoiseSuppression Using HydrothermalBarium Titanate Thin- FilmEmbedded CapacitorsDevarajan Balaraman,Vijay Patel, P.Markondeya Raj, Lixi Wan, MichaelSacks, Isaac R.Abothu, MadhavanSwaminathan and Rao Tummala -Georgia Institute of Technology
Design and Performance ofPolymeric Ultra-Thin Substrates forUse as Embedded CapacitorsJohn Andresakis,Takuya Yamamoto andPranbes Pramanik - Oak-MitsuiTechnologies; Nicholas Biunno -Sanmina-SCI
Thin-Film Integration of Passives -Single Components, Filters,Integrated Passive DevicesKai Zoschke, M. Jürgen Wolf, OswinEhrmann,Thomas Fritzsch, KatrinScherpinski, Michael Töpper andHerbert Reichl - Fraunhofer IZM;Franz-Josef Schmückle - Ferdinand-Braun-Institut (FBH)
Design and Fabrication of anAutomotive Engine Controller UsingEmbedded Passive Technology forPWBJohn Myers and Jiming Zhou - DelphiElectronics and Safety
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Wednesday, June 2Session 8: Flip-ChipPackaging1:30 – 5:10 PMCommittee:AdvancedPackaging
Session Co-Chairs:Raj N. Master - AMDTel: +1-408-982-7023Fax: +1-408-982-6164Email: [email protected]
Raj Pendse - ChipPAC, Inc.Tel: +1-510-979-8330Fax: +1-510-979-8009Email:[email protected]
IXP2400 NPU PackageDevelopmentAndreh Janian,Altaf Hasan,AdamBarrett and Upendra Sheth - IntelCorporation
High Speed DDR Performance in 4vs. 6 Layer FCBGA Package DesignEdward Chan, Huabo Chen and CheeYee Chung - NVIDIA Corporation
NanoLinks: Lithography-BasedWafer-Level Compliant Chip-to-Substrate InterconnectsSuresh Sitaraman and George Lo -Georgia Institute of Technology
BGA Ball Field Interaction withManufacturing and DesignAltaf Hasan and Daryl Sato - IntelCorporation
Gbps High-Speed ElectricalCharacteristics of Flip-Chip BGAPackage Exceeding 2,000pin CountsKazuyuki Nakagawa, Masaki Watanabe,Shinji Baba and Michitaka Kimura -Renesas Technology Corp.; KeitaroYamagishi,Yuuichi Sasaki,TomoyukiKamiyama and Masaaki Namatame -Mitsubishi Electric Corporation
Wednesday, June 2Session 9:Wirebond1:30 – 5:10 PMCommittee:Interconnections
Session Co-Chairs:Wolfgang Sauter - IBMMicroelectronicsTel: +1 802 769 3634Fax: +1 802 769 1038Email: [email protected]
Rajen Dias - Intel CorporationTel: +1-480-554-5202Fax: +1-480-554-7171Email: [email protected]
Manufacturability and Reliability ofDifferent Size Wirebonds onDifferent Al Pad StructuresWolfgang Sauter and Kevin Ostrowski- IBM Corporation;Toyohiro Aoki andTakashi Hisada - IBM Japan, Ltd.;Frederic Beaulieu and Stephanie Allard- IBM Canada, Ltd.
Wire Bonding on a Novel ImmersionGold-Capped Copper-MetallizedIntegrated CircuitGanesh Vetrivel Periasamy, KripeshVaidyanathan and Chih Hang Tung -Institute of Microelectronics; Loon AikLim - ASM Singapore
Assembly Process Development of50um Fine Pitch Wire BondedDevicesYufeng Yao, Zhengpeng Xiong, Xin Guand Simon Chua - Agere SystemsSingapore Pte Ltd.;Tingyu Lin -Motorola Electronics Pte Ltd.Singapore
Changes in Wirebond Integrity andReliability as Wirebond PitchDecreasesToyohiro Aoki and Takashi Hisada - IBMJapan, Ltd.;Wolfgang Sauter - IBMCorporation
A Study on the Reliability and Thermo-Mechanical Properties of The Gold Ribbon Wire BondingChee Wei Tan and Yan Cheong Chan -City University of Hong Kong; HongDu Liu and Bernard N.W. Leung -Photonic Manufacturing Service Ltd.
Thermosonic Wire Bonding ProcessSimulation and Bond Pad overActive (BPOA) Stress AnalysisYong Liu, Scott Irving and Timwah Luk- Fairchild Semiconductor Corporation
Radio Frequency Characterizationof Bonding Wire Interconnections ina Molded ChipJun Yi Chuang, Sung Pi Tseng and J.Andrew Yeh - National Tsing HuaUniversity
Wednesday, June 2Session 10: Characterizationof Failure Mechanisms inAdvanced Packagaing1:30 – 5:10 PMCommittee: Quality &Reliability
Session Co-Chairs:Darvin R. Edwards - Texas Instruments, Inc.Tel: +1-972-995-3569Fax: +1-972-995-2658Email: [email protected]
Jeffrey Suhling - AuburnUniversityTel: +1-334-844-3332Fax: +1-334-844-3307Email: [email protected]
Gold Embrittlement of Solder Jointsin Wafer-Level Chip Scale Packageon Printed Circuit Board with Ni/AuSurface FinishingS.W. Ricky Lee - Hong Kong Universityof Science and Technology; XingjiaHuang - Foxconn Inc.; Ming Li -Chinese University of Hong Kong;William Chen - ASE Technologies Inc.
Development of BGA Solution forthe IBM PowerPC 970 Module inApple’s G5 SystemDavid Edwards, Mukta Farooq andLewis Goldmann - IBM Corporation;Hope Chambers and Amir Salehi -Apple Computer
Failure Analysis and VirtualQualification of PBGA UnderMultiple Environmental LoadingsHaiyu Qi, Chris Wilkinison, MichaelOsterman and Michael Pecht -University of Maryland
Modeling Thermo-MechanicalReliability of Bumpless Flip-ChipPackageJohn H. L. Pang and T. H. Low -Nanyang Technological University;Charles Lin and Andrew Yang - BridgeSemiconductor
Thermo-Mechanical Reliability ofPower Flip-Chip Cooling ConceptsBernhard Wunderle, Rainer Dudek andMichel Bernd - Fraunhofer IZM; ReichlHerbert - Technical University of Berlin
Continuous Operation at 200CDevice Junction Temperature:TheFinal Frontier for RF PowerSemiconductor Plastic PackagingMali Mahalingam, Dave Abdo, FrankDanaher and Alex Elliott - Motorola,Inc.
Calculation of CriticalDelamination Size for Failure of thePad/Encapsulant Interface of PlasticIC Packages Undergoing SolderReflowAndrew Tay - National University ofSingapore;Yiyi Ma - Institute ofMicroelectronics;Toshio Nakamura -State University of New York, StonyBrook; Soon Huat Ong - NationalSemiconductor Manufacturing,Singapore
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Wednesday, June 2Session 11: Nanoscale andEmerging Technologies1:30 – 5:10 PMCommittee: Special Topics
Session Co-Chairs:Jim Morris - Portland StateUniversityTel: +1-503-725-9588Fax: +1-503-725-3807Email: [email protected]
S.W. Ricky Lee - Hong KongUniversity of Science &TechnologyTel: +852-2358-7203Fax: +852-2358-1543Email: [email protected]
Low-Cost and Repairable Nano IC-Package Interconnections bySolution SynthesisAnkur Aggarwal, Pulugurtha Raj, IsaacAbothu, Michael Sacks and RaoTummala - Georgia Institute ofTechnology; Andrew Tay - NationalUniversity of Singapore
Metallic Fullerene and MWCNTsComposite Solutions forMicroelectronics SubsystemElectrical InterconnectionEnhancementRandy Pike, Russell Dellmo, J.AnthonyWade, Scott Newland, Gregory Hylandand Charles M. Newton - HarrisCorporation
Z-Axis Interconnects Using FinePitch, Nanoscale Through SiliconVias: Process DevelopmentSilke Spiesshoefer, Leonard Schaper,Susan Burkett, Gowtham Vangara,Parthiban Arunasalam and ZiaurRahman - University of Arkansas
Power and Reliability Improvementof an Electro-ThermalMicroactuator Using Ni-DiamondNanocompositeLi-Nuan Tsai - National Chiao TungUniversity
Study and Characterization on theNano-Composite Underfill for Flip-Chip ApplicationsYangyang Sun and C. P.Wong - GeorgiaInstitute of Technology
Combined Process for Wafer-DirectBonding by Means of the SurfaceActivation MethodTadatomo Suga,Tae Hyun Kim andMatiar Howlader - University of Tokyo
A New Approach in Measuring Cu-EMC Adhesion Strength by AFMCell K.Y.Wong, Hongwei Gu, Bing Xuand Matthew M. F.Yuen - Hong KongUniversity of Science and Technology
Wednesday, June 2Session 12: Materials forEmbedded Passives1:30 – 5:10 PMCommittee: Materials &Processing
Session Co-Chairs:Rajen Chanchani - SandiaNational LabsTel: +1-505-844-3482Fax: +1-505-844-7011Email: [email protected]
Mark Poliks - EndicottInterconnect Technologies, Inc.Tel: +1-607-755-2064Fax: +1-607-755-6151Email: [email protected]
Effects of the Low-Loss Polymers onthe Dielectric Behavior of NovelAluminum-Filled High-KNanocompositesJianwen Xu and C. P.Wong - GeorgiaInstitute of Technology
Development of a Novel Polymer-Metal Nanocomposite Obtainedthrough the Route of In-SituReduction and Its DielectricPropertiesYi Li, Suresh Pothukuchi and C. P.Wong- Georgia Institute of Technology
Development of High-K EmbeddedCapacitors on Printed Wiring BoardIsaac Robin Abothu, Markondeya RajPulugurtha, Balaraman Devarajan,Swapan Bhattacharya, Michael Sacksand Rao Tummala - Georgia Institute ofTechnology
Development of Low-K InterlayerDielectric Film for EmbeddedPassives and Actives IntegralSubstratesKazuki Uwada and Hotta Yuuji - NittoDenko Corporation
Development of High-KInorganic/Organic CompositeMaterial for Embedded CapacitorManabu Kawasaki,Yoshitake Hara,YukaYamashiki, Noboru Asahi, Ryo Nagase,Takenori Ueoka and Masahiro Yoshioka- Toray Industries, Inc.
Low-Temperature EmbeddedCapacitor Fabrication Albert Chee W. Lu, Boon K. Lok, Lai L.Wai and Fan Wei - Singapore Instituteof Manufacturing Technology; Kim HuatWong and Mok C. Neo - PentexSchweizer Circuits, Ltd.
Super High Dielectric ConstantCarbon Black-Filled PolymerComposites as Integral CapacitorDielectricsJianwen Xu and C. P.Wong - GeorgiaInstitute of Technology
Wednesday, June 2Session 13: Power Delivery1:30 – 5:10 PMCommittee: Modeling &Simulation
Session Co-Chairs:Tawfik Rahal-Arabi - IntelCorporationTel: +1-503-613-5903Fax: +1-503-613-8261Email: [email protected]
Moises Cases - IBM CorporationTel: +1-512-838-6225Fax: +1-512-823-5938Email: [email protected]
Design Methodology for MultipleDomain Power Distribution SystemsNam Pham, Moises Cases, Daniel deAraujo and Erdem Matoglu - IBMCorporation
New Methods for PowerDistribution System Design andAnalysisJoel Auernheimer - Intel Corporation
The Effects of On-Chip andPackage Decoupling Capacitors andan Efficient ASIC DecouplingMethodologyNanju Na,Tim Budell, Charles Chiu,Eric Tremble and Ivan Wemple - IBMCorporation
Coupling of Simultaneous SwitchingNoise to Interconnecting Lines inHigh-Speed SystemsJingook Kim, Jongbae Park and JounghoKim - Korea Advanced Institute ofScience and Technology; Mihai DragosRotaru, Kok Chin Chong andMahadevan K. Iyer - Institute ofMicroelectronics
Analysis of Coupling SuppressionMethods on Split Power/GroundPlanesYouchul Jeong and Joungho Kim -Korea Advanced Institute of Scienceand Technology;Albert Chee Wai Lu,Lai L.Wai,Wei Fan and Boon Keng Lok- Singapore Institute of ManufacturingTechnology
Power Delivery System PerformanceOptimization of a Printed CircuitBoard with MultipleMicroprocessorsOm Mandhana - Motorola, Inc.; JinZhao - Sigrity, Inc.
Power Delivery ValidationMethodology and Analysis forNetwork ProcessorsMahadevan Suryakumar,Wei Cui,Christopher Carlson, Morgan John,Bruce Fishbein and Prashant Parmar -Intel Corporation
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Thursday, June 3Session 14: 3D Packaging8:00 – 11:40 AMCommittee:AdvancedPackaging
Session Co-Chairs:Tiao Zhou - Texas InstrumentsIncorporatedTel: +1-214-567-2736Email: [email protected]
Young-Gon Kim - TesseraTel: +1-408-383-3685Fax: +1-408-894-0285Email: [email protected]
Advanced Warpage PredictionMethodology for Matrix StackedDie BGA During Assembly ProcessesXueren Zhang and Tong Yan Tee -STMicroelectronics
Process Integration of 3D ChipStack with Vertical InterconnectionKenji Takahashi,Yuichi Taguchi, MasatakaHoshino,Yoshihiko Nemoto, MitsuoUeno, Koji Marusaki,Yasuhiro Yamajiand Hiroshi Terao - Association ofSuper-Advanced ElectronicsTechnologies (ASET);ToshihiroYonezawa and Kazuo Kondo -Okayama University
System Design Issues for 3D System-in-Package (SiP)Jani Miettinen, Matti Mäntysalo, KimmoKaija and Eero O. Ristolainen -Tampere University of Technology
High-Performance VerticalInterconnection for High-Density3D Chip Stacking PackageMitsuo Umemoto, Kazumasa Tanida,Yoshihiko Nemoto, Masataka Hoshino,Kazumi Kojima,Yuji Shirai and KenjiTakahashi - Association of Super-Advanced Electronics Technologies(ASET)
Board-Level Reliability Study onThree-Dimensional Thin StackedPackageJinYoung Kim,WonJoon Kang,YoonHyun Ka,YongJoon Kim, EunSookSohn, SungSu Park, JaeDong Kim andChoonHeung Lee - Amkor TechnologyKorea, Inc.;Akito Yoshida and AhmerSyed - Amkor Technology, Inc.
Ultra-Wide Bandwidth Performanceof High-Density Wiring Interposerfor 3D PackagingKatsuya Kikuchi, Eun-Sil Jung, HiroshiNakagawa, Kazuhiko Tokoro andMasahiro Aoyagi - National Institute ofAdvanced Industrial Science andTechnology (AIST); Shigemasa Segawa -PI Research and Development Co.,Ltd.;Yoshihiko Nemoto and MitsuoUmemot
Development and Characterisationof Ultra- Thin Autonomous Modulesfor Ambient System ApplicationsUsing 3D Packaging TechniquesJohn Barton, Kieran Delaney, KevinDwane, Bivragh Majeed, Ken Rodgers,Stephen Bellis and Sean C. O’Mathuna- NMRC
Thursday, June 3Session 15:Pb-Free Flip-Chip II8:00 – 11:40 AMCommittee:Interconnections
Session Co-Chairs:Sung K. Kang - IBM - T.J.WatsonResearch CenterTel: +1-914-945-3932Fax: +1-914-945-2141Email: [email protected]
Lei L. Mercado - IntelCorporationTel: +1-480-552-1383Fax: +1-480-554-7171Email: [email protected]
Lead-Free Flip Chip InterconnectReliability in DCA and PBGAPackagesJong-Kai Lin, Jin-Wook Jang, ScottHayes and Darrel Frear - Motorola,Inc.
Injection Molded Solder Technology for Pb-Free Wafer BumpingPeter Gruber and Da-Yuan Shih - IBMResearch; Luc Belanger and GuyBrouillette - IBM Canada;ValerieOberson, Michel Turgeon and DavidDanovitch - IBM Canada, Ltd.; HideoKimura - IBM Japan, Ltd.
Pb-Free Bumping for High-Performance SoCsHirokazu Ezawa, Masaharu Seto andHiroshi Katsumata - Toshiba
Evaluation of Thermal Fatigue Lifeand Failure Mechanisms of Sn-Ag-Cu Solder Joints with Reduced AgContentsSung K. Kang, Paul Lauro and Da-YuanShih - IBM T. J.Watson ResearchCenter; Donald Henderson,TimothyGosselin, Jay Bartelo, Steve Cain,Charles Goldsmith and Karl Puttlitz -IBM Corporation;Tae-Kyung Hwang -Korea Advanced Institute of Scienceand Technology
Impact Reliability of Flip ChipSolder JointsMasayoshi Date - Hitachi MetalsAmerica, Ltd.;Tatsuya Shoji, MasaruFujiyoshi and Koji Sato - HitachiMetals, Ltd.; King-Ning Tu - Universityof California, Los Angeles
Interfacial Reactions and BumpReliability of Various Pb-Free SolderBumps on Electroless Ni-P UBMsKyung-Wook Paik,Young-Doo Jeon andMoon-Gi Cho - Korea AdvancedInstitute of Science and Technology
Qualification of SnAg Solder Bumpsfor Lead-Free Flip-Chip ApplicationsBernd Ebersberger, Robert Bauer andLars Alexa - Infineon Technologies AG
Thursday, June 3Session 16: Pb-Containingand Pb-Free Solder JointReliability8:00 – 11:40 AMCommittee: Quality &Reliability
Session Co-Chairs:Charles Zhang - Intel CorporationTel: +1-480-552-0453Fax: +1-480-554-7171Email: [email protected]
Jo Caers - Philips ElectronicsSingapore Pte Ltd.Tel: +65-6357-9370Fax: +65-6356-6741Email: [email protected]
Effect of Compression Loads on theThermal Cycle Performance of Flip-Chip BGA PackagesLuke Garner, Keh Shin Beh,Yew LipTan, Charles Zhang and Chris Peterson- Intel Corporation
Board-Level Thermal CycleReliability and Solder Joint FatigueLife Predictions of Multiple StackedDie Chip Scale PackageConfigurationBret Zahn, Dianne Mitchell and FlynnCarson - ChipPAC, Inc.
Damage Mechanics of Electronicson Metal-Backed Substrates inHarsh EnvironmentsPradeep Lall, Nokibul Islam, Jeff Suhling,John Evans,Tushar Shete and HechamAbdel-Hady - Auburn University
Reliability Assessment and FailureAnalysis of Fine Pitch Pb-Free FlipChip on Build-Up LaminateT. C. Chai, Poi-Siong Teo, Navas Khan, S.F. Choy,Vanissa Lim, S. N. Priya and A.Trigg - Institute of Microelectronics
Lead-Free Solder-Joint Reliabilityand Failure Analysis of High-DensityPackagesJohn Lau,Walter Dauksher and Ed Ott- Agilent Technologies, Inc.; DongkaiShangguan - Flextronics; Joe Smetana -Alcatel; Rob Horsley - Celestica; DaveLove - Sun Microsystems, Inc.; IrnMenis - IBM Corporation; Bob Sullivan- HDPUG
Intermetallic Morphology andAttendant Damage Evolution UnderThermomechanical Fatigue of Sn-Ag-Cu Solder InterconnectionsSteven Dunford, Sridhar Canumalla andPuligandla Viswanadham - NokiaCorporation
A Thermal Fatigue Life PredictionModel for SnAgCu Solder JointsAhmer Syed - Amkor Technology, Inc.
Thursday, June 3Session 17: Flip-ChipUnderfill8:00 – 11:40 AMCommittee: Materials &Processing
Session Co-Chairs:Daoqiang (DQ) Lu - IntelCorporationTel: +1-480-552-2909Fax: +1-480-552-1295Email: [email protected]
C. P. Wong - Georgia Institute ofTechnologyTel: +1-404-894-8391Fax: +1-404-894-9140Email: [email protected]
Four-Laser Bending BeamMeasurements and FEM Modelingof Underfill Induced Wafer WarpageZhuqing Zhang, Lianhua Fan, Suresh S.Sitaraman and C. P. Wong - GeorgiaInstitute of Technology
Fundamental Research on SurfaceModification of Nano-Size Silica forUnderfill ApplicationsYangyang Sun and C. P.Wong - GeorgiaInstitute of Technology
The Effect of Flow Properties onFiller Settling of Underfill in Flip-Chip PackageJinlin Wang and Tim Chen - IntelCorporation
Underfill Characterization for Low-K Dielectric / Cu Interconnect ICFlip-Chip Package ReliabilityPei-Haw Tsao, Chender Huang, Mirng-JiLii, Bob Su and Nun-Sian Tsai - TaiwanSemiconductor Manufacturing Co., Ltd.
Investigation of Different Options ofPre-Applied CSP Underfill forMechanical ReliabilityEnhancementsNael Hannan and Arni Kujala - NokiaCorp.;Vinod Mohan, Paul Morganelli,Jayesh Shah and Doug Katze - Emerson& Cuming
Stencil Printing on Bumped Waferfor Preapplied Underfill ApplicationHao Tang, Gray Shi, Larry Crane,George Carson and Michael Todd -Henkel Loctite Corporation
Void-Free Process Development andReliability for No-Flow UnderfillsMichael Colella and Daniel Baldwin -Georgia Institute of Technology
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Thursday, June 3Session 18: OptoeletronicsManufacturing Technology8:00 – 11:40 AMCommittee:Optoelectronics
Session Co-Chairs:Randy Heyler - NewportCorporationTel: +1-949-253-1657Fax: +1-949-253-1800Email: [email protected]
Bill Ring - Tyco Electronics - FiberOptic Business UnitTel: +1-908-704-6605Fax: +1-908-704-6637Email:[email protected]
Infrared Light Induced Degradationof Polymeric MaterialsJohn Osenbach - Agere Systems;Christopher Theis and Curt Jack -Triquint Optoelectronics
Design and Implementation of aMetallization Structure for High-Power Semiconductor Lasers forImproved Thermal Management andReliabilityXingsheng Liu, Kechang Song, RonaldDavis, Martin Hu and Chung-En Zah -Corning, Inc.
Thermal Impedance Measurementsof Junction-Down Mounted Singe-Side Contact Laser DiodesGuy Cohen, Dan Kuchta, BruceFurman, Joanna Rosner and JeanTrewhella - IBM Corp.;Y.Tatsuoka, S.Shira, K.Takagi,T.Aoyagi and E. Omura- Mitsubishi Electric Corporation
Fast Active Alignment in PhotonicsDevice PackagingJingyan Guo and Randy Heyler -Newport Corporation
Thermally-Tuned External CavityLaser with Micromachined SiliconEtalons: Design, Process andReliabilityMarc Finot, Mark McDonald, John Sell,Brad Bettman,Andrew Daiber,WilliamB. Chapman and William J. Kozlovsky -Intel Corporation
Development of Super High-DensityOptical Circuit Using DownsizedFibers and Flame-Retardant FiberTape and Multi-Fiber OpticalConnectorKenichiro Ohtsuka, Kousuke Tanaka,Shinji Ishikawa and Toshifumi Hosoya -Sumitomo Electric Industries, Ltd.
Modified Passive Alignment ofOptical Fibers with Low ViscosityEpoxy Flow Running in V-GroovesJeffery Lo and Ricky Lee - Hong KongUniversity of Science and Technology
Thursday, June 3Session 19: MEMS Packaging8:00 – 11:40 AMCommittee: Special Topics
Session Co-Chairs:Michael B. McShane - Motorola,Inc.Tel: +1-512-996-6175Fax: +1-512-996-6853Email: [email protected]
Erik Jung - Fraunhofer Institutefor Reliability andMicrointegrationTel: +49-30-46403-230Fax: +49-30-46403-254Email: [email protected]
Wafer-Level Vacuum Packaging ofMEMS SensorsJoseph Soucy,Thomas Marinis, JamesLawrence and Megan Owens - DraperLaboratory
New Wafer-Level-PackagingTechnology Using Silicon-Via-Contacts for Optical and OtherSensor ApplicationsJürgen Leib - SCHOTT ElectronicPackaging GmbH; Michael Toepper -Fraunhofer IZM, Berlin
Novel MEMS CSP to Bridge theGap Between Development andManufacturingErik Jung and Rolf Aschenbrenner -Fraunhofer IZM; Maik Wiemer -Fraunhofer IZM, Chemnitz;AlexanderFärber - ZEMI Branchlab MicrosystemEngineering, Berlin
Packaging of Disposable Chips forBioanalytical ApplicationsMatthias Schuenemann - IndustrialResearch Institute Swinburne; DavidThomson, Sebastiaan Garst, Paul Miller,Matthew Solomon and Jason Hayes -CRC for Microtechnology; Micah Atkin- OzMicrofluidics & CRC forMicrotechnology; Erol Harvey -MiniFab
Packaging Considerations forMicroelectromechanical MicrowaveSwitchesSamara Firebaugh - United States NavalAcademy; Harry Charles, RichardEdwards and Allen Keeney - The JohnsHopkins University
Chip Scale Packaging of MEMSAccelerometersLarry Felton,William A.Webster,Nicole Hablutzel and Kieran P. Harney- Analog Devices, Inc.
A Class of Distributed-MassMicromachined GyroscopesCenk Acar and Andrei Shkel -University of California, Irvine
Thursday, June 3Session 20:Thermal andThermo-MechanicalModeling of PackagingPolymer and Low-KDielectrics8:00 – 11:40 AMCommittee: Modeling &Simulation
Session Co-Chairs:Suresh K. Sitaraman - GeorgiaInstitute of TechnologyTel: +1-404-894-3405Fax: +1-404-894-9342Email:[email protected]
John L. Prince - University ofArizonaTel: +1-520-621-6187Fax: +1-520-621-2999Email: [email protected]
Experimental Validation ofHygro/Thermo-MechanicalSimulations for Multi-MaterialPolymer StructuresJoshua Kirk, Joshua Tor, Ibrahim Guvenand Erdogan Madenci - University ofArizona;Atila Mertol and Zafer Kutlu -LSI Logic Corporation
Constitutive Modeling of MouldingCompoundsLeo Ernst, Cornelis van ‘t Hof, KasparJansen and Daoguo Yang - DelftUniversity of Technology; Kouchi Zhang- Philips-CFT; Rik Bressers - PhilipsSemiconductors
Warpage Investigation of a PWBAssembly Under Thermal Loading:Modeling and ExperimentalValidationReinhard Powell, Carl Hanna and I.Charles Ume - Georgia Institute ofTechnology; Hai Ding - Intel Shanghai
Simultaneously Determining YoungModulus, Coefficient of ThermalExpansion, Poisson Ratio andThickness of Multi-Layered ThinFilms on Silicon WaferEnboa Wu and Albert J. D.Yang -National Taiwan University
FEM Study of Deformation andStresses in Copper Wire Bonds onCu Low-K Structures DuringProcessing and TestingDominiek Degryse, Bart Vandevelde,Serguei Stoukatch and Eric Beyne -IMEC
The Effect of Material Propertiesand Initial Defects on the Thermo-Mechanical Behavior of a Dual-Damascene ModuleViktor Gonda and Leo Ernst - DelftUniversity of Technology; Jaap denToonder - Philips ResearchLaboratories; Johan Beijer and KouchiZhang - Philips Center for IndustrialTechnology
Thermal Modeling of an ExtremePower Density Macro on a High-Power Density Microprocessor Chipin the Presence of RealisticPackaging and InterconnectStructuresKai Xiu - IBM Corporation; MarkKetchen - IBM T. J.Watson ResearchCenter
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Thursday, June 3Session 21: Special Topics:MEMS Processing andApplications1:30 – 5:10 PMCommittee:AdvancedPackaging
Session Co-Chairs:Joseph W. Soucy - DraperLaboratory, Packaging GroupTel: +1-617-258-2953Fax: +1-617-258-1779Email: [email protected]
Sudipta K. Ray - IBMMicroelectronicsTel: +1-845-894-6240Fax: +1-845-892-6799Email: [email protected]
Wafer Bonding Using MicrowaveHeating of Parylene for MEMSPackagingHong-Seok Noh, Kyoung-Sik Moon,Andrew Cannon, Peter Hesketh and C.P.Wong - Georgia Institute ofTechnology
Enabling Technologies for Wafer-Level Bonding of 3D MEMS andIntegrated Circuit StructuresAnna Topol, Bruce K. Furman, KathrynW. Guarini, Leathen Shi and Guy M.Cohen - IBM Corporation
Novel Microstructuring Technologyfor Glass on Silicon and Glass-SubstratesDietrich Mund and Jürgen Leib -SCHOTT Electronic Packaging GmbH
Lotus Effect Coating and ItsApplication forMicroelectromechanical SystemsStiction PreventionJun Li, Jianwen Xu, Lianhua Fan and C.P. Wong - Georgia Institute ofTechnology
A Wafer-Level Packaging Solutionfor a Piezoresistive MEMS PressureSensor for Harsh OceanicEnvironmental ConditionsAjay Malshe and Ashwin Mohan -University of Arkansas; ShyamAravamudhan and Shekhar Bhansali -University of South Florida
Vacuum Packaging Developmentand Testing for an Uncooled IRBolometer DeviceC. S. Premachandran, Choong SerChong, Chai Tai Chong and MahadevanK. Iyer - Institute of Microelectronics
Location and SensitivityComparison of MEMSAccelerometers in SignalIdentification for AmbulatoryMonitoringTeck Hong Koh, Myo Naing Nyan andFrancis Eng Hock Tay - NationalUniversity of Singapore;Yih Yiow Sitoh- Tan Tock Seng Hospital; Kwong LuckTan - Institute Bioengineering &Nanotechnology
Thursday, June 3Session 22: Bump Reliabilityand Electromigration1:30 – 5:10 PMCommittees:Interconnections / Quality& Reliability
Session Co-Chairs:Senol Pekin - Intel CorporationTel: +1-480-552-4898Email: [email protected]
George G. Harman - NISTTel: +1-301-975-2097Fax: +1-301-948-4081Email: [email protected]
Electromigration Reliability ofSnAgxCuy Flip-Chip InterconnectsJenq-Dah Wu and C.W. Lee - AdvancedSemiconductor Engineering, Inc.
Electromigration Study of High-Lead Solders in Flip-Chip Packagesby Wheatstone Bridge MethodMin Ding, Guotao Wang and Paul S. Ho- University of Texas at Austin; HidekiMatsuhashi - PDF Solutions, Inc.;AmitMarathe, Raj Master and Van Pham -Advanced Micro Devices Inc.
Electromigration in Pb-Free SolderBumpsGlenn Rinne - Unitive Electronics
Electromigration Failure Mechanismof Sn96.5Ag3.5 Flip-Chip SolderBumpsT. L. Shao - AU Optronics Corp.
Flip-Chip Electromigration: Impactof Test Conditions in Product LifePredictionsHaluk Balkan - Kulicke & SoffaIndustries, Inc. - Flip-Chip Division
Thursday, June 3Session 23: High-Speed andParallel Optical Modules1:30 – 5:10 PMCommittee:Optoelectronics
Session Co-Chairs:Torsten Wipiejewski - ASTRITel: +852-3406 2894Fax: +852-3406 2801Email: [email protected]
Mario Dagenais - University ofMarylandTel: +1-301-405-3684Fax: +1-301-314-9281Email: [email protected]
120Gb/s VCSEL-Based ParallelOptical Link and Custom 120Gb/sTesting StationDan Kuchta,Young Kwark, ChristianSchuster, Christian Baks, ChuckHaymes, Jeremy Schaub, PetarPepeljugoski, Lei Shan, Richard John,Daniel Kucharski, Dennis Rogers, MarkRitter, Jack Jewell and Luke Graham -IBM T. J.Watson Research Center; KarlSchrodinger - Infineon TechnologiesAG;Alexander Schild and Hans-Rein -Ruhr-University Bochum
Integration of Micro-Optics with aFiber Array Connector Using PassiveAlignment Technique for ParallelOptics ApplicationsHongtao Han, Jim Morris,Adam Fedor,Eden Chen, Bingzhi Su and HollyWeathersbee - Digital OpticsCorporation
Parallel Optical Interconnect at 10Gb/s per ChannelLisa Buckman Windover, JonathanSimon, Steven Rosenau, Kirk Giboney,Benjamin Law, Graham Flower, LauraMirkarimi,Annette Grot, Chaokun Lin,Ashish Tandon, Glenn Rankin, RussellGruhlke and David Dolfi - AgilentTechnologies, Inc.
4 Channel x 10 Gbit/s OpticalModule for CWDM LinksTakeshi Sakamoto, Nobuo Sato, ShinjiKoike, Koichi Hadama and NaoyaKukutsu - NTT
Silicon Optical Bench for Robust,High-Speed Receiver OpticalSubassembliesChristian Baks, Jeremy Schaub and FuadDoany - IBM Corporation
Transmitter Component for 10.5Gbps at 1310 nm with Receptacleand 50 Ohm FlexboardOliver Stier, Daniel Reznik, FrankMeyer-Güldner, Robert Scholz, GundolfWenger, Nicola Iwanowski and MartinWeigert - Infineon Technologies AG
An Opto-Electronic HybridIntegration Platform with a PolymerOptical Waveguide for HighPerformance and Low-CostModulesTakanori Shimizu,Yuji Akimoto andKazuhiko Kurata - NEC Corporation
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Thursday, June 3Session 24: Shock andVibration Modeling1:30 – 5:10 PMCommittee: Modeling &Simulation
Session Co-Chairs:Pradeep Lall - Auburn UniversityTel: +1-334-844-3424Fax: +1-334-844-3307Email: [email protected]
Tony Mak - Dallas SemiconductorCorporationTel: +1-972-371-4364Fax: +1-972-371-4381Email: [email protected]
Mechanical Shock Testing andModeling of PC MotherboardsBrian Roggeman, Satish Chaparala andPriyank Jain - Binghamton University;Phil Geng - Intel Corporation
Vibration Fatigue Analysis for FCOBSolder JointsJohn H. L. Pang, F. X. Che and T. H. Low- Nanyang Technological University
Free Drop Test Simulation forPortable IC Package by ImplicitTransient Dynamics FEMScott Irving and Yong Liu - FairchildSemiconductor Corporation
Ball-Grid Array Failure EnvelopeDevelopment for Dynamic LoadingKetan Shah and Michael Mello - IntelCorporation
Dynamic Materials Testing andModeling of Solder InterconnectsKai Chuan Ong,Vincent Tan andChwee Teck Lim - National Universityof Singapore; Ee Hua Wong andXiaowu Zhang - Institute ofMicroelectronics
Vibration and Thermo-MechanicalDurability Assessments in AdvancedElectronic Package InterconnectsTse Wong and Harold Fenger -Raytheon Space and Airborne Systems
Advanced Experimental andSimulation Techniques for Analysisof Dynamic Responses During DropImpactTong Yan Tee and Jing-en Luan -STMicroelectronics; Eric Pek andChwee Teck Lim - National Universityof Singapore; Zhaowei Zhong -Nanyang Technological University
Thursday, June 3Session 25: IntegratedInductors1:30 – 5:10 PMCommittee: Components& RF
Session Co-Chairs:Amit P.Agrawal - BroadcomCorporationTel: +1-408-922-7332Fax: +1-408-922-7478Email: [email protected]
Rao Bonda - Motorola, Inc.Tel: +1-480-413-6121Fax: +1-480-413-4511Email: [email protected]
Flip-Chip Based 3D High-QIntegrated InductorsJing-Feng Gong and Philip Chan - HongKong University of Science andTechnology
Fully Embedded LTCC SpiralInductors Incorporating Air Cavityfor High Q-Factor and SRFKichan Eun, Myungsun Song andJaewook Lee - Electronics andTelecommunications Research Institute;Youngchul Lee and Chulsoon Park -Information and CommunicationsUniversity
Super Broadband Lumped Modelsfor Embedded PassivesChih T. Chiu, Jason T.S. Horng andAnderson H.L. Ma - National Sun Yat-sen University; Sung M.Wu and Chih P.Hing - Advanced SemiconductorEngineering, Inc.
Experiments on Embedded PlanarSpiral Inductor Design Optimizationfor FabricationC. K. Liu, P. L. Cheng, S.Y.Y. Leung andD. C. C. Lam - Hong Kong Universityof Science and Technology
On-Wafer Inductors for SOS-BasedRF IC’sPäivi Karjalainen and Eero O.Ristolainen - Tampere University ofTechnology
High-Q Above-IC Inductors andTransmission Lines - Comparison toCu Back-End PerformanceGeert Carchon and Walter De Raedt -IMEC; Xiao Sun - IMEC, div. MCP-MaRS
Tunable Wideband High-AbsorptionBandstop Filter and Low-AbsorptionPhase Shifter Using Ultrathin Fe-GaAs Layer StructuresBoh-Shun Chiu, Hui-Jae Yoo and ChenS.Tsai - University of California, Irvine
Thursday, June 3Session 26: Leading EdgeDesign and Manufacturing inElectronic Applications1:30 – 5:10 PMCommittee: ManufacturingTechnology
Session Co-Chairs:Jie Xue - Cisco Systems, Inc.Tel: +1-603-896-5337Fax: +1-603-896-5033Email: [email protected]
Claude Ladouceur - IBM Canada,Ltd.Tel: +1-450-534-7314Fax: +1-450-534-6773Email: [email protected]
Design and Process Optimizationfor Reliable Resistor Pack SolderJoints for Microprocessor PackagesS. Sidharth, Ranjit Gannamani, CharlieZhai, Richard Blish and Raj Master -Advanced Micro Devices Inc.
Improvement of the Adhesion ofNew Memory Packages by SurfaceEngineeringThomas Herzog, Markus Köhler andKlaus-Jürgen Wolter - TechnischeUniversität Dresden
Development of a High-Reliabilityand Large Volume ManufacturingAssembly Process for a StackedMemory PackageR. Scott Priore and Anthony Burton -Cisco Systems, Inc.
Impact of Component Technologiesand Physical Design Methodologieson High-Density Wireless ProductsTom Swirbel - Motorola, Inc.
Router Flip-Chip Packaging Solutionand ReliabilityEric Tosaya - Procket Networks, Inc.;Sylvain Ouimet and Robert Martel -IBM Canada Ltd.
Development and Evaluation of aHigh-Performance Fine PitchSODIMM® Socket PackagePhillip Li, Jorge Martinez, Jennifer Tang,Scott Priore, Ken Hubbard and Jie Xue- Cisco Systems, Inc.; Mason Hu -Cisco; Edmund Poh, MeiLin Ong andKengYin Chok - Molex; Dave Mendez -Solectron
Integration of Sea of Leads (SoL)Chip-to-Module I/OInterconnections with an Intel Chipand ResultsMuhannad Bakir, Bing Dang and JamesMeindl - Georgia Institute ofTechnology; Ric Emery and GilroyVandentop - Intel Corporation
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Friday, June 4Session 27: BGA/CSPPackaging8:00 – 11:40 AMCommittee:AdvancedPackaging
Session Co-Chairs:Tim Chen - Intel CorporationTel: +1-480-552-8712Email: [email protected]
E. Jan Vardaman - TechSearchInternational, Inc.Tel: +1-512-372-8887Fax: +1-512-372-8889Email: [email protected]
Development of a New ImprovedHigh- Performance Flip-Chip BGAPackageDesmond Y. R. Chong, Beng Kuan Lim,Kenneth J. Rebibis, Shujun Pan,Krishnamoorthi Sivalingam, RahulKapoor,Anthony Y. S. Sun and HienBoon Tan - United Test & AssemblyCenter, Ltd.
Investigation of Cu Stud Bumpingfor Single Chip Flip-Chip AssemblyMatthias Klein, Erik Busse, HermannOppermann and Karin Kaschlun -Fraunhofer IZM
Qualification and Assembly of anEnhanced BGA Package UsingBuild-Up Layers on Heat SpreaderLiyu Yang, Carl King and Ralph Doe -Intel Corporation
Cavity-Down Thermally-EnhancedPackage Reliability Evaluation forLow-K Dielectric / Cu InterconnectsICsChender Huang, Pei-Haw Tsao,AllanLin, Mirng-Ji Lii, D. J. Perng and Nun-Sian Tsai - Taiwan SemiconductorManufacturing Co., Ltd.
Four Layer BGA DesignOptimization for Improved ThermalPerformance and Lower CostTiao Zhou - Texas Instruments;AriannaMorelli and Claudio Villa -STMicroelectronics
High-Performance, Four-Layer,Wire-Bonded, Plastic Ball Grid ArrayPackage for a 10 Gbps per LaneBackplane SerDes TransceiverDon Draper, Ravi Kollipara, Ming Li andDon Mullen - Rambus, Inc.; ScottMcMorrow - Teraspeed ConsultingGroup LLC
A Novel Joint-in-Via, Flip-Chip CSPTeck Kheng Lee and Ah Chin Tan -Micron Semiconductor Asia Pte, Ltd.;Sam Zhang and Chee Cheong Wong -Nanyang Technological University
Friday, June 4Session 28: NovelInterconnections8:00 – 11:40 AMCommittee:Interconnections
Session Co-Chairs:Voya Markovich - EndicottInterconnect Technologies, Inc.Tel: +1-607-755-1978 Fax: +1-607-755-6151 Email: [email protected]
Lei Shan - IBM T.J.WatsonResearch CenterTel: +1-914-945-2304Fax: +1-914-945-4134Email: [email protected]
Innovative Packaging Techniques forWearable Applications UsingFlexible Silicon FibresThomas Healy, Julie Donnelly, JohnAlderman, Brendan O’Neill, KieranDelaney, Kevin Dwane, John Bartonand Alan Mathewson - NMRC, Ireland
Improving Signal Integrity of SystemPackaging by Back-Drilling PlatedThrough Holes in Assembly BoardSergio Camerlo, Bilal Ahmad,Yida Zou,Lekhanh Dang, Mason Hu and ScottPriore - Cisco Systems, Inc.
Integrated Module Board (IMB);AnAdvanced ManufacturingTechnology for Embedding ActiveComponents Inside OrganicSubstratePetteri Palm and Risto Tuominen -Imbera Electronics Oy; Antti Kivikero- Helsinki University of Technology
An Integrated Substrate TechnologyRajen Chanchani, Don Bethke, DeniseWebb, Charlie Sandoval and GreggWouters - Sandia National Labs
Compliant Die-PackageInterconnects at High FrequenciesHenning Braunisch, Kyu-Pyung Hwangand Richard D. Emery - IntelCorporation
Ultrathin Soldered Flip-ChipInterconnections on FlexibleSubstratesBarbara Pahl and Thomas Loeher -Technical University of Berlin; ChristineKallmayer, Rolf Aschenbrenner andHerbert Reichl - Fraunhofer IZM
Fabrication and Parametric Study ofWafer-Level Multiple-Copper-Column InterconnectEbin Liao and Andrew Tay - NationalUniversity of Singapore; Simon Ang -University of Arkansas; Han Hua Feng,Nagarajan Ranganathan and KripeshVaidyanathan - Institute ofMicroelectronics
Friday, June 4Session 29: Portable ProductReliability: Drop,Vibrationand Bending8:00 – 11:40 AMCommittee: Quality &Reliability
Session Co-Chairs:Harry K. Charles - The JohnsHopkins University APLTel: +1-443-778-8050Fax: +1-443-778-6119Email: [email protected]
Sridhar Canumalla - Nokia MobilePhonesTel: +1-469-767-9808Fax: +1-972-894-4988Email:[email protected]
Effect of Thermal Aging on Board-Level Drop Reliability for Pb-FreeBGA PackagesTz-Cheng Chiu, Kejun Zeng, RogerStierman and Darvin Edwards - TexasInstruments, Inc.; Kazuaki Ano - TexasInstruments Japan, Ltd.
Package to Board InterconnectionShear Strength (PBISS) Behavior atHigh Strain Rates ApproachingMechanical DropMurali Hanabe and Sridhar Canumalla -Nokia Corporation
Experimental and NumericalReliability Assessment of CCGASolder Joints Under High-FrequencyVibrationAndy Perkins and Suresh K. Sitaraman- Georgia Institute of Technology
Use-Condition-Based Cyclic BendTest Development for HandheldComponentsLei Mercado, Joe Paul Sedillo, DavidBray, Shubhada Sahasrabudhe and EricMonroe - Intel Corp.; George Lo andKang Joon Lee - George TechnologicalUniversity
Effect of Intermetallic Phases onPerformance in a Mechanical DropEnvironment: Sn3.5Ag Solder on Cuand Ni/Au Pad FinishesSambit Saha, Sesil Mathew and SridharCanumalla - Nokia Corporation
Models for Reliability Prediction ofFine-Pitch BGAs and CSPs in Shockand Drop-ImpactPradeep Lall, Dhananjay Panchagade,Yueli Liu,Wayne Johnson and JeffSuhling - Auburn University
High Drop Test Reliability: Lead-FreeSoldersYoshitaka Toyoda and Takeshi Tashima -Senjyu Industry Inc.
Friday, June 4Session 30: Pb-Free Solders8:00 – 11:40 AMCommittee: Materials &Processing
Session Co-Chairs:Chin C. Lee - University ofCalifornia, IrvineTel: +1-949-824-7462Fax: +1-949-824-3732Email: [email protected]
Kwang-Lung Lin - National ChengKung UniversityTel: + 886-6-2762709Fax: +886-6-2759602Email: [email protected]
Wetting Interaction Between Pb-Free Sn-Zn Series Solders and Cu,Ag SubstratesKwang-Lung Lin and Pei-Chi Liu -National Cheng Kung University
Lead-Free Packaging and Sn-WhiskersJohn Osenbach, Rick Shook, BrianVaccaro and Brian Pottieger - AgereSystems
Aging and Creep Behavior ofSn3.9Ag0.6Cu Solder AlloyQiang Xiao and William D.Armstrong -University of Wyoming; Luu Nguyen -National Semiconductor Corporation
Creep and Fatigue Characterizationof Lead-Free 95.5Sn-3.8Ag-0.7CuSolderJohn H. L. Pang, B. S. Xiong and T. H.Low - Nanyang TechnologicalUniversity
Study of Intermetallic Growth onPWBs Soldered with Sn3.0Ag0.5CuMikyoung Lee,Yuchul Hwang andMichael Pecht - University of Maryland,CALCE EPSC; Jaihyun Park andYoungseop Kim - RIST;Weifeng Liu -Hewlett Packard Company
Materials Interfacial Reactions andIntermetallics Characteristics in theFormation of Micro-Joints with Sn-Pb and Pb-Free Solder AlloysChangqing Liu, Zhiheng Huang, PaulConway and Rachel Thomson -Loughborough University
Lead-Free TQFP Package AchievedJEDEC Level 1/260ºC by SpecificCombination of Die Attach Adhesiveand LeadframeTadashi Takano, Renyi Wang, RichardKuder, Shirley Lam and Kenji Kuriyama- Ablestik; Kazumitsu Seki,Takashi Yoshiand Ayako Saki - Shinko ElectricIndustries Co., Ltd.; Gordon Emmersonand Gordon Seeley - ICI StrategicTechnology Group
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Friday, June 4Session 31: EmergingOptoelectronic Applications8:00 – 11:40 AMCommittee:Optoelectronics
Session Co-Chairs:Christopher D.Theis - TriquintOptoelectronicsTel: +1-484-397-2964Fax: +1-484-397-3057Email: [email protected]
Ping Zhou - GeneralOptoelectronic Devices, Inc.Tel: +1-818-735-7823Email: [email protected]
Optical Data Links for AutomotiveApplicationsEberhard Zeeb and Thomas Kibler -DaimlerChrysler AG
780nm & 850nm VCSELs for HomeNetworks and PrintersHideo Nakayama,Takeshi Nakamuraand Masao Funada - Fuji Xerox Co.,Ltd.;Yuichi Ohashi and Mikihiko Kato -Fuji Photo Film Co., Ltd.
Low-Cost Transceiver Componentsfor Short Distance OpticalInterconnectsFlora Ho, Mark Mak, Ben Lui, EdwinCheung,Allan Hui,Amanda Siu, F.W.Tong, Kin Yau and Torsten Wipiejewski -ASTRI
Design and Simulation of NovelOptoelectronic Interconnect UsingPhotonic Crystal Virtual Waveguidewith Robust Fabrication andMisalignment TolerancesTsuyoshi Yamashita and ChristopherSummers - Georgia Institute ofTechnology
Micromachined Double-Side 45°Silicon Reflectors for Dual-LaserDVD Optical Pickup HeadApplicationsChun-Wen Chang and Wen-Feng Hsieh- National Chiao Tung University; An-Nong Wen - NeostonesMicrofabrication Corporation
Development of a Novel and Cost-Effective Bi-Directional OpticalTriplexer Based on a Polymer PLCPlatformJunehyeon Ahn,Youngmin Lee, KyusubKwak, Dongsung Shin, Sungmin Kimand Taeil Kim - Samsung ElectronicsCo., Ltd.
Mirror Coating and Packaging for aHorizontal MEMS Optical SwitchArrayMing Li, P. S. Chung, M.T.Yeung, P. S.Chan,T. K. Liang, C. Shu, K.W. C. Lai,W.J. Li, F.Tong and H. K.Tsang - ChineseUniversity of Hong Kong
Friday, June 4Session 32: Modeling,Measurement and DesignOptimization8:00 – 11:40 AMCommittee: Modeling &Simulation
Session Co-Chairs:Steve Dvorak - University ofArizonaTel: +1-520-621-6170Fax: +1-520-621-2999Email: [email protected]
Ravi Kaw - Agilent Technologies,Inc.Tel: +1-408-345-8893Fax: +1-408-345-8088Email: [email protected]
Design and Analysis Methodologiesof a 6.4 Gb/s Memory InterconnectSystem Using ConventionalPackaging and Board TechnologiesWendem Beyene and Chuck Yuan -Rambus, Inc.
Design and Optimization of 3D RFModules, Microsystems andPackages Using Electromagneticand Statistical ToolsNathan Bushyager, Daniela Staiculescu,Jong-Hoon Lee, Nikolaos Vasiloglou andManos Tentzeris - Georgia Institute ofTechnology; Lara Martin - Motorola,Inc.
Evaluation of Frequency-DependentTransmission Line Model ExtractionMethods Based on LaboratoryMeasurementsSeth Syverson and David Heckmann -University of North Dakota;TrevorTimpane and Paul Dahlen - IBMCorporation
Optimization of RF/MicrowaveMultichip Module PerformanceBased on Neural Models of Passivesand InterconnectsMustapha C. E.Yagoub and PrasunSharma - University of Ottawa
Broadband Via Transition Analysisand CharacterizationAlbert Chee Wai Lu, Lai L.Wai,WeiFan and Lin Jin - Singapore Institute ofManufacturing Technology
Calibration of Near-FieldMeasurements Using MicrostripLine for Noise PredictionsMadhavan Swaminathan, KrishnaSrinivasan and Rao Tummala - GeorgiaInstitute of Technology; Hideki Sasaki -NEC Corporation
Electromagnetic Interference Issuesfor Mixed-Signal System-on-Package (SOP)Hideki Sasaki - NEC Corp.;VinuGovind, Krishna Srinivasan, SidharthDalmia,Venky Sundaram, MadhavanSwaminathan and Rao Tummala -Georgia Institute of Technology
Friday, June 4Session 33: ManufacturingAdvances for NextGeneration Technologies8:00 – 11:40 AMCommittee: ManufacturingTechnology
Session Co-Chairs:Kitty Pearsall - IBM CorporationTel: +1-512-838-7004Fax: +1-512-823-7544Email: [email protected]
Shawn Shi - IntelTel: +1-480-554-2155Fax: +1-480-552-1304Email: [email protected]
High Reliability Second-LevelInterconnects Using Polymer CoreBGAsSashidhar Movva - Kyocera America,Inc.
Effect of Organic Package Core ViaPitch Reduction on PowerDistribution PerformanceJean Audet - IBM Canada Ltd.; MichaelGrinberg, Daniel O’Connor and JimLibous - IBM Corporation
Process and Design Analysis of UltraFine-Pitched Wiresweep Eliminationfor Advanced Copper HeatSpreader BGA PackageSurasit Chungpaiboonpatatana -Conexant (Mindspeed) Corporation;Frank Shi - University of California,Irvine
High-Frequency Thermosonic Flip-Chip Bonding for Gold to GoldInterconnectionCharles C. H. Pang and Kin-Yik Hung -ASM Assembly Automation Ltd.; Man-Lung Sham - Hong Kong University ofScience and Technology
Comparison of Via-FabricationTechniques for Through-WaferElectrical Interconnect ApplicationsAlexander Polyakov, Ines Eidner, MarianBartek and Joachim N. Burghartz -Delft University of Technology;TimonGrob, Ron A. Hovenkamp, Henk J.Kettelarij and Marc A. de Samber -Philips CFT Eindhoven
Innovative Solutions to EnableSmaller Substrate Bump Pad Sizefor Flip-Chip TechnologySeaw Lai Cheah, Chee Koang Chen,Kuljeet Singh,Toon Yoon Ang, C. C.Loke, Mun Lin Lai and Anita Earley -Intel Corporation
A High Throughput OptoelectronicModule Assembly ProcessPaul Schwab,Terry Bowen, RichardPerko and Nuri Delen - TycoElectronics, Inc.; Richard Anderson andJoel Goodrich - MACOM Inc.
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Friday, June 4Session 34:Wafer-LevelPackaging1:30 – 5:10 PMCommittee:AdvancedPackaging
Session Co-Chairs:Daniel Baldwin - Georgia Instituteof TechnologyTel: +1-404-894-4135Fax: +1-404-894-9342Email:[email protected]
Yee L. Low - Lucent Technologies Bell LabsTel: +1-908-582-2718Fax: +1-908-582-6228Email: [email protected]
Constrained Collapse Solder JointFormation for Wafer Level-ChipScale Packages to AchieveReliability ImprovementViraj Patwardhan, Hau Nguyen, NikhilKelkar and Li Zhang - NationalSemiconductor Corporation
A Low-Temperature Wafer-LevelHermetic Package Using UVCurable AdhesiveZhi-Hao Liang,Yu-Ting Cheng andWensyang Hsu - National Chiao TungUniversity;Yuh-Wen Lee - IndustrialTechnology Research Institute
Low-Cost,Wafer Level Underfillingand Reliability Testing of Flip-ChipDevicesAlan Grieve, M.Albert Capote, HowardA. Lenos and Arsenia Soriano - AguilaTechnologies, Inc.
Reaching Détente in the Design andMaterial Selection for Hi Rel WL-CSPsGlenn Rinne - Unitive Electronics;Craig Schuckert - HD MicroSystems
Effect of Wafer-Level Packaging,Silicon Substrate and BoardMaterial on Gigabit Board-Silicon-Board Data TransmissionMadhavan Swaminathan, R. Madhavan, J.Mao, D. Ravi, Z. Zhang, George Lo andC. P. Wong - Georgia Institute ofTechnology; S. Sitaraman, M. Iyer and M.Rotaru - Institute of Microelectronics;A.Tay - National University ofSingapore
Wafer-Level Interconnects for 3DPackagingRiki Banerjee and Rhonda Drayton -University of Minnesota
Circuit Partitioning and RF Isolationby Through-Substrate TrenchesSaoer M. Sinaga,Alexander Polyakov,Marian Bartek and Joachim N.Burghartz - Delft University ofTechnology
Friday, June 4Session 35: Board-Level andEmbedded OpticalInterconnects1:30 – 5:10 PMCommittees:Optoelectronics /Interconnections
Session Co-Chairs:Jean Trewhella - IBM T. J.WatsonResearch CenterTel: +1-914-945-2786Fax: +1-914-945-1974Email: [email protected] Matijasevic - Univeristy ofCalifornia, IrvineTel: +1-949-824-9830Fax: +1-949-824-3732Email: [email protected] Optical Interconnectionsin Printed Wiring BoardsTakeshi Suzuki - Matsushita ElectricIndustrial Co., Ltd.;Toshihisa Nonaka -Toray Industries, Inc.; Nobuyuki Ogawa- Hitachi Chemical Co., Ltd.; Sang-YeonCho and Sang-Woo Seo - GeorgiaInstitute of Technology; Nan MarieJokerst - Duke University,Optical Path Redirected Three-Dimensional Lightguide Connectorsfor High-Speed InterconnectionModulesSeiki Hiramatsu, Masao Kinoshita,Takashi Mikawa and Osamu Ibaragi -Association of Super-AdvancedElectronics Technologies (ASET);Hidetoshi Nanai - Central Glass Co.,Ltd.;Takumi Yoshida and Shuji Suzuki -Hirose Electric Co., Ltd.Heterogeneous Integration ofInP/InGaAsP MQW Thin Film EdgeEmitting Lasers and PolymerWaveguidesHung-Fei Kuo, Sang-Yeon Cho and NanJokerst - Georgia Institute ofTechnologyOptical Interconnects on PrintedCircuit Board Level - Results Basedon the German Funded ProjectOPTICONMartin Franke and Frank-PeterSchiefelbein - Siemens AGHigh-Efficiency OpticalInterconnection Using 45 Degree-Ended Connection Blocks in Fiber-and Waveguide-Embedded PCBsByung Sup Rho, Mu Hee Cho, Han SeoCho and Hyo-Hoon Park - Informationand Communications University;Kyoung-Up Shin, Sang-Won Ha andByoung-Ho Rhee - Samsung Electro-Mechanics Co.; Dong-Su Kim, Sun TeaJung and Taeil Kim - SamsungElectronics Ltd.Demonstration of an MT-Compatible Connectorisation of aLaser-Ablated OpticalInterconnection on a Printed CircuitBoardGeert Van Steenberge, Peter GeerInc.k,Steven Van Put and Peter Van Daele -Ghent University; Jan Van Koetsem andDanny Morlion - FCI ‘s-Hertogenbosch1K-Channel Optical Interconnectsof CMOS-PQR Flip-ChipO’Dae Kwon, Sangkyeom Kim, MoojinKim, Seungeun Lee, Dongkwon Kimand Junho Yoon - Pohang University ofScience and Technology; Kwonsub Lim,Jungyeon Kim and Byunghun Park -Samsung Electronics Co., Ltd.
Friday, June 4Session 36:Thermo-Mechanical Modeling ofPackage and Interconnect1:30 – 5:10 PMCommittee: Modeling &Simulation
Session Co-Chairs:Erdogan Madenci - University ofArizonaTel: +1-520-621-6113Fax: +1-520-621-8191Email:[email protected]
Michael Lamson - TexasInstruments, Inc.Tel: +1-972-995-2490Fax: +1-972-995-2658Email: [email protected]
Isothermal Fatigue Test of Wafer-Level Chip Scale Package (WLCSP)and Plastic Ball Grid Array (PBGA)Lead-Free Solder Joints on PrintedCircuit Board (PCB) with ImmersionSilver (ImAg) Surface FinishJohn Lau - Agilent Technologies, Inc.;Ricky Lee - Hong Kong University ofScience and Technology; DongkaiShangguan - Flextronics
Leading Indicators of Failure forPrognosis of Electronic and MEMSPackagingPradeep Lall, Nokibul Islam, KaysarRahim and Jeff Suhling - AuburnUniversity
Accelerated Thermal Cycling: Is ItDifferent for Pb-Free Solder?Krishna Tunga, Karan Kacker, RaghuramPucha and Suresh Sitaraman - GeorgiaInstitute of Technology
Fatigue Life Estimation of an Ultra-Fine-Pitch Solder Column WaferLevel Package Using the Macro-Micro Modeling ApproachAudrey Chng,Andrew Tay and KianMeng Lim - National University ofSingapore; Ee Hua Wong - Institute ofMicroelectronics
Influence of Interfacial Complianceon Thermomechanical Stresses inMultilayered MicroelectronicsPackagingYujun Wen and Cemal Basaran - StateUniversity of New York, Buffalo
Applied FEM Techniques in CeramicFeedthru Package DesignMark Eblen - Kyocera America, Inc.
Stacked-Chip Packaging: Electrical,Mechanical, and ThermalChallengesJ. J. Maloney, Richard S. Graf, HanyiDing, Elie Awad and Geoff Simson -IBM Corporation
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Thursday, June 3Session 37: Substrates andBumps1:30 – 5:10 PMCommittee: Materials &Processing
Session Co-Chairs:Ceferino Gonzalez - DuPontAdvanced Fibers SystemsTel: +1-919-248-5062Fax: +1-360-285-6000Email:[email protected]
Yeong Lee - Dow Corning Tel: +1-989-496-7032Fax: +1-989-496-7084Email:[email protected]
Integrated RF Module Produced byAerosol Deposition MethodYoshihiko Imanaka - FujitsuLaboratories, Ltd.; Jun Akedo - NationalInstitute of Advanced Industrial Scienceand Technology (AIST)
A Novel Highly Heat ResistantSubstrate Material for Halogen-FreeApplicationsKenji Shima, Kousuke Hirota, KoutarouAsahina and Takashi Iiyama - MitsuiChemicals, Inc.
Materials, Process and Reliability ofMixed Signal Microvia Substratesfor SOP TechnologyRaghuram Pucha, Saketh Mahalingam,Suresh Sitaraman,Venky Sundaram,Fuhan Liu,White George and RaoTummala - Georgia Institute ofTechnology
Flip-Chip Bump Integrity withCopper/Ultra Low-K DielectricsVaidyanathan Kripesh, Hong Yu Li, ChaoYong Li,Yong Ji Jeffrey Su andMahadevan K. Iyer - Institute ofMicroelectronics
Fluxless Flip-Chip Technique withElectroplated Sn/Au BumpsDongwook Kim, Jongsung Kim andChin C. Lee - University of California,Irvine
Characterization of NanocrystallineCopper and Nickel forNanointerconnect ApplicationsShubhra Bansal,Ashok Saxena and RaoTummala - Georgia Institute ofTechnology
Effect of Substrate Material andSolder Ball Pitch on ReliabilitySubhotosh Khan - DuPont - AFS;Mohamed Asaduzzaman, MarkLamontia and Jay Sloan - DuPont -DuET
Friday, June 4Session 38: RF Modules1:30 – 5:10 PMCommittee: Components& RF
Session Co-Chairs:Craig Gaw - Motorola, Inc.Tel: +1-480-413-5920Fax: +1-480-413-3481Email: [email protected]
Lih-Tyng Hwang - Motorola, Inc.Tel: +1-847-576-5182Fax: +1-847-435-3780Email: [email protected]
Multi-Band RF and mm-WaveDesign Solutions for Integrated RFFunctions in Liquid Crystal PolymerSystem-On-Package TechnologyValeria Palazzari - Universita’ diPerugia; Dane Thompson, NikkoPapageorgiou, Stephane Pinel, Jong-Hoon Lee, Saikat Sarkar, Rana Pratap,Gerald De Jean, RamananBairavasubramanian, Rong-Lin Li andManos Tentzeris - Georgia Institute ofTechnology
A Multiple Frequency SignalGenerator for 802.11a/b/g VoWLANType Applications Using OrganicPackaging TechnologySidharth Dalmia,Amit Bavisi, SouvikMukherjee,Vinu Govind, GeorgeWhite, Madhavan Swaminathan andVenkatesh Sundaram - GeorgiaInstitute of Technology
Characterization of TransferMolding Effects on RF Performanceof Power Amplifier ModuleLi Li,Anju Kapur and Ken BriceHeames - Motorola, Inc.
Design Consideration for System-in-a-Package with Embedded PassiveCircuitsGye-An Lee and Franco De Flaviis -University of California, Irvine;Mohamed Megahed - SkyworksSolution, Inc.
System-on-Package Based CMOSVoltage Controlled OscillatorTae-Je Cho and Se-Yong Oh - SamsungElectronics Co., Ltd.; Sang-WoongYoon, Kyutae Lim, Stephane Pinel, JoyLaskar, Swapan Batthacharya and RaoTummala - Georgia Institute ofTechnology
Chip-Package Co-Design of aConcurrent LNA in System-on-Package for Multi-Band RadioApplicationsTommi Torikka and Esa Tjukanoff -University of Turku; Xinzhong Duo, Li-Rong Zheng and Hannu Tenhunen -Royal Institute of Technology
System-on-a-Package (SOP) ModuleDevelopment for a Digital, RF andOptical Mixed-Signal IntegratedSystemKyutae Lim, Lixi Wan, Daniel Guidotti,Stephane Pinel,Venkatesh Sundaram,George White, Fuhan Liu, SwapanBhattacharya, Ravi Doraiswami, ManosTentzeris, Joy Laskar and Rao Tummala- Georgia Institute of Technology
Friday, June 4Session 39: EducationalInitiatives for the 21stCentury1:30 – 5:10 PMCommittee: Education
Session Co-Chairs:Paul Wesling - ConsultantTel: +1-408-252-9051Fax: +1-408-285-9670Email: [email protected]
Leyla Conrad - Georgia Instituteof TechnologyTel: +1-404-385-0439Fax: +1-404-894-3842Email:[email protected]
Electronics Packaging;A Course forthe Rutgers UniversityMichael Caggiano and Ka-Mun Ho -Rutgers University
Undergraduate Students’ ResearchActivitiesPaul Svasta,Virgil Golumbeanu, CiprianIonescu, Daniel Victoras Ene, RocsanaIonescu and Diana Sinzeana Chirileasa- Politehnica University of Bucharest
Development of a Curriculum inNano and MEMS Packaging andAjay P. Malshe - University of Arkansas
Research and Education in MEMSand Optoelectronics Packaging inSheng Liu - Wayne State University;Sheng Liu - Huazhong University ofScience and Technology
Multi-Level Education Curriculumof Electronics ManufacturingEngineering in GUETD. G.Yang, Ling Sun and Xiaosong Ma -Guilin University of ElectronicTechnology
Process Technology of Electronics - AGraduate TextbookThomas Zerna, Martin Oppermann,Wilfried Sauer and Klaus-JuergenWolter - Dresden University ofTechnology
Distance Learning - How to Use thisNew Didactic Method in Educationof Electronics EngineeringZsolt Illyefalvi-Vitez and Peter Gordon- Budapest University of Technologyand Economics
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Wednesday, June 2 and Thursday, June 3PostersCommittee: Posters
Session Co-Chairs:Michael CaggianoTel: +1-732-445-0678Fax: +1-732-445-2820Email: [email protected]
Swapan BhattacharyaGeorgia Institute of TechnologyTel: +1-404-385-0708Fax: +1-404-894-0957Email: [email protected]
Active Devices and Wiring Under ChipBondpads: Stress Simulations and ModelingMethodologyElie Awad - IBM Corporation
Reliability of Large Organic Flip-ChipPackages for Industrial TemperatureEnvironmentsAnurag Bansal and Yuan Li - AlteraCorporation
A Thermodynamic Model for ElectricalCurrent Induced Damage inMicroelectronics Solder JointsCemal Basaran - State University of New York,Buffalo
Development of a Fully Automated Low-Cost High-Throughput Menis CoatingMethod for Large Format SOP SubstratesSwapan Bhattacharya, Sachin Bhatevara, GaryMay and Rao Tummala - Georgia Institute ofTechnology
Broadband Electrical Characterization of aFlip-Chip InterconnectAndrew Byers and Laudie Doubrava -Tektronix
High-Frequency Characterization ofDifferential Signals in Flip-Chip OrganicPackageCharles Chiu and Hanyi Ding - IBMCorporation
Study of Assembly Processes for LiquidCrystal on Silicon (LCoS) MicrodisplaysAnupam Choubey, Bahgat Sammakia and FrankAndros - State University of New York,Binghamton
Simulation Study of Power DeliveryPerformance on Flip-Chip SubstrateTechnologiesMusawir Chowdhury - Agere Systems; Jin Zhaoand Raymond Chen - Sigrity, Inc.
Liquid Crystalline Polymer BasedRF/Wireless Components for Multi-BandApplicationsSidharth Dalmia,Venkatesh Sundaram, GeorgeWhite and Madhavan Swaminathan - GeorgiaInstitute of Technology
Co-Design Optimization of LaminateSubstrates for High Speed ApplicationsDaniel de Araujo, Moises Cases, Nam Pham andErdem Matoglu - IBM Corporation
Impediments to Impedance & CoupledNoiseMatt Doyle - IBM Corporation
LTCC and Thick-Film MicroresistorsAndrzej Dziedzic and Edward Mis - Universityof Technology,Wroclaw; Lars Rebenklau andKlaus-Jurgen Wolter - Dresden University ofTechnology
The Challenge of Ultra-Thin Chip AssemblyMichael Feil, Cliff Adler and DieterHemmetzberger - Fraunhofer IZM; MartinKönig and Karlheinz Bock - Fraunhofer IZM,Munich
Moisture and Temperature Effects on theReliability of Interfacial Adhesion of aPolymer/Metal InterfaceTimothy Ferguson and Jianmin Qu - GeorgiaInstitute of Technology
Design of Multiband Baluns on LiquidCrystalline Polymer (LCP) Based SubstratesVinu Govind, Sidharth Dalmia,Venky Sundaramand Madhavan Swaminathan - Georgia Instituteof Technology; George White - Jacket MicroDevices, Inc.
Test Vehicle to Characterize Silicon toOrganic Flip-Chip PackageThermomechanical FailuresDongming He, Sriram Srinivasan, SairamAgraharam, Biju Chandran, Mike Mello, PankajSinha and Vasu Atluri - Intel Corporation
Design, Fabrication, and Reliability Testingof Embedded Optical Interconnects onBoardShashikant Hegde, Suresh Sitaraman, RaghuramPucha, Daniel Guidotti, Fuhan Liu and RaoTummala - Georgia Institute of Technology
A Novel Fiber Alignment Shift MeasurementTechnique Employing an Ultra-HighPrecision Laser Displacement Meter inLaser-Welded Laser Module PackagingYi-Cheng Hsu,Yeh-Lin Ho,Ying-Chien Tsai, Jao-Hwa Kuang and Wood-Hi Cheng - NationalSun Yat-sen University; Maw-Tyan Sheen - YungTa Institute of Technology and Commerce
A Comparison Study between Eutectic Au-Si and Au-Sn Solders as Die AttachMaterials for High Power DevicesJin-Wook Jang, Scott Hayes, Jong-Kai Lin andDarrel Frear - Motorola, SPS
Computer-Aided Thermal, Mechanical andOptical Simulation for Parallel OpticalSubassembly DesignChih-Ting Kao, Chih-Hsiang Ko, Shu-Jung Yang,Chun-Hsun Tsai,Yii-Tay Chu and Rex Chiou -Industrial Technology Research Institute
Measurement of Deformation and Strain inFlip-Chip on BGA (FC-BGA)Liam Kehoe,VIncent Guénebaut and PatriceKelly - Optical Metrology Innovations, Ltd.
Sensitivity Analysis of On-Chip Delta-INoise CalculationBernd Kemmler and Andreas Huber - IBMDeutschland Entwicklung GmbH
Electrical Characteristics of Fine-Pitch Flip-Chip Solder Joints Fabricated UsingLow-Temperature SoldersYoung-Ho Kim and Un-Byoung Kang - HanyangUniversity
C-SiC Package /Board Materials Technologyfor Next Generation Convergent MicroSystemsNitesh Kumbhat, P. Markondeya Raj, RaghuramPucha, Shashikant Hegde, Ravi Doraiswami,Swapan Bhattacharya, Suresh Sitaraman andRao Tummala - Georgia Institute of Technology;Steve Atmur and Susan Hayes - StarfireSystems
The Effect of Tg on Thermo-MechanicalDeformation and Reliability of AdhesiveFlip-Chip Assemblies During TemperatureCyclingWoon-Seong Kwon, Se-Young Yang, Soon-BokLee and Kyung-Wook Paik - Korea AdvancedInstitute of Science and Technology
The Solder Joint Characterization in GreenWLCSPJeffrey C. B. Lee - ASE Corp.; S.W Li -Advanced Semiconductor Engineering,Inc.
Chip-on-Chip 3D Optical Interconnect withPassive AlignmentRicky Lee and Jeffery Lo - Hong KongUniversity of Science and Technology
Modeling of Embedded Inductor on Low-Cost Multilayer Laminate MCM Technologyand Its ApplicationRyan Lee, Jeremy Goodrich and Anil Agarwal -Skyworks Solutions, Inc.
High Manufacturability and ThermalStability Mini-Flat Transmitter for 10Gb/sEthernet ApplicationsShin-Ge Lee, Chih-Li Chen, Chu-Li Chao,Chun-Hsing Lee, Li-Chun Liao, Chih-Hao Hsu,Fu-Yi Cheng, Cheng-Hung Tsai, Min-Fa Huangand Chiung-Hung Wang - Industrial TechnologyResearch Institute
27
Photolithography of 3D Topology in SiOptical Bench for Self-Aligned Placementof Laser DiesMing Li, H. K.Tsang and C. Shu - ChineseUniversity of Hong Kong; C.W. Law,Y. K. Lauand R.W. M. Kwok - Shipley Asia, Ltd.; X.W. Huand H. L. Zhu - Institute of Semiconductors
Electrical Property of AnisotropicallyConductive Adhesives Joint Modified bySelf-Assembled MonolayerYi Li, Kyoung-Sik Moon and C. P. Wong -Georgia Institute of Technology
Conductivity Improvement of IsotropicConductive Adhesives with Short-ChainDicarboxylic AcidsYi Li, Kyoung-sik Moon, Haiying Li and C. P.Wong - Georgia Institute of Technology
ShapeTControlled Synthesis ofNanoparticles and Their Incorporation intoPolymersYi Li, Suresh Pothukuchi and C. P.Wong -Georgia Institute of Technology
Polymeric Waveguides on Rigid and FlexiblePCBWei-Chung Lo, Li-Cheng Shen, Hsiang-HungChang, Huan-Chun Fu,Yu-Chih Chen, Shu-MingChang,Yuan-Chang Lee,Wun-Yan Chen andMing-Chieh Chou - Industrial TechnologyResearch Institute
Optimizing the Output Impedance of aPower Delivery Network forMicroprocessor SystemsOm Mandhana - Motorola, Inc.
Wafer-Level Integration of On-ChipAntennas and RF PassivesPaulo Mendes - University of Minho / DelftUniversity of Technology; Saoer Sinaga,Alexander Polyakov, Marian Bartek and JoachimBurghartz - Delft University of Technology;Higino Correia - University of Minho
Nano-Metal Particles for Low-TemperatureInterconnect TechnologyKyoung-Sik Moon, Hai Dong,Yi Li, SureshPothukuchi and C. P.Wong - Georgia Instituteof Technology
Lead-Free Solder Interconnect by VariableFrequency Microwave (VFM)Kyoung-Sik Moon,Yi Li, Jianwen Xu and C. P.Wong - Georgia Institute of Technology
High Thermal Dissipation Transfer MoldedPackage for Power ModulesDai Nakajima, Kazuhiro Tada and YoshihiroKashiba - Mitsubishi Electric Corporation;Taishi Sasaki and Takeshi Shikano - FukuryoSemicon Engineering Corporation Japan
Heat Spreader Impact on ElectricalPerformances of a 4-Layer PBGA PackageShujun Pan and Anthony Sun Y.S. - United Test& Assembly Center, Ltd.
An Accurate Electromagnetic Modeling ofthe Die-to-Die Interconnect Link forGigabit Systems ApplicationsVictor Prokofiev, Udy Shrivastava, Lesley Polkaand Michael Hill - Intel Corporation
High Aspect Ratio Metal-PolymerComposite MEMS Structures for TunableCapacitors and Wafer-Level NanoInterconnectsP. Markondeya Raj,Ankur Aggarwal, KianoushNaeli, Farrokh Ayazi, Swapan Bhattacharya andRao Tummala - Georgia Institute of Technology
Electromagnetic Noise Mitigation in High-Speed Printed Circuit Boards and PackagesUsing Electromagnetic Band Gap StructuresShahrooz Shahparnia, Baharak Mohajeriravaniand Omar Ramahi - University of Maryland
LCP Injection Molded Packages-Keys toJEDEC 1 PerformanceRichard Ross - RJR Polymers, Inc.
Modeling and Hardware Correlation ofPower Distribution Networks for Multi-Gigabit DesignsRalf Schmitt, Xuejue Huang, Ling Yang andChuck Yuan - Rambus, Inc.
FR4 Printed Circuit Board Design for Giga-bits Embedded Optical InterconnectApplicationsJaemin Shin, Cheolung Cha, Sang-Yeon Cho andJaehong Kim - Georgia Institute of Technology;Nan Marie Jokerst and Martin Brooke - DukeUniversity
RF Modeling and Design of Flip-ChipConfigurations of Microwave Devices onPCBsYoung Song - University of California, Irvine
Ultrathin Patterned GraphiteNanoelectronicsZhimin Song, Clair Berger and Walt De Heer -Georgia Institute of Technology
Package-Level Performance Analysis Basedon Laser Diode Far Field DistributionYakov Soskind, Jeff Perkins and Jack Tomlinson -JDS Uniphase Corporation
A Micromechanics Model for ElectricalConduction in Isotropically ConductiveAdhesives During CuringBin Su and Jianmin Qu - Georgia Institute ofTechnology
Process Characterization and Issues inLTCC AssemblyVasudivan Sunappan,Arulvanan Periannan andChua Kai Meng - Singapore Institute ofManufacturing Technology
Components’ Emisivity Influence in ReflowSoldering ProcessPaul Svasta, Daniel Simion-Zanescu andRocsana Ionescu - Politehnica University ofBucharest; Gabriel Popovici - Micronix Plus
A Leadless Packaging Concept for High-Frequency ApplicationsHorst Theuss, Jochen Dangelmaier, Mario Engl,Klaus Pressel,Werner Simbürger, HerbertKnapp, Klaus Gnannt,Wolfram Eurskens andJosef Hirtreiter - Infineon Technologies AG
Effect of Spin Coating on the Adhesion ofEpoxy Adhesive on Si Substrate for theFabrication of Polymer Optical WaveguideM.A. Uddin, H. P. Chan and C. K. Chow - CityUniversity of Hong Kong
Time Domain Analysis of the SignalIntegrity of a 1Gbps 4-Module Memory Buswith a Broadband Ceramic DirectionalCoupler Designed in the FrequencyDomain.Yutaka Uematsu, Hideki Osaka, Hiroaki Ikedaand Yasunori Sakisaka - Hitachi
Parametric Study of Warpage of PWBAssemblies and PWB Assembly WarpageMinimization by Component LayoutOptimizationI. Charles Ume - Georgia Institute ofTechnology; Hai Ding - Intel Corporation
Embedded Passives Technology forBluetooth Application in Multi-LayerPrinted Wiring BoardChing-Liang Weng - Industrial TechnologyResearch Institute; Pel-Shen Wei, Chun-KunWu, Chang-Sheng Chen, Uei-Ming Jow andYing-Jiunn Lai - ERSO,ITRI; Shur-Fen Liu -Materials Research Laboratories,ITRI
Packaging of Thermally Tunable Fiber BraggGrating SensorLing Xie, D. Pinjala, K. Sudharsanam, RamanaPamidighantam and Navas Khan - Institute ofMicroelectronics; Jingbo Zhang,Wanxun Heand Baoxi Xu - Data Storage Institute
High Coupling Tapered Hyperbolic FiberMicrolensHuei-Min Yang, Sun-Yuan Huang, Chao-Wei Leeand Shih-Hung Wang - National Sun Yat-senUniversity
A Novel Silica Planar Waveguide Structurewith High Thermal EfficiencyEnchao Yu and Dawei Zheng - Consultant
Process Considerations and Long TermThermal Performance of Power Packageswith Heat Slug Soldered to PCBTiao Zhou - Texas Instruments; Mike Hundt -STMicroelectronics
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Please indicate howmany luncheon
tickets are needed.PRIMARY AREA OF INTEREST (Check One)___Advanced Packaging ___Interconnections ___Modeling & Simulation___Components & RF ___Manufacturing Technology ___Optoelectronics___Connectors & Contacts ___Materials & Processing ___Quality & Reliability
ECTC/ITHERM Joint RegistrationJoint ECTC/ITHERM Advance . . . . . . . . . . . . . . . . . . .$750(Joint Door Registration $800; includes both luncheons and proceedings.)
29
June 1, 2004Morning Professional
Development Courses8:15 AM - 12:00 PM
1. Optoelectronics Compon- ents and Modules for Communication Networks
2. Advanced Organic Substrate Package Design & Manufacturing for RF and Broadband
3. Integrated Passive Technology and Commercialization
4. Polymers for Electronic Packaging
5. System-On-Package (SOP) vs. System-In-Package (SIP), and System-On-Chip (SOC)
6. “Nano” - The Next Technology?
7. Microelectronic and MEMS Sensors
8. Microelectronics Packaging and Interconnection - A Worldwide Perspective
June 1, 2004Afternoon ProfessionalDevelopment Courses
1:15 - 5:00 PM
9. RF/Wireless Packaging10. Wafer Level - Chip
Scale Packaging11. Microvias & High-
Density Interconnects for Advanced Packaging
12. Interconnect and Packaging Technologies for 10 and 40GBPS Telecom and Datacom
13. Package Failure Analysis - Failure Mechanisms and Analytical Tools
14. Advanced Thermal Management Materials
15. Introduction to Nanoscale Packaging and Systems
16. Lead-Free Solders for Robust IC Electronic and Optoelectronic Packaging
June 1, 2004NEMI Tin Whisker
Workshop8:15 AM - 5:00 PM
June 2, 2004Technical Sessions
8:00 - 11:40 AM
S1 SIP/SOPS2 Pb-Free Flip-ChipS3 Innovative Testing
MethodsS4 Adhesives and
EncapsulantsS5 Optoelectronic
Packaging TechnologyS6 Electrical ModelingS7 Integrated Capacitor
and Resistor Technology
June 2, 20041:30 - 5:10 PM
S8 Flip-Chip PackagingS9 WirebondS10 Characterization of
Failure Mechanisms in Advanced Packaging
S11 Nanoscale and Emerging Technologies
S12 Materials for Embedded Passives
S13 Power Delivery
June 3, 20048:00 - 11:40 AM
S14 3D PackagingS15 Pb-Free Flip-Chip IIS16 Pb-Containing and Ob-
Free Solder Joint Reliability
S17 Flip-Chip UnderfillS18 Optoelectronics Manu-
facturing TechnologyS19 MEMS PackagingS20 Thermal and Thermo-
Mechanical Modeling of Packaging Polmer and Low-K Dielectrics
June 3, 20041:30 - 5:10 PM
S21 Special Topics: MEMS Processing and Applications
S22 Bump Reliability and Electromigration
S23 High-Speed and Parallel Optical Modules
S24 Shock and Vibration Modeling
S25 Integrated InductorsS26 Leading-Edge Design and
Manufacturing in Electronic Applications
June 4, 20048:00 - 11:40 AM
S27 BGA/CSP PackagingS28 Novel InterconnectionsS29 Portable Product
Reliability: Drop,Vibration and Bending
S30 Pb-Free SoldersS31 Emerging Optoelectronic
ApplicationsS32 Modeling, Measurement
and Design OptimizationS33 Manufacturing Advances
for Next-Generation Technologies
June 4, 20041:30 - 5:10 PM
S34 Wafer-Level PackagingS35 Board-Level and
Embedded Optical Interconnects
S36 Thermo-Mechanical Modeling of Package and Interconnect
S37 Substrates and BumpsS38 RF ModulesS39 Educational Initiatives for
the 21st Century
June 2, 20041:30 - 6:00 PM
S40 Poster Session 1
June 3, 20041:30 - 6:00 PM
S41 Poster Session 2
June 2, 20041:30 - 6:00 PM
Technology Corner Exhibits
June 3, 20049:00 AM - 12:00 PM
1:30 - 6:00 PMTechnology Corner Exhibits
Conference Overview
Session Summary byInterest Area
Advanced PackagingS1, S8, S14, S21, S27, S34
Components & RFS7, S25, S38
EducationS39
InterconnectionsS2, S9, S15, S28, S35
Manufacturing TechnologyS26, S33
Materials & ProcessingS4, S12, S17, S30, S37
Modeling & SimulationS6, S13, S20, S24, S32, S36
OptoelectronicsS5, S18, S23, S31, S35
PosterS40, S41
Quality & ReliabilityS3, S10, S16, S22, S29
Special TopicsS11, S19
Electronic Industries Alliance2500 Wilson Boulevard
Arlington,VA 22201-3834
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Electronic Industries Alliance2500 Wilson Boulevard
Arlington,VA 22201-3834
PAR AVION
INTERNATIONAL PRIORITY AIRMAIL
FIRST CLASSU.S. POSTAGE
PAIDGREENVILLE, SCPERMIT NO. 113
Sponsored by:
Mailroom:If the person on this label is no longer employed at yourcompany, please route this information brochure to his/herreplacement or department manager.
Route to:______________________________________________________________________________Attn: Engineers, scientists and technical managers