[email protected] pattern gas detectors. towards an r&d collaboration cern, 10 september...

[email protected] Micro Pattern Gas Detectors. Towards an R&D Collaboration CERN, 10 September 2007 1

P. Baron1, A. Delbart1, X. de la Broise1, D. Calvet1, E. Delagnes1, F. Druillole1,

J-L. Fallou1, E. Mazzucato2,F. Pierre2, A. Sarrat2, , E. Virique1, E. Zonca1, M. Zito2.

1CEA Saclay, DSM/DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex , France

2CEA Saclay, DSM/DAPNIA/SPP, 91191 Gif-sur-Yvette Cedex , France

P. Baron1, A. Delbart1, X. de la Broise1, D. Calvet1, E. Delagnes1, F. Druillole1,

J-L. Fallou1, E. Mazzucato2,F. Pierre2, A. Sarrat2, , E. Virique1, E. Zonca1, M. Zito2.

1CEA Saclay, DSM/DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex , France

2CEA Saclay, DSM/DAPNIA/SPP, 91191 Gif-sur-Yvette Cedex , France

AFTER- TPC readout electronicsAFTER- TPC readout electronics

•The T2K experiment

•The TPC

•Electronic architecture

•The AFTER ASIC

•Results

•Status

•Conclusions

LollyPollaccoModified the fileOf Pascal Baron

2CERN, 10 September 2007Micro Pattern Gas Detectors. Towards an R&D Collaboration

The T2K experimentThe T2K experiment

Super Kamiokande

ND280

J-PARC,Tokai

Kamioka

•Goal: Study of neutrino oscillationGoal: Study of neutrino oscillation•J-PARC: 50GeV synchrotron (under construction)J-PARC: 50GeV synchrotron (under construction)•ND280m: Near detector at 280m from the neutrino production targetND280m: Near detector at 280m from the neutrino production target

Time schedule: Q3 2009Time schedule: Q3 2009


The T2K TPCsThe T2K TPCs

359 mm

342

mm

1726 active pads

Bulk MicromegasBulk Micromegas

12 detector modules per TPC plane

=> 72 modules

=> 124.272 pads !!

Design of a novel compact readout electronicsDesign of a novel compact readout electronics

2.5m

2.5m

1m


Initial Requirements & Constraints Initial Requirements & Constraints

• Store and digitize the detector signal over a 511 sample time window larger than the drift time over 12bits.

• Must be versatile to be usable with various end-plate detectors and gas (not defined at the beginning of the design Q1 2005):

• compatible with both polarities of signal, programmable gain

• Sampling frequency adjustable (1MHz-50MHz)

• Short time development (2 years for the all electronics)

=> architecture with limited risks and use of mature technologies.

• Minimum power consumption (detector inside magnet).

• Minimize the cabling between detectors and acquisition.

• Low cost

• But, fortunately:

• Low Event rate: beam rate ~0.3Hz; cosmic ~ 20Hz.

• External trigger available.


A Highly multiplexed architecture to reduce the power consumption taking benefit of the low event

rate

Read-out Electronic ArchitectureRead-out Electronic Architecture

Architecture principlesArchitecture principles• AFTER ASIC : 72 channels; Signal amplified & stored in the SCA (511 cells)

• External trigger: digitization of the totality of the SCA of all the channels (2ms)

• ADC + digital buffer mounted close to the detector

• Multiple optical fibers send data to off-detector concentrators

• Interface to common DAQ via standard network

Pre-amp and shapers

Samplers and multiplexers

Analog to digital conversion

Digital buffer

Data concentration

~124.000 channels

1728 AFTERs

On-detector electronics

72 Optical fibers

1-6 Tbaud*/s peak*1 baud = 10 bit

~2 ms retention max.

34 Gbaud/s peak

400 Gbit/s peak

~1-10 Gbit/s averaged

Shared DAQ system~0.1-1 Gbit/sStandard LAN connection(s)

432

FE

C

6 Concentrator Cards

72 Mezzanine cards

432 ADCs


3 TPC

1 m

2,5

m

2,5 m

1 of 6 TPC planes(12-modules)

Outside magnetInside magnet

1 of 6 DataConcentrator

Card

12 duplexOptical fibres

x 6

TCP/IP

PC Linux

6 DCCs

VME/PCIbackplane bus

GigabitEthernet

DAQ control

DetectorB

DetectorA

Global trigger

Réseau

1 of 72 modules

Front End MezzanineCard (FEM)

288 channelFront End Card (FEC)

1728 pad Micromegas plane

Slow controlnetwork

Optical fiberto/from DCC

Low voltagePower supply

1 of 1728 Front-End ASIC “AFTER”

72 channel x 511 time bucketsSwitched capacitor array

Read-out Electronic ArchitectureRead-out Electronic Architecture


Assume that …

•50cm diameter•0.25 cm²/pad•8000 pads 10,000 pads•AFTER 72 Channels/ASIC•160 AFTER chips•36 FEC•6 FEM•1 Optic Concentrator

50 cm

Card (FEM)

288 channelFront End Card (FEC)

1728 pad Micromegas plane

Optical fiberto/from DCC


Then …

•An event of two traces will give us– 300 fired pads– 300x511x2 bytes = 306Kbytes =

•Assume 1,000 events/sec– 306 Mbyte/sec– Need 1GHz through-put

•Am not sure we can afford the 1k events/sec

•Rise –Time difficulty•Placing the AFTER layout

– Dead-time is common for the full AFTER chip


AFTER Main FeaturesAFTER Main Features

Main features:Main features:•Input Polarity:Input Polarity: positive positive oror negative negative•7272 Analog Channels Analog Channels•44 Gains: 120fC, 240fC, 360fC & 600fC Gains: 120fC, 240fC, 360fC & 600fC •1616 Peaking Time values: (100ns to 2µs) Peaking Time values: (100ns to 2µs)•511 analog memory cells / Channel:511 analog memory cells / Channel:

Fwrite: 1MHz-Fwrite: 1MHz- 50 MHz; Fread: 20MHz50 MHz; Fread: 20MHz

AFTER

511 cells

SCA

FILTERPA

76 to 1 BUFFER

SCA MANAGERSLOW CONTROL

Serial Interface

W / R

Mode

CK

CK

ADC

TEST

In Test

Asic Spy Mode

CSA;CR;SCAin (N°1)

PowerOn

Reset

•Slow ControlSlow Control•Power on resetPower on reset•Test mode: Test mode:

calibration or testcalibration or test [channel/channel] [channel/channel]

functionalfunctional [72 channels in one step] [72 channels in one step]•Spy mode on channel 1: Spy mode on channel 1:

CSA, CR or filter outCSA, CR or filter out

No zero suppress. No auto triggering. No selective readout.


AFTER Main FeaturesAFTER Main Features

Main features:Main features:•Input Polarity:Input Polarity: positive positive oror negative negative•7272 Analog Channels Analog Channels•44 Gains: 120fC, 240fC, 360fC & 600fC Gains: 120fC, 240fC, 360fC & 600fC •1616 Peaking Time values: ( Peaking Time values: (5050/100ns to 2µs)/100ns to 2µs)•511 analog memory cells / Channel:511 analog memory cells / Channel:

Fwrite: 1MHz-Fwrite: 1MHz-100100MHz; Fread: 20MHzMHz; Fread: 20MHz

AFTER

511 cells

SCA

FILTERPA

BUFFER

SCA MANAGERSLOW CONTROL

Serial Interface

W / R

Mode

CK

CK

ADC

TEST

In Test

Asic Spy Mode

CSA;CR;SCAin (N°1)

PowerOn

Reset

•Slow ControlSlow Control•Power on resetPower on reset•Test mode: Test mode:

calibration or testcalibration or test [channel/channel] [channel/channel]

functionalfunctional [72 channels in one step] [72 channels in one step]•Spy mode on channel 1: Spy mode on channel 1:

CSA, CR or filter outCSA, CR or filter out

No zero suppress. No auto triggering. No selective readout.

ADC


Possible Changes

•Pre-amp also outside

•Slow controlled Shaper

•Disc

•Trigger (Sum of Disc)

– Slow controlled

•Selective read-out via FPGA

•Selective trigger via FPGA

•Increase in gain by x2 possible

•Increase of an ADC at 20 MHz read-out


Layout & packageLayout & package•Technology:Technology: AMS CMOS 0.35µm AMS CMOS 0.35µm•Area:Area: 7.8 x 7.4 mm 7.8 x 7.4 mm22

•Package:Package: LQFP 160 LQFP 160 (28x28x1.4 mm)•Run:Run: April 2006 April 2006•Delivery:Delivery: August 2006 August 2006•Test:Test: Start in October 2006 Start in October 2006

SCA :76 x 511 Cells


AFTERAFTER Test set-up Test set-upLABVIEW Test Software

Inte

rfa

ce c

ard

Evaluation kit (Memec) Xilinx Virtex 2 pro

Protection 1 Protection 2 No Protection

ASIC Test Socket

Protection1: Protection1: diodes + PhotoMOSProtection2: Protection2: diodes

Font-end ASIC Test Card


Pulse ShapePulse Shape

RangeRange Tpeak (5% -100%)Tpeak (5% -100%) Tpeak (100% -5%)Tpeak (100% -5%) FWHMFWHM

100ns 111ns 182ns 150ns

200ns 185ns 552ns 287ns

400ns 387ns 823ns 631ns

1µs 893ns 2118ns 1529ns

2µs 1776ns 4037ns 2953ns

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 1000 2000 3000 4000 5000 6000 7000 8000

Time (ns)

Am

pli

tud

e100ns

200ns

400ns

1µs

2µs

)/sin(... / 3/3 tfit teAt

FWHM


Charge Charge GainGain

Charge Range 120fC 240fC 360fC 600fC

Gain 18mV/fC 9.7mV/fC 6.7mV/fC 4.1mV/fC

Spread (ASIC) 5.6% 4% 3.8% 3.4%

Spread (50 ASICs) 12% 8% 7% 6.5%


LinearityLinearity

Specification:Specification: 1% [0-3MIPS]; 5% [3-10MIPS]

Measured INL < 1.2% Full range< 1.2% Full range

-1.2

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000 13000 14000 15000

DAC bin

Inte

gra

l N

on

_Lin

eari

ty =

(d

ata

- f

it)/

fitm

ax

(%) 100ns

2µs

Range: 120fC; FCKW=50MHz

At 100MHz, the INL is the same

Large speed margin of the system !!Large speed margin of the system !!

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000 13000 14000 15000

DAC bin

Inte

gra

l N

on

_Lin

eari

ty =

(d

ata

- f

it)/

fitm

ax

(%) 50M

100M

Range: 120fC; FCKW=100MHz

Peaking Time: 100ns


0

50

100

150

200

250

300

120

140

160

180

200

220

240

260

280

300

320

340

360

380

400

420

440

460

480

500

Baseline (ADC bin)

Nu

mb

er o

f C

han

nel

s

Baseline of 50 Asics x 76 channels Spread: 360 ADC bin peak-peak

Baseline of 1 Asic x 76 channels Spread: 160 to 300 ADC bin peak-peak

The mean value is controlled on the FEC card. It will be fixed to the same value on all the TPC FEC cards

PedestalsPedestals


300

800

1300

1800

2300

2800

3300

0 20 40 60 80 100 120

Cin (pF)

EN

C (

e- r

ms)

116ns

200ns

500ns

1054ns

1400ns

1912ns

Equivalent Noise Charge on ASICEquivalent Noise Charge on ASIC

Icsa : 400µA

measured (dots) and parameterized (lines) for the 120fC range

300

800

1300

1800

2300

2800

0 20 40 60 80 100 120

Cin (pF)

EN

C (

e-

rms

)

116ns

200ns

500ns

1054ns

1400ns

1912ns

Icsa : 800µA

222

120.

22_22

02

20

22 .)(

)()(CSA

CSA

ndstagesnpin

p

inPOLcsaAFTER Range

GchainF

vtCC

tCCI

ENC

222

120.

22_22

02

20

22 .)(

)()(CSA

CSA

ndstagesnpin

p

inPOLcsaAFTER Range

GchainF

vtCC

tCCI

ENC

Noise equation for AFTER

The current of CSA input transistor is controlled on the FEC


Input Protection CircuitInput Protection Circuit

PhotoMOSPhotoMOS

Other pads

100MΩ

1V

220pF

PAD In ASIC

Need to protect the electronic against sparkNeed to protect the electronic against spark•Input Protection diode in ASIC, but robustness ??Input Protection diode in ASIC, but robustness ??=> Input Protection diode on the FEC=> Input Protection diode on the FEC

Need to protect the electronic against sparkNeed to protect the electronic against spark•Input Protection diode in ASIC, but robustness ??Input Protection diode in ASIC, but robustness ??=> Input Protection diode on the FEC=> Input Protection diode on the FEC

The TPC must work without distortion of the electric field even The TPC must work without distortion of the electric field even in case of problem on a Micomegas modulein case of problem on a Micomegas module

•No access to the module inside the magnet during data No access to the module inside the magnet during data takingtaking

PhotoMos to disconnect the pad from the groundPhotoMos to disconnect the pad from the ground[1 PhotoMos for 2*72 channels][1 PhotoMos for 2*72 channels]

The TPC must work without distortion of the electric field even The TPC must work without distortion of the electric field even in case of problem on a Micomegas modulein case of problem on a Micomegas module

•No access to the module inside the magnet during data No access to the module inside the magnet during data takingtaking

PhotoMos to disconnect the pad from the groundPhotoMos to disconnect the pad from the ground[1 PhotoMos for 2*72 channels][1 PhotoMos for 2*72 channels]

1 10 19 28 37 461

8

15

22

29

36

7

8

9

10

11

12

13

14

15

16

17

18

PA

D c

apac

itan

ce (

pF

)

Y axis

X axis

17-18

16-17

15-16

14-15

13-14

12-13

11-12

10-11

9-10

8-9

7-8

Pad capacitancePad capacitance

Measurements on module MM1_005Measurements on module MM1_005

7 to 17pF7 to 17pF

Measurements on module MM1_005Measurements on module MM1_005

7 to 17pF7 to 17pF


Equivalent Noise Charge on TPC moduleEquivalent Noise Charge on TPC module

Range: 120fC

Target value: ENC <750 e -

Range:120fC

400

450

500

550

600

650

700

750

800

850

900

950

1000

1050

100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

Peaking Time (ns)

NO

ISE

(e

-)

ASIC(Cin=0pF)

FEC

FEC + 22pF

T2K: 200ns or 400ns


Range: 240fC



Range:240fC

600

700

800

900

1000

1100

1200

100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

Peaking Time (ns)

NO

ISE

(e

-)

ASIC (Cin=0pF)FEC FEC + 22pF



Range: 360fC


Range:360fC

900

1000

1100

1200

1300

1400

100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

Peaking Time (ns)

NO

ISE

(e

-)

ASIC (Cin=0pF)

FEC

FEC+22pF



Range: 600fC


Range:600fC

1550

1600

1650

1700

1750

1800

1850

1900

1950

100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

Peaking Time (ns)

NO

ISE

(e

-)

ASIC (Cin=0pF)FECFEC+22pF


ASIC Cross-talkASIC Cross-talk•Asic connected to the MM03;Calibration mode Asic connected to the MM03;Calibration mode •High signal on ch 18; Range: 120fC; TPeak =100ns High signal on ch 18; Range: 120fC; TPeak =100ns

Av

era

ge

ou

tpu

t C

h 1

8

Ch 16

Ch 17

Ch 19

Ch 20

Ped

esta

l &

FP

N s

ub

tra

cted

Th

e cr

os

stal

k is

ma

inly

T

he

cro

sst

alk

is m

ain

ly

der

iva

tive

der

iva

tive

Rel

ati

ve

Cro

ss-

talk

am

pli

tud

eR

ela

tiv

e C

ros

s-ta

lk a

mp

litu

de

(Am

pli

tud

es n

orm

ali

zed

by

the

18)

(Am

pli

tud

es n

orm

ali

zed

by

the

18)

18

< +/- < +/- 0.4%0.4%

< +/- < +/- 0.4%0.4%

Cross-talk is proportional Cross-talk is proportional

to the distance / ch 18to the distance / ch 18


SCA leakage CurrentSCA leakage Current

Reading Phase:Reading Phase: 2ms 2ms

High leakage current can degrade the signal/noise ratioHigh leakage current can degrade the signal/noise ratio

Reading Phase:Reading Phase: 2ms 2ms

High leakage current can degrade the signal/noise ratioHigh leakage current can degrade the signal/noise ratio

0

1000

2000

3000

4000

5000

6000

7000

8000

9000

Nu

mb

er

of

SC

A m

emo

ry c

ells

-0.05 0.05 0.15 0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95ADC bin

Amplitude variation for 2ms of memory Amplitude variation for 2ms of memory timetime

1 (a

sic)

x 7

6 (c

han

nel

s) x

511

(m

emo

ry

1 (a

sic)

x 7

6 (c

han

nel

s) x

511

(m

emo

ry

cells

)ce

lls)

< 1 ADC bin 97% < 0.5 ADC bin


Power & YieldPower & Yield

Yield on a total number of 198 Asics:Yield on a total number of 198 Asics: 73%73% Yield on a total number of 198 Asics:Yield on a total number of 198 Asics: 73%73%

The main current sources are controlled on the FEC cardThe main current sources are controlled on the FEC card

•Icsa = 400µA; 1.88mA & 6.25mW per channel (135.5mA & 447mW per ASIC)Icsa = 400µA; 1.88mA & 6.25mW per channel (135.5mA & 447mW per ASIC)


The main current sources are controlled on the FEC cardThe main current sources are controlled on the FEC card



Example of bad chipExample of bad chipExample of bad chipExample of bad chip


Status of electronicStatus of electronic

Present Status FECPresent Status FEC

•7 boards produced and tested7 boards produced and tested

•Foresee PRR in ~Q1-2008; production in ~Q2-Q3 2008 Foresee PRR in ~Q1-2008; production in ~Q2-Q3 2008

Present Status FECPresent Status FEC

•7 boards produced and tested7 boards produced and tested

•Foresee PRR in ~Q1-2008; production in ~Q2-Q3 2008 Foresee PRR in ~Q1-2008; production in ~Q2-Q3 2008

Present Status FEMPresent Status FEM

•1 board produced and tested1 board produced and tested

•Foresee PRR in ~Q2-2008 Foresee PRR in ~Q2-2008

& Production in ~Q3-Q4 2008 & Production in ~Q3-Q4 2008

Present Status FEMPresent Status FEM

•1 board produced and tested1 board produced and tested

•Foresee PRR in ~Q2-2008 Foresee PRR in ~Q2-2008

& Production in ~Q3-Q4 2008 & Production in ~Q3-Q4 2008

Present Status AFTERPresent Status AFTER

•200 ASICs tested200 ASICs tested

•Foresee PRR in 12 October 2007; production in ~Q4-2007Foresee PRR in 12 October 2007; production in ~Q4-2007

Present Status AFTERPresent Status AFTER

•200 ASICs tested200 ASICs tested

•Foresee PRR in 12 October 2007; production in ~Q4-2007Foresee PRR in 12 October 2007; production in ~Q4-2007


Present Status of TPC modulePresent Status of TPC moduleMicromegas Module + 1 FEC tested at Lab with Micromegas Module + 1 FEC tested at Lab with 5555Fe source Fe source Micromegas Module + 1 FEC tested at Lab with Micromegas Module + 1 FEC tested at Lab with 5555Fe source Fe source

Emesh = 350 V

Edrift = 200 V/cm

~8% energy resolution @ 5.9 keVAr(95%)/iC4H10(2%)/CF4(3%)


Present Status of TPC modulePresent Status of TPC module

1 complete Module will be tested at the end of September in the HARP cage for cosmic tests1 complete Module will be tested at the end of September in the HARP cage for cosmic tests1 complete Module will be tested at the end of September in the HARP cage for cosmic tests1 complete Module will be tested at the end of September in the HARP cage for cosmic tests

6 FECs

1 MicromegasDetector 1 FEM

Power Supply(PC ATX)

1 reducedDCC

20-30 mOptical fibre

Linux PC

Power Supply(PC ATX)

Ethernet #1

Ethernet #2(DAQ)

RS232(Console)

CERN LAN

NIM->LVTTLTrigger

HARP flange


AFTER upgrade for nuclear projects: AFTER upgrade for nuclear projects:

selective readout; threshold/channel & auto triggeringselective readout; threshold/channel & auto triggering

The next week, the complete TPC module will be tested with cosmicsThe next week, the complete TPC module will be tested with cosmics

The Tests prove the full functionality of the electronicThe Tests prove the full functionality of the electronic

Compact readout electronic for large TPCCompact readout electronic for large TPC

ConclusionConclusion

[email protected] pattern gas detectors. towards an r&d collaboration cern, 10 september...

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