part ii: recent advances on oversampled analog-to-...

- 1 -J. Silva-Martinez

TAMU-ECE MWCAS-2012

Jose Silva-MartinezAmesp02.tamu.edu/~jsilva

[email protected]

Department of ECE

Texas A&M University

Part II: Recent advances on Oversampled Analog-to-

Digital Converters


TAMU-ECE MWCAS-2012

State of the Art

Fundamentals of Sigma-Delta Modulators Noise and Signal Transfer Function

Error Function

Blockers tolerance

System Limitations Stability

Clock Jitter

DAC issues

Global Tuning

Cases of Study Sigma-Delta Modulator using TDC Techniques

Sigma-Delta Modulator employing Multi-phase approach

Methodologies to improve ADC resolution

Conclusions

Recommended readings

Outline


TAMU-ECE MWCAS-2012

Introduction: ConnectivityWLAN

UWB, 802.15.3a

Connectivity to

EVERYTHING

PAN, 802.15

GPS

WI-FIMAN

Wi-Max,

802.16a,e

BLUETOOTH

Increasing number of wireless standards

Support of multiple-standards on the same chip

Advances in Integrated RF design towards universal devices

Software Radio: easy addition of new standards


TAMU-ECE MWCAS-2012

Direct Conversion Multi-Standard Receiver

System issues in broadband systems:High frequency filtering is especially critical in broadband applicationsRejection of Blockers: ADC filtering must be complemented by LP filteringNeighbor channels are quite relevant even if heavy filtering is used

Trade-offs:Light filtering in front demands an ADC with higher SNR and higher SDRHigher SNDR-ADC implies more power and more circuit complexity


TAMU-ECE MWCAS-2012

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

10 20 30 40 50 60 70 80 90 100 110 120

ISSCC 2010

ISSCC 1997-2009

VLSI 1997-2009

FOM=100fJ/conv-step

FOM=10fJ/conv-step

B. Murmann, http://www.stanford.edu/~murmann/adcsurvey.html.SNDR (dB)

State of the art

Video

100mW @10MHz

10mW @10MHz

Po

we

r/fs

(pJo

ule

s)

Challenge 1: Jitter Tolerance


TAMU-ECE MWCAS-2012

Challenge 2: Co-existenceSimultaneous Usage of Radio Bands

RF Interference: Frequency Overlap, Out-of-Band Emissions, Receiver Saturation

RF Interference from Frequency Overlap, Out-of-Band Emissions and Receiver Saturation

-9

0

30

20

Output Power (dBm)

24

33

16

3.1 3.3 4.9 5.1 5.2 5.3 5.47 5.7 5.8

Frequency (GHz)

3.8

WiMAX

802.16e

. . .

Y-Axis

...

UWB

0.8 0.9 2.7

GPS

WWAN

WCDMA

1.58 1.60 1.8 1.9 2.2

WLAN

802.11b/g

2.3 2.4 2.48

WWAN

GPRS/EDGE

0.4 0.7

UHF

WLAN

802.11a

Bluetooth

WiMAX

802.16e

WiMAX

802.16e

WLAN

802.11a

E

u

r

o

p

e

J

a

p

a

n

* Plot courtesy of Camille Chen/IntelFrequency (GHz)

Ou

tpu

tP

ow

er

(dB

m)


TAMU-ECE MWCAS-2012

1

2

3

LNA

RF Filter

RF

Anti-

Aliasing

Filter

A/D

SCF, Gm

C

OP-RC

Anti-

Aliasing

Filter

A/D

Dig. Filter

DSP

DSPRF

RF Filter

RF Filter

A/D

Dig. Filter

DSPG

Dig. Mod.RF

IF or BB

DR

DR

BB

How much RF processing should be done before the ADC? The front-end must be scalable and configurable to fit multiple standards. Better performance at higher frequency.

Roadmap for high-resolution Receivers: ParadigmSlide courtesy of Prof. Yun Chiu


TAMU-ECE MWCAS-2012

Impact of SNDR on ADC Power Consumption

♦ For 4MHz BW a 10dB increase in DR leads to ADC power increment of

50mW at 70dB or 1W at 90dB

♦ Required: Systematic evaluation of filter-ADC interdependence for broadband receivers

A

B

Slope is around:

x10 in Power/12.5 dB in SNDR

x10 in Power/2 bits in SNDR


TAMU-ECE MWCAS-2012

Conventional (Nyquist) ADC

A/D

Data

Out

Vin

SQNR=6.02*n+1.76


TAMU-ECE MWCAS-2012

Basic concepts in SD Modulators

)s(H

)s(HSTF

1 )s(HNTF

1

1

DAC

Vin

ss

FT

1

S H(s) A/D

Data

Out

Vin

Quantization

Noise

Feedback

DAC

H(s) A/DDout

VDAC

NTF =Dout

Qn

STF =Dout

Vin

ff0

0 dB

ff0

OBG


TAMU-ECE MWCAS-2012

Fundamentals of Oversampled A/D Conversion

22

22

11

2

2221

TsinzH

TsinjezH

eeeeZzH

e

Tj

e

Tj

Tj

Tj

Tj

e

Check the input-output trajectoriesOriginal E(z) is shaped by NTF

Original E(z) is amplified here!

2

2

21

22

1

Tsin

*zE

zXSQNR

zHzE

ZzXSQNR

e

Spot SQNR

+ +1

1

1

Z

Z+

-

qE

ZY ZX

DAC

Filter


TAMU-ECE MWCAS-2012

Oversampled A/D Conversion

Signal to Quantization

Noise Ratio (SQNR)

N=number of bits

OSR=fs/2fb

SQNR improves by 30dB when

OSR increases by 10

Or 9dB SQNR improvement

when doubling OSR

D

D

2

32

2

3

2

2

0

2

2

0

2

2

0

2

21

31251

26

2

12

2

12

2

1

22

1

OSR***.SQNR

f*

f

f*

*

f*

V

V

SQNR

then,fsfbIf

dfT

sin

*zE

zXSQNR

dfzHzE

zX

dfzHzE

ZzXSQNR

N

S

b

S

S

q

q

N

f

f

e

f

e

b

bb

dBOSRlog*.N*..SQNR

OSR***.SQNR N

10

2

32

3025026761

31251

+ +1

1

1

Z

Z+

-

qE

ZY ZX

DAC

Filter


TAMU-ECE MWCAS-2012

System Design Considerations

0

25

50

75

100

125

150

0 10 20 30 40

Sig

na

l to

Qu

an

tiza

tio

n N

ois

e R

ati

o (d

B)

Oversampling Ratio (OSR)

Filter order=2Quantizer Bits=1




Dashed lines are for 2-bit quantizerDashed=Solid+6.02


TAMU-ECE MWCAS-2012

4

6

8

10

12

14

16

18

20

4 8 12 16 20 24 28 32 36 40

Eff

ec

tive

Nu

mb

er

of

Bit

s (

EN

OB

)

Oversampling Ratio (OSR)

Design Considerations: 3rd order loop

4-bit quantizer

2-bit Quantizer

3-bit quantizer

1-bit Quantizer

3rd order loop

02.6

76.1)dB(SNDRENOB


TAMU-ECE MWCAS-2012

STF and NTF are definitely not enough to design a robust system; a1*a2=1; b=2

At the input of the first amplifier we have:

Linearized Model to Analyze SD Modulators: 2nd

order Multiple Feedback

Schreier and Temes

zEazzzUazzz

azzVzU

zEzzUzzVzU

zEzzUzzV

q

q

q

1

11

1

11

1

1

1

212

212

111

11

1

If a1>0.5, hence the in-band output of the 1st integrator is > than the input !

At the output of the first integrator we have (saturation?)

Small for inband signals but what about the blockers?

+ +1

1

1

1

Z

Za+

-

qE

ZY ZU

DAC

1

1

2

1

Z

Za+

+

-

ZV

b


TAMU-ECE MWCAS-2012

Sigma-Delta Modulators:

Practical Design Issues


TAMU-ECE MWCAS-2012

Eq stands for the quantization noise

Ed stands for DAC non-idealities (jitter + thermal noise)

Filter’s thermal noise is accounted in Eh

The modulator’s output becomes

The error signal (Filter’s input) is

Oversampled A/D ConversionFeedforward Architecture

qhd E*NTFEEX*STFY

1

1

1

1

1

Z*sZOH*sH

NTF

Z*sZOH*sH

sZOH*sHSTF

H(s) ZOH

Z-1

X Ve Vy Y

Ef

Eq

S

Ed

SS

Eh


TAMU-ECE MWCAS-2012

ZOH parameters are defined as

The lowpass transfer function H(s) provides large loop gain (Noise shaping)

DC gain >>0 dB

Enough phase margin at 0 dB gain

Z is a complex number (phase)

Loop stability is fundamental

Stability Issues: 2nd Order System

2

S

Tj

TcsinzZOH

eZ S

H(s) ZOH

Z-1

X Ve Vy Y

Ef

Eq

S

Ed

SS

Eh

1

1

1

1

1

Z*sZOH*sH

NTF

Z*sZOH*sH

sZOH*sHSTF

Magnitude of loop transfer function


TAMU-ECE MWCAS-2012

-30

-25

-20

-15

-10

-5

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Notice that

Oversampled A/D Conversion: Effects of ZOH

S

Tj

TzPhase

eZ S

1

H(s) ZOH

Z-1

X Ve Vy Y

Ef

Eq

S

Ed

SS

Eh

-30

-25

-20

-15

-10

-5

0

0.1 1

S

S

S

f

f

f

fsin

f

fcsin

Sf

f

Sf

fcsinfZOH

dB

1 dB

4 dB

20 dB


TAMU-ECE MWCAS-2012

L(f) is defined as the loop gain

Phase of L(f) is quite important for stability

Z is quite relevant for phase of L(f)

Oversampled A/D Conversion: Stability Issues

fLNTF

fL

Z*fLSTF

1

11

1

2

Z*zZOH*zH)f(L

Tcsin*TzZOH

Tsin*jTcoseZ

SS

SS

Tj S

H(s) ZOH

Z-1

X Ve Vy Y

Ef

Eq

S

Ed

SS

Eh


TAMU-ECE MWCAS-2012

Check the phase contribution of the filter and the delay element!

Check the phase of the loopat the unity gain frequency!

Can’t stabilize the loop employing the conventional filter design approach

Additional parasitic poles!

fLNTF

fL

Z*fLSTF

1

1

1

ADC

Freq0

L(f) H(f)

Fs

Sf

f2

fH

2

2

3

Stability Issues: SD Modulators


TAMU-ECE MWCAS-2012

Stability Issues: SD Modulators

Not very difficult to stabilize the loop if the unity gain frequency is below Fs/4! (not very Low OSR); e.g. around 100Mhz if clock frequency is 400MHz

Notice that larger OSR allow you to reduce the filter gain at high-frequency

Out-of-Band noise is distributed in wider bandwidth, hence smaller noise density but same integrated noise

ADC

Freq

0

L(f)

Sf

f2

fH

2

2

3

H(f) fS0.5fS

Loop

Phase

Hard to implement H(s)

Split the filter in 2 parts

Loop filter and fast path


TAMU-ECE MWCAS-2012

Remarks on Filter’s operation: Filter’s input signal

Effect of the blockers on loop operation

Inband signal is usually very small: Nice property

Transition band is more critical for filter’s linearity (neighbor channels);

Filter must be designed for the blockers

Blocker tolerance is a major issue in broadband applications (LTE)

sL

E*ZEEXV

qhd

e

1

1

H(s) ZOH

Z-1

X Ve Vy Y

Ef

Eq

S

Ed

SS

Eh

Fs Freq

InbandTransition

bandOut of

bandVe(f)

ADC

0 dB

H(f)

ZOH(f)

FsNTF Freq

1/(1+L)

X(f)


TAMU-ECE MWCAS-2012

Typical Quantizer: Flash Architecture S/H operates at clock rate

Huge input capacitance if N>6

Kick back noise

Requires a precise low-

impedance resistive ladder:

Power-accuracy-Speed

tradeoff

Limited by comparator

Speed and accuracy

Offset voltage

Hard to improve its resolution

State of the art: ~ >2.4 GS/s 6 bits resolution

Digital

Signal

Processor

and

MemoryTh

erm

om

etr

ic

to B

ina

ry

+Vref

-Vref

R/2

R/2

R

R

Vin

+

-

+

-

+

-

+

-

clock

Dig

ita

l d

ata


TAMU-ECE MWCAS-2012

Kick-back noise and coupling capacitors

Preamp delay is signal-dependent (Metastability)

Power of the latch could excessive during the resetting phase (M9-ON)

A major challenge: distributing clock signals across 2N-1 comparators

with minimum clock skew (routing, PVT effects)

Input capacitance could be excessive for multi-bit applications

M1 M2

Vi+

M5 M6

M9

Φ

Vo+

Vo-

Fully-diff. PA Latch

M3 M4

Vi-

VR+

VR-

M7 M8Φ


TAMU-ECE MWCAS-2012

Excess loop delay : Constant delay between ideal and implemented DAC

feedback pulse

Decision time required by quantizer affecting latches used for

synchronizing DAC inputs

Finite response time of DAC to its clock and inputs

Filter’s delay is sensitive to PV variations

Excess Loop Delay can be incorporated into: Z-1Z-1-D

Inter-symbol interference : Finite slew rate of DAC outputs with unequal

rise and fall times

Additional noise and tones fold into baseband

Clock jitter in DAC

DAC and Filter Non-linearity

ADC Non-idealities

Processed by STF

Not noise-shaped


TAMU-ECE MWCAS-2012

Remarks on DAC non-idealities. Same analysis apply to the input referred filter’s noise

Oversampled A/D Conversion

dDAC E*STFY

11

Z*sZOH*sH

sZOH*sHSTF

DAC non-idealities are reflected at the ADC output similarly to the signal

Baseband noise can be directly mapped to ADC input (Ed and Eh)

Non-linearities in DAC that translate HF noise into baseband affects directly SQNR

DAC is a critical component

H(s) ZOH

Z-1

X Ve Vy Y

Ef

Eq

S

Ed

SS

Eh


TAMU-ECE MWCAS-2012

Binary-Weighted Current Steering DAC

Current switching is simple and fast.

INL and DNL depend on matching, not inherently monotonic.

Thermometric arrays usually lead to better INL figures

Large component spread (2N-1:1)

VX

Vo

b3 b2 b1 b0 A

I/2 I/4 I/8 I/16

R

N

1jj

j-N

o2

bIV


TAMU-ECE MWCAS-2012

This is a major research area in multi-bit sigma-delta modulators. Several alternatives have been reported; main trends are:

Randomize the errors such that the non-linear errors are converted in noise instead of tones that degrades SNDR Dynamic element matching techniques

Pseudo Randomizers such as Rotators

Digital signal processors

Drawbacks?

Calibration Usage of large overdrive voltages and large dimensions

Pre-calibration of current cells

Other options?

DAC Calibration (Signal-to-Distortion Ratio)


TAMU-ECE MWCAS-2012

Dynamic Element Matching: Simpified scheme

Representing DAC input using a thermometer DAC

I1

I2

I3

I4

I5

I6

I7

I8

I1

I2

I3

I4

I5

I6

I7

I8

I1

I2

I3

I4

I5

I6

I7

I8

I1

I2

I3

I4

I5

I6

I7

I8

Data -out= 1

I1

I2

I3

I4

I5

I6

I7

I8

I1

I2

I3

I4

I5

I6

I7

I8

I1

I2

I3

I4

I5

I6

I7

I8

I1

I2

I3

I4

I5

I6

I7

I8

Data-out= 3

Data-Out= 1 can be represented by any one of I1-8

Averaging all possible combinations produces the ideal output

Use different combinations to represent a given code

Errors are randomized, and do not generate harmonics but noise

t

0 Ts 2Ts 3Ts

t

0 Ts 2Ts 3Ts


TAMU-ECE MWCAS-2012

Implementation of DEM Scheme

Shifter performs a Rotate-right shift on its inputs

PN-sequence generator indicates number of shifts

DEM is operated at higher frequency to minimize its delay

Routing and extra cells increase the bill of silicon and power

Excessive delay for high frequency applications

Noise level increases


TAMU-ECE MWCAS-2012


TAMU-ECE MWCAS-2012

A reference current source is used At the end of a calibration cycle, CCAL attains the correct VGS

required to generate Iref

Analog Self-Calibration of Current Sources

R. T. Baird and T. S. Fiez, IEEE TCAS-II, December 1995.


TAMU-ECE MWCAS-2012

Analog Current Calibration Realization


TAMU-ECE MWCAS-2012

Simulation Results: DEM increases noise level

100

101

102

103

-140

-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

Po

we

r (d

B)

Output Spectrum

Ideal

1% mismatch

1% mismatch +DEM + Calibration

Mismatch DEM Calibration SNR (dB)

N N N 73.8

Y N N 55

Y Y N 63.6

Y N Y 70

Y Y Y 72.7

We found thatCalibration (Digital Memory) looks better for wideband applications, but..

OFFLINE!


TAMU-ECE MWCAS-2012

Clock Jitter Sensitivity (SJNR)

The main effects of clock jitter is present at the input of the quantizer and DAC.

Jitter induced noise at DAC output is processed according to the STF, which is a serious problem for continuous-time sigma-delta modulators

Clock Jitter in quantizer

is not very relevant:

processed by NTF.

Clock jitter introduce

uncertainty at the DAC

output (jitter induced

noise) processed by STF.

Vin

Loop Filter Quantizer

Dout

VDAC

Jittered

Clock

Re-timed

Data

Multi-Bit

DAC

Flip-Flops

Jittered

Clock


TAMU-ECE MWCAS-2012


TAMU-ECE MWCAS-2012

Jitter Insensitivity of Switched-Capacitor DACs

•So far, SC-DAC is the most jitter tolerant approach•Quite precise and may not require further calibration procedures

• Drawbacks of the SC DAC•Peak current in the SC-DAC can be as high as 5 times IDAC used in the current mode DAC!•Very demanding SR and GBW for the OPAMP: Power consumption; RC discharge is a good trade-off for medium speed architectures!•Class AB OPAMP may help while dealing with this issue

Jitter error


TAMU-ECE MWCAS-2012

Phase Modulation: wide frequency spectrum

Phase Modulation:

Then

Typical phase noise measured in the spectrum analyzer

RMS value of total jitter

22

2

n

no

T

T

tcos

D

dffT

JRMS nper

2

2

0

2

2

dffLT

JRMS per

L (in dBc)

1010

dBcL

fL

Clock Jitter Sensitivity (SJNR)


TAMU-ECE MWCAS-2012

The DAC error due to clock jitter:

In the frequency domain: Differential of Dout convolves with Jn()

In-band signal is shaped by , then it is not very criticalOut-of-Band quantization noise and blockers convolve with the clock jitter

T

tTnDnDnE outoutj

D1

Jitter Issues: High Clock Frequency

noutS

noutj JDT

sinJDZE2

21 1

11 Z

Error Function

Vin

Loop Filter

Quantizer

Dout

VDAC

Jittered

Clock

Re-timed

Data

Multi-Bit

DAC

Flip-Flops

Jittered

Clock


TAMU-ECE MWCAS-2012

ZJZV*NTFZ

ZJZV*STFZ)Z(E

Therefore

ZJZVZNTFZV*ZSTFZ)Z(E

Or

ZJZVZ)Z(E

thenT

ntnVnV)n(e

q

inj

qinj

outj

outoutj

1

1

1

1

1

1

1

1

1D

dJVNTFZP q

OSR/

Q,j

21

21

012

dEP j

OSR/

S,j

221

02

Quantization noise

Clock NoiseDensity

SJNR is function of the convolution of NTF and J(Z)

Effect of clock jitter and Quantization noise on SNR

2

21 1 sTsinZ

NTF*Vq

Jn

f

f

Jn

fs-fs


TAMU-ECE MWCAS-2012

2

2

1021

10

4

2sinc

101

10

s

j

soin

BW

onQuantizatin

inNRZ

T

T*P*OSR

logdfVZJ

PlogSJNR

Continuous-Time BP-ΣΔ ADC: Jitter effects

In absence of blockers, assuming white jitter spectrum, the jitter induced noise has been usually approximated as:

LPF(s) HoldVin

Data

out

CLK

N-bit

Quantizer

Multi-bit

DAC

S Sampler

Z-1

S

Qn

ffck

+

-

0 fckf00 fckf0

0 fckf0

H(s) HoldVin

Data

out

CLK

N-bit

Quantizer

Multi-bit

DAC

S Sampler

S Z-1

JnX

S

Qn

ffck

+

-

fck

1-Z-1

Quantization

and Jitter

Jitter induced noise

f0

0 fckf00 fckf0

0 fckf0

0 fck

f0

0 fckf0

2sTsinc

sj

j

sin

NRZ

T

TPOSR

dBSJNR

3

6

2

10

10

4

*

60


TAMU-ECE MWCAS-2012

BW

onQuantizatin

BW

kerBlocn

kerBlocno

BW

kerBlocnonQuantizatin

in

dfVZJ

dfVZJ

logSJNR

dfVZJVZJ

PlogSJNR

21

21

10

21

21

10

1

1

110

11

10

Continuous-Time ΣΔ ADC: Jitter & Blockers

High frequency blockers convolve with Jn and are folded back in band.

RF clock filtering is an method to partially overcome this issue!

Considering

Pblocker and

Pquantization

LPF(s) HoldVin

Data

out

CLK

2-bit

Quantizer

Multi-bit

DAC

S Sampler

S Z-1

JnX

S

Qn

ffck

+

-

fck

1-Z-1

Quantization

and Jitter

Jitter induced noise

f0

0 fckf00 fckf0

0 fck

f0

0 fckf0

0 fckf0

0 f0 fck


TAMU-ECE MWCAS-2012

H(s)Vin

D

Multi-bit

ADC

Multi-bit

DAC

DAC

ADCS

S Z-1

Jn

ffck

ffck

Lowpass

Filter

Blocker

Desired

Images

ffck

ffck

ffck

fck

fck

D

DY

Y

Y

a

b

*

*

*

1-Z-1

10-1

100

101

102

-140

-120

-100

-80

-60

-40

-20

0

SNRIdeal

= 71.2dB

SNRJitter

= 67.2dB

Frequency (MHz)

Po

we

r (d

BF

S)

No jitter tone

Jitter tone at 497.43Mhz

Jitter tone around Fsconvolve with images ofinband signal and producein-band noise tones

10-1

100

101

102

-140

-120

-100

-80

-60

-40

-20

0

SNR = 39.3dB

SNR = 71.2dB

Frequency (MHz)

Po

we

r (d

BF

S)

fj =80.26Mhz, f

b =75.27Mhz

Ideal

Jitter and blocker

convolves, producing in-

band noise tones.

Jitter also convolves with

OOB quantization noise

and downconverts into in-

band noise.


TAMU-ECE MWCAS-2012

Another Major Issue: Loop SaturationSignal Bandwidth 20MHz

Oversampling Ratio 10

Order 5

No. of Quantizer levels 9

Peak SQNR 80dB

Max. NTF Gain 10dB

Max. Stable Input Amplitude -3dBFS

BIQUAD1

LP1

BP1

VIN

RIN

NR

Z

DA

C1

BIQUAD2

LP2

BP2

LPF1

LP3

kLP3

kLP2

kBP2

kBP1

Quantizer

_

NR

Z

DA

C2

DAC

Controller

Clock

Generator

VOUT

DAC Control Signals

kLP1

107

108

-60

-50

-40

-30

-20

-10

0

10

20

30

Frequency (Hz)

Ga

in (

dB

)

BP1

LP1

BP2

LP2

105

106

107

108

-60

-40

-20

0

20

Ma

gn

itu

de

(d

B)

Frequency (Hz)

STF FB

STF FF

NTF(z)

Feed-forward and feedback architectures

Internal gain: BP1, BP2 and LP1 are critical nodes


TAMU-ECE MWCAS-2012

“Blocker and Jitter Tolerant Wideband SD Modulators” Silva-

Karşılayan-Geddada, MWCAS-12

BP2

LP1

Quantizer

Z-1

Clock

Generator

YOUT

NR

Z

DA

C1

NR

Z

DA

C2BP1

RIN

VIN

Active-RC

5th

order Filter

LP2

LP3

I DA

C2

I DA

C1

PGA

SATURATION

DETECTORVCONTROL

+

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10-6

0.4

0.5

0.6

0.7

0.8

0.9

Time (sec)

VO

UT

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10-6

0

0.5

1

VIN

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10-6

0

0.5

1

VD

ET

=0.5u sec

10-1

100

101

102

-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

Po

we

r (d

BF

S)

SNR = 75.1dB

10-1

100

101

102

-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

Po

we

r (d

BF

S)

SNR = 46.5dB

Vin = -6dBFS @ 5MHz

No blocker

Vin = -6dBFS @ 5MHz

Blocker = -9dBFS @ 40MHz

Attenuation factor = 12dB

Transient response of the

ADC to the 8.7dBFS blocker

at 100MHz in the presence

of a -6dBFS in-band signal

at 5MHz

Effectiveness of the

saturation detector:

Output spectrum of the

ADC with and without

the -9dBFS blocker at

40Mhz

Stable Operation


TAMU-ECE MWCAS-2012

System-level Optimization

7

8

9

10

11

2.5

3

3.5

472

74

76

78

80

82

84

86

88

90

No. of Quantizer levels

Peak SQNR vs NTFmax

, No. of Quantizer levels

NTFmax

Pe

ak

SQ

NR

(d

B)

Order of modulator (L), and OSR set by target SQNR (~80dB) and

settling time requirements on 1st integrator stage

L = 5, OSR = 10

Order of modulator (L),

and OSR set by target

SQNR (~80dB)

L = 5, OSR = 10

A number of tradeoffs

involved

Just picking

values is not a

good approach

EDUCATED

GUESS!


TAMU-ECE MWCAS-2012


0

2

4

6

8

0

2

4

6

868

70

72

74

76

78

80

82

84

86

Q2 (

0 = 10.8MHz)

Peak SQNR vs Biquad Quality FactorsL = 5, OSR = 10, N = 9

Q1 (

0 = 18.1MHz)

Pe

ak

SQ

NR

(d

B)

Order of modulator

(L), and OSR set by

target SQNR (~80dB)

High-Q filters give

you better SQNR

(due to picking in

the gain; better in-

band noise)

Implications on

filter’s signal

swing and out-

of-band noise?


TAMU-ECE MWCAS-2012


7

8

9

10

11

2.5

3

3.5

4

-5

-4.5

-4

-3.5

-3

-2.5

-2

-1.5

-1

NTFmax

MSA vs NTFmax

, No. of Quantizer levels

No. of Quantizer levels

MS

A (

dB

)

Maximum Signal

Amplitude Increase

with number of levels

and with small NTF

values

Signal at internal

nodes could limited

even more MSA

This is a multi-

dimensional

problem: several

tradeoffs

involved


TAMU-ECE MWCAS-2012

Data

Out

High-Order

LP Filter

ADC

DAC

Input

SignatureAmplitude/Phase

Comparators Filter tuning

schemeFilter tuning

scheme

VinVin

Calibration

Algorithm

cal

op

cal

System Optimization: Tuning Filter Parameters

Calibration of (standalone) building blocks:Does not guarantee loop stability (excess loop delay) Does not guarantee best NTF (Coefficient adjustments)

0 f0

f

Effect of PVT Variations Filter Tuning; reconfiguration orMaster slave techniques could be used


TAMU-ECE MWCAS-2012

System Optimization: Global Tuning Scheme

Linear model used to findNTF

Model used to calibrate NTF

Loop response to calibration tones is analyzed in digital domain

F. Silva-Rivas, et. al., “Digital Based Calibration Technique for Continuous-Time Bandpass Sigma-Delta Analog-to-Digital Converters,” Analog Integrated Circuits and Signal Processing, April-09.

C.Y. Lu, et. al., “A Sixth-Order 200MHz IF Bandpass Sigma-Delta Modulator With over 68dB SNDRin 10MHz Bandwidth,” IEEE J. Solid-State Circuits, June 2010.


TAMU-ECE MWCAS-2012

Global Tuning Scheme for NTF Parameters: Digital

A set of strategic tones are used to optimize:Loop StabilityBest NTFBandwidth

Frequency

Testing tones Output tones

Vin

QnQuantizer

Dout

β

Feedback DAC

ZOH

Zero-Order

Hold

Calibration

Tones

Software

Platform

FFT Transform, Power

Detector and

Calibration Algorithms

Controller: C,

Coefficients and loop

delay

Loop Filter


TAMU-ECE MWCAS-2012

Filter's

control

Software

Platform

DSP

N-channel

digital

receiver

Wideband

Programmable Filter

Dout

Quantizer

NRZ DAC

z-1/2

Programmable

z-1/2

Array of

DACs

Vin

Calibration

ff0

Test Tones

DACs

Control

Calibration

Algorithm

After

DAC & Freq

calibration

Digitally assisted calibration scheme

Freq calibration

Data control

A 6th-Order 200MHz IF Bandpass Sigma-Delta Modulator With over 68dB SNDR in 10MHz Bandwidth, C.Y. Lu, et.al., IEEE J. Solid-State Circuits, June 2010.

TSMC 1P6M 0.18um


TAMU-ECE MWCAS-2012

ADC Calibration: Experimental results


TAMU-ECE MWCAS-2012

Strategy for nanometric technologies

Make use of time domain signal representation

Small supply voltage limits the dynamic range of analog signals

Fast switching gates provide fine time precision, which provide alternate means for high DR signal representation

Also takes advantage of CV2f

0

Vdd

0 Ts

Am

plit

ud

etime timeA

mp

litu

de

Vdd

VQ

TQ

0

2T

s

4T

s

0

2T

s

4T

s

Time domain signal representation

A 20MHz Signal Bandwidth 68dB Dynamic Range Continuous Time DS ADC Based On Multi-bit Time

Domain Quantizer and Feedback Element, V. Dhanasekaran, et.al. ISSCC-2009; JSSC March 2011


TAMU-ECE MWCAS-2012

Proposed ADC Architecture

• Multi-level quantizer and Digital to Analog Converter (DAC) are

replaced by PWM generator and Time to Digtal Converter (TDC)

• Width of p(t) is proportional to the amplitude of the signal in a given

clock period

• Output code (Dout) represents “quantized pulse” edges with a

quantization step size = TQ

Conventional DS Time domain Quantizer-DAC

S+

-

Vin Dout

Multi-bit

DAC

CLK

Multi-bit QuantizerLoop Filter

1-Level

DAC

Loop Filter

Time Quantized PWM

Digital

OutputS

+

-

Vin

TDC &

Digital Logic

CLK

CLK

PWM Generator

Decimation

Filter

THA

P(t)

Dout


TAMU-ECE MWCAS-2012

PWM Generator

PWM signal generated by standard method - comparing signal with triangle waveform

Double-sampled or “asymmetric sampled” PWM is used to minimize distortion and improve OSR

Performance is relaxed due to noise shaping

S+

-

Vin

pq(t)

Loop Filter

CLK

TDC

PWM Gen

Dout

p(t)


TAMU-ECE MWCAS-2012

TDC Functionality

Time-to-Digital Converter

Converts pulse timing information to digital codes (Drout & Dfout)

Drout & Dfout can be used to reconstruct signal in clocked digital domain

Also generates a feedback pulse aligned to the timing edges represented by the dotted lines

0 2 4 6 8 1210 14

TCLK

TQ

TDCDrout

Dfout

(6)

(11)

CLK


TAMU-ECE MWCAS-2012

TDC & Time quantized feedback pulse

Digital output code

CT PWM output p(t) is latched by delayed versions of the clock

Flipflop outputs provide “thermometer” coded pulse width

D input of the flipflops are driven by p(t) to facilitate easy generation of f/b pulse

Feedback pulse - pq(t)

Must match output code

Edges of pq(t) are always aligned to the delayed clock edges

D

D

D

D

CK0

CK1

CK2

CK3

p(t)

D

D

D

D

CK4

CK5

CK6

CK7

p(t)

RST

RST

CK1

CK2

CK3

CK4

CK5

CK6

CK7

CK0

RST

RST

p(t)

TQ

TCLK

62

Binary code

pq(t)


TAMU-ECE MWCAS-2012

Time quantized pulse generator

Pq(t) can be generated using a OR gates and SR latch

Pq(t) turns ‘High’ when the earliest of CK0-3 goes High after p(t) is High

Pq(t) turns ‘Low’ when the earliest of CK4-7 goes High after p(t) is Low

D

D

D

D

CK0

CK1

CK2

CK3

p(t)

D

D

D

D

CK4

CK5

CK6

CK7

p(t)

+

+

S

Rp

q(t)

RST

RST

Thermo-to-Bin

DRout

DFout

Thermo-to-Bin

Wired-NOR/NAND gate can be

used to ensure uniform delay


TAMU-ECE MWCAS-2012

Full TDC Schematics

50 levels of time steps are used in the proposed design for 20MHz ADC

Clock phases are generated using cascade of delay elements that are tuned using a phase detector

D D D D D D D D D D D D D D D

1 2 3 4 5 6 7 8 9 10 46 47 48 49 50

P(t)P(t)

CK1 CK2 CK3 CK4 CK5 CK6 CK7 CK8 CK9 CK10 CK46 CK47 CK48 CK49 CK50

CK4 CK5 CK6 CK7CK3 CK9 CK10 CK11 CK12CK8

D

51

D

52

CK50 CK51 CK52CK48 CK49

CK51 CK52

25 Input OR Gate25 Input OR Gate

CLKIN

S R

Pq(t)


TAMU-ECE MWCAS-2012

Active-RC Topology Loop Filter

The gain of the filter in the signal bandwidth (20MHz) serves to

suppress the quantization noise of the TDC

The filter has a minimum inband gain of 37dB

CH

CB

Rq

R1

R3

C1 C3

RF

R2

C2

V_bp

V_lp

Vin

Vout

_

+

_

+

_

+A1

A2A3

Noise Transfer

Function (NTF))16e279.1s7e414.1s(s

25e223.4s17e312.2s312.7

)s(Vin

)s(Vout)s(H

2

2


TAMU-ECE MWCAS-2012

Mitigating Excess loop delay

KFB provides a ‘fast path’ through INT3 => Make AMP3 a minimum phase structure

PWM

T

D

C

DAC

KFB path

FILTER

Characterstics Amplifier 1-2 Amplifier 3

DC Gain High (>30dB) Moderate-low (20dB)

Gain-Bandwidth Moderate (150-250MHz) High (>500MHz)

Supply Noise Rejection

High (>40dB) Moderate


TAMU-ECE MWCAS-2012

Schematic: Amplifier1 / Amplifier2

Two Stage ‘Typical’ configuration

maximizes gain of the initial stages => Better Q control

Output pole ~ 4*GBW

Overall noise limited by input devices

Rf reduces (degenerate) noise due to NMOS current mirrors

Limitations:

• Parasitic poles result in additional loop delay/excess phase in

the filter (could be > 10 deg at 500MHz)

•Limits loop stability and affects the overall performance

Pbias

VDD

VSS

Vinp

cmbias

M1 M2

M9 M8

M6

Vinm

M3 M4

Pbias

cmbias

Voutm

M7

M5

Voutm

Rf

Cc Rc Rc Cc

Rf


TAMU-ECE MWCAS-2012

Simplified schematic: Amplifier 3

A simple single stage pseudo-differential ‘inverter based’ amplifier

Complementary structure with class A-B action

CM noise (supply etc) is suppressed by biquad gain of 18dB

Limitations:

•Bias point not accurately controlled + % variation across

statistical corner & Temp

•Need for ‘Non-conventional’ common-mode control

Single Ended Schematic of Amp3

VDD

GND

Vinp Vinm Vout


TAMU-ECE MWCAS-2012

Amplifier 3 Common Mode control

Current sources at virtual ground control amplifier’s common

mode

Icm are: small current source, sized to meet transconductance

and noise specifications

CH

R3

CB

R3

C3

C3 Cmref

Icm

Icm

EA

Amp3From

Biquad

CB


TAMU-ECE MWCAS-2012

Chip Micrograph

Folded layout to minimize delay in feedback

Digital approach minimizes area requirement

Occupies 0.15mm2


TAMU-ECE MWCAS-2012

Output Spectrum: -5dB Input

Output spectrum for -5dB 4MHzInput signal

• SNR=62dB

• THD=65dB


TAMU-ECE MWCAS-2012

Dynamic Range and SNDR

DR = 68DB

Peak SNDR=60dB @ -5dB input

Peak THD=67dB @ -6dB input

FoM = 319 fJ/step

Dynamic Range (DR) is defined as the amplitude

range with SNR>0dB


TAMU-ECE MWCAS-2012

tntmCosnmSin

nm

MnmJV

tmCosmSinMmJm

V

tnCosnSinMnJ

n

Vtv

SR

m n

R

S

R

Sn

a

R

m

oa

S

R

Sn

n

R

S

ap

2

22

22

12

22

12

1

1

1

The PWM spectrum consists of tones at

Signal frequency (S) and its odd harmonics,

Reference tones due to the ramp’s fundamental frequency (R) and its harmonics,

Intermodulation products of the signal and the reference tones.


TAMU-ECE MWCAS-2012

Second ADC:System Architecture: Injection Locking

OUT

b1

b2

b4

b5

Σb3

Level-to-PWM

Converter

VCO

3-Bit Two-Step

Quantizer

Vin

Digital

Output

3-Bit NRZ

DAC

1-B

it P

WM

DA

C

BP

LP

2nd

-Order

Filter

Complementary Injection-

Locked Frequency Divider

Φ1

Φ2

Φ3

Φ4

Φ5

Φ6

Φ7

Ts

0

Ts/7

2T

s/7

3T

s/7

4T

s/7

5T

s/7

6T

s/7

+

-

+

-

+

-

RF

RF

RF

RQ

RQ

CC

C C

+-

+-

RF

BP

LP

2nd

-Order

Filter

Rin

Rin

Programmable Delay

4

11

OUTBP

OUTLP

+

-

Rg

C

C

+-

Rg

RC

RC

IN IN

LP

1st

-Order

CILFD

• 5th-order 3-bit feedforward architecture

• Local feedback is to compensate the excess loop delay

• LC-VCO+CILFD are used to generate clean reference clocks

“25MHz Bandwidth (BW) Continuous-Time Lowpass ΣΔ Modulator with Time-Domain3-bit Quantizer and DAC” Cho-Ying Lu, et.al., Sept 2010, JSSC


TAMU-ECE MWCAS-2012

Rq

R

1

C1

RF

R2

C2

V_bp

Vin_

+

_

+A1

A2

-1

RL1 CL1RL2 CL2

gm1 gm2

gmf

in out

V_lp

Two stage amplifier with

feedforward compensation

1st stageVIN+ VIN-

VOUT- VOUT+

VCMFB

VOUT+

VOUT-

VREF

VCMFB

2nd stage

feedforward

stage

CMFB

stage

MN1 MN1

MP1MP1

IB1

MN2 MN2

MN3 MN3

MP2A

MP2B

R1R1

MP4 MP4

MN4 MN4

IB2

IB3

IB4

MP2AMP2B

R2

R2

C2

C2

VIN-VIN+

First stage Second stage

No extra CMFB (current re-use)

needed

Large resistors are used

Feed-forward stage

Biquadratic Filter and Amplifier

Quiescent current ~ 1.0 mA

GBW > 800MHz


TAMU-ECE MWCAS-2012

2IF

MFMF

Feed-Forward Path

2I3

M3M3

Vcmfb

-Vout ++

Vin

-

2IL

MLML

Linearity

Compensation

AV2AV1

VCM

2I1

R1 R1

-30 -28 -26 -24 -22 -20 -18 -16 -12 -10

45

50

55

60

65

70

75

80

85

90

95

IM3

(d

B)

Output Signal (dBV)

17dB improvement

Convetional

Linearized

Very linear OPAMP for >100MHz applications

C.-Y. Lu, “A 6th-order 200MHz IF

Bandpass Sigma-Delta Modulator

With over 68dB SNDR in 10MHz

Bandwidth,” JSSC, June 2010


TAMU-ECE MWCAS-2012

VOUT

R1

R1

Gm

VBP1-

VLP1-

VBP2-

VLP2-

VBP1+

VLP1+

VBP2+

VLP2+

R2

R3

R4

R5

R2

R3

R4

R5

VLP3-

VLP3+

RA

RB RC

RA

RCRB

CT

CT

RDAC2

VDAC2-

RDAC2

VDAC2+

CL

CL

Wide-band Adder with delay compensation

)(tan)(tan)( 11

pz

))((

))(()(2222

2

pz

pzpz

d

ddelay

The load resistor is split into 2 pieces and

one section replaced by an RC T-network

Rfeedback = Ra||(Rb+Rc) at low frequencies

Rfeedback = Ra at low frequencies


TAMU-ECE MWCAS-2012

Pulse Amplitude Modulation

Traditional Multi-level Digital Signal

Unit element current mismatch generates DAC non-linearity.

Ts

I

I/7

4I/7

sinj TIQ )(

]1,....7

2,

7

1,0[

where:

Ts

I

I/7

4I/7

Ts

I

I/7

4I/7

Ts

I

I/7

4I/7


TAMU-ECE MWCAS-2012

Time-Domain Pulse Width Modulation

Only inherently linear 1-level DAC achieve multi-bit feedback

PWM scheme employing multi-phase controller

Ts/7

)( sinj TIQ

]1,....7

2,

7

1,0[

where:

I

2Ts/7

I

4Ts/7

I

Ts

I


TAMU-ECE MWCAS-2012

Systematic (Nonlinearity) errors

Error Charge from Device Mismatch

4Ts/7

I

serr ITT

TQ )(2

D

Ts

I

I/7

4I/7

serr ITI

INQ )(

D

Conventional Multi-Level DAC

1-level PWM DAC

Current errors accumulate

Timing errors at the pulse edges


TAMU-ECE MWCAS-2012

INL, DNL and Linearity

Robustness to device mismatch

only affect the edges of the pulse

%5.0

%16.0

7

2

3

3

%

%

I

T

alconvention

PWM

HD

HD

PWM Linearity could be >10dB better!

%16.0% D

T

TT

%5.0% D

I

II


TAMU-ECE MWCAS-2012

Time-Domain Pulse Width Modulation

Pulse Arrangement To ease the design of interface circuitry

between quantizer and level-to-PWM converter

001

010

011

000 100

101

110

111

Ts

0

Ts/7

2T

s/7

3T

s/7

4T

s/7

5T

s/7

6T

s/7Ts

0

Ts/7

2T

s/7

3T

s/7

4T

s/7

5T

s/7

6T

s/7

-I

-I

-I

-I

+I

+I

+I

+I

22

2

102

10 y

speak

OSRTlogSJNR


TAMU-ECE MWCAS-2012

LC-VCO + CILFD

Phase noise of VCO is -119dBc/Hz @ 1MHz

CILFD phase noise is -136dBc/Hz @ 1MHz

b1

b2

b4

b5

Σb3

Level-to-PWM

Converter

VCO

3-Bit Two-Step

Quantizer

Vin

Digital

Output

3-Bit NRZ

DAC

1-B

it P

WM

DA

C

BP

LP

2nd

-Order

Filter



+

-BP

LP

2nd

-Order

Filter

Programmable Delay

4

11

LP

1st

-Order

CILFD

Φ1P

7-stage chain

phase order:

Φ1,Φ5,Φ2,Φ6,Φ3,Φ7,Φ4

Φ1N

Φ5P Φ5N

Φ4P Φ4N

VCOP

Vbn

VBP VBPVCON

Mpt

Mnt

Mp

Mn

7-stage chain

Vbn

(off-chip)

(off-chip) (off-chip)

(off-chip)

Jitter among phases is highly correlated


TAMU-ECE MWCAS-2012

The output is composed by 1 MSB + 3LSB

The MSB is determined first

Vin S/H

CLK

Vref1

Vref2

Vref3

Iin

Iref1

Iref2

Iref3

4:1 MUX

MSB

IrefCTRL

Rcmp

MSB

B2

B1

B0

Gm

Gm

Gm

Gm

Gm

VrefDC

Vcmp

IrefDC

(τ1)

(τ2)

(τ3)

(τ4)

τ1

τ4

τ3

τ2

b1

b2

b4

b5

Σb3

Level-to-PWM

Converter

VCO

3-Bit Two-Step

Quantizer

Vin

Digital

Output

3-Bit NRZ

DAC

1-B

it P

WM

DA

C

BP

LP

2nd

-Order

Filter



+

-BP

LP

2nd

-Order

Filter

Programmable Delay

4

11

LP

1st

-Order

CILFD

+Vref3 = +150mV

VrefMSB = 0V

0 Ts/7 2Ts/7 3Ts/7 4Ts/7 5Ts/7 6Ts/7 7Ts/7

B2 B1 B0

successive

comparisons to Vref (Iref)

S/H tracking

(for next cycle)

MSBsampling

MSB > VrefDC

MSB < VrefDC

Time

τ1

Differential Voltage Range= decision (latching) instant for a bit

sampling

+200mV

-200mVτ2 τ3 τ4

+Vref2 = +100mV

+Vref1 = +50mV

-Vref1 = -50mV

-Vref2 = -100mV

-Vref3 = -150mV

3-bit Algorithmic Quantizer


TAMU-ECE MWCAS-2012

Proposed Level-to-PWM Converter

SR latches generate the pulses

• AND gates + OR gates decide the required pulses

• Programmable Delay is used to minimize excess loop delay5-Input OR Gate

MSB B2

5-Input OR Gate

MSB B2

to 1-Bit

PWM DAC

Φ1

Φ3

ΔT

S

R

Q S

R

Q S

R

Q S

R

Q S

R

QΦ6

Φ1

Φ4

Φ5

Φ3

Φ4

Φ5

Φ6

B1B1

B0B0

S

R

Q

Q

Φ6 Φ4 Φ2 Φ1 Φ3

D Q

D QD Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

Programmable

Delay

b1

b2

b4

b5

Σb3

Level-to-PWM

Converter

VCO

3-Bit Two-Step

Quantizer

Vin

Digital

Output

3-Bit NRZ

DAC

1-B

it P

WM

DA

C

BP

LP

2nd

-Order

Filter



+

-BP

LP

2nd

-Order

Filter

Programmable Delay

4

11

LP

1st

-Order

CILFD


TAMU-ECE MWCAS-2012

Loop Filter +

Summing Amplifier

3-Bit Two-Step

Quantizer

VCO & Complementary

Injection-Locked

Frequency Divider

Level-to-PWM

Converter

DAC1 &DAC2

Buffers

Core area = 2.6mm2RMS jitter= 0.27ps => SJNR > 75dB

Chip Microphotograph & Clock Phase Noise Fabricated in Jazz Semiconductor, 180nm technology


TAMU-ECE MWCAS-2012

Output Spectrum of the Modulator

104 10

510

610

710

8

-140

-120

-100

-80

-60

-40

-20

0

Frequency (Hz)

Magn

itu

de

(dB

FS

)

78d

B

-2.2dBFS @ 5.08MHz

-70 -60 -50 -40 -30 -20 -10 0

0

10

20

30

40

50

60

70

Input Signal (dBFS)

SN

R &

SN

DR

(d

B)

-4.5 -4 -3.5 -3 -2.564

65

66

67

68

69

SNR

SNDR

DR=69dB

-5-5.5

Peak SNR= 68.5dB @25MHz BW

Peak SNDR= 67.7dB @25MHz BW

SFDR>70dB


TAMU-ECE MWCAS-2012

Signal to Distortion Ratio

Two tones with 2MHz apart and -2dBFS overall power

-72

-73

-74

-75

-76

0 5 10 15 20 25

Two-Tone Average Frequency (MHz)

IM

3 (

dB

)

-120

-100

-80

-60

-40

-20

0

107

Frequency (Hz)

Ma

gn

itu

de

(dB

FS

)

IM3

= -

76

.3d

B


TAMU-ECE MWCAS-2012

Quite relevant topology:

Quantizationnoise E1 gets cancelled

Notice that the auxiliary ADC processes the quantization error E1

What about Eq2?

2241241313

221241113

22122

1111

2413

qq

qqq

qq

q

ENTF*HESTF*HNTF*HXSTF*HzY

E*NTFE*STFHE*NTFX*STFHzY

Then

EzNTFEzSTFzY

EzNTFXzSTFzY

VzHYzHzY

Can we do better?Fundamentals on MASH architectures

Digital

+

1qE

DAC

Loop

Filter

ZY1 ZX ZH1

ZH2

+

2qE

ZY2+

H3

H4

+

ZY

ADC

+

-

+

-

Leslie and SinghISCAS-1990


TAMU-ECE MWCAS-2012

Schreier-Temes

Analog Intensive MASH topology

2

11

1

2

2

2

2

2

1

22413

2413 0

qq

q

q

E*NTF

X*STF

NTF

STF

E

ESQNR

ENTF*HXSTF*HzY

Then

STF*HNTF*HIf

Fundamentals on MASH architectures

+

1qE

DAC

Loop

Filter

ZY1 ZX ZH1

ZH2

+

2qE

ZY2+

H3

H4

+

ZY

ADC

+

-

+

-


TAMU-ECE MWCAS-2012

Analog Intensive Pseudo-MASH topology

Fundamentals on MASH architectures

RIN

kLP2

kBP2

kBP1

4-Bits

_

DELAYDigital signals (D1-D7)

Active-RC

4th

order

Filter

NR

Z

DA

C2

Clock

Generator

DA

C

Software

Platform

High-Resolution

Pipeline ADCN-bits

kLP1

CLK

Vin

Todd Brooks, et. al., JSSC, Dec 1997


TAMU-ECE MWCAS-2012

Efficient Pseudo-MASH architecture


TAMU-ECE MWCAS-2012

Target: SNDR Improvement by 3 bits

SQNR improvement should be around 18dB (3 bits)

Power overhead, area overhead < 20%

105

106

107

108

-160

-140

-120

-100

-80

-60

-40

-20

0

X: 5.005e+006

Y: -6.02

Power Spectrum of Output1

Frequency (Hz)

Po

we

r (d

BF

S)

SNR = 79.516dB

SNR = 105.803dB

Output With Cancelation

Output Without Cancelation


TAMU-ECE MWCAS-2012

Conclusions

Minimization of filtering functions in the receiver chain demands innovative ADC solutions;

SNDR > 80 dB will be frequently needed in wireless applications;

Jitter and Blocker tolerant architectures are needed;

DAC calibration techniques for fast and high-resolution applications;

Global tuning strategies (for stability)

Advanced LTE applications require high-resolution for signal BW as high as 200MHz


TAMU-ECE MWCAS-2012

Recommended Readings

S. Norsworthy, R. Schreier and G. Temes, Delta-Sigma Data Converters: Theory, Design and Simulation, IEEE Press

R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters, IEEE Press

J. Cherry, M. Snelgrove,Theory, Practice, and Fundamental Performance Limits of High-Speed Data Conversion Using Continuous-Time Delta-Sigma Modulators, Kluwer Academic Press.

J. M. de la Rosa, Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey, TCAS-I, Jan 2011.

Other tutorials: IECE-2012


TAMU-ECE MWCAS-2012


TAMU-ECE MWCAS-2012

98

Nice feature: Robust against blockers!

The DEM is usually slow and may lead to significant loop delay!

May require loop compensation


TAMU-ECE MWCAS-2012

part ii: recent advances on oversampled analog-to-...

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