DIGITAL TV TUNER FRONT END DESIGN

PART B

PLL & VGA

PREPARED BY:

AHMED MAHMOUD GABER

AHMED TAREK IBRAHIM

AYMAN HASSAN DORRAH

MOHAMED KHALIFA

PHASE LOCKED LOOP

PHASE FREQUENCY DETECTORS

• A rising edge on A yields a rising edge on QA (if QA is low).

• A rising edge on B resets QA (if QA is high).

BASIC PFD DESIGN

DRAWBACKS

A. The logic gates delay (reset delay)

DRAWBACKS

B. The dead zone

PROPOSED PFD

SIMULATION RESULTS

1. The frequency of reference (net018 ) 48 MHz> The feedback

frequency (net016) 40 MHz

SIMULATION RESULTS

2. The frequency of reference (net018 ) 48 MHz< The feedback

frequency (net016) 56 MHz

SIMULATION RESULTS

3. The frequency of reference (net018 ) 48 MHz= The feedback

frequency (net016) 48 MHz

CHARGE PUMP

SIMPLE SINGLE ENDED CP

When Up =1 I1 = I0 VOUT increase

DN =1 I2 = I0 VOUT decrease

DRAWBACKS

If Up = 0

S1 is OFF

I1 = 0

when an edge trigger happens at Up

S1 is ON

VOUT = VDD

∴ transient ripples at the output

DIFFERENTIAL CP

If Up = 1 and DN = 0

I1 = I0 I2 charge the buffer ∴ Current sources will be always ON

DRAWBACKS

If DN = 1

When VOUT decrease

Voltage at node B decrease

∴ the current and the output swing will decrease

PROPOSED CHARGE PUMP

DESIGN PROCEDURE

=−

+ + +

=− +

1

1

+ + +

=

∗

1

=

∗

1

SIMULATION RESULT

1. The output voltage of the charge pump when the 2 inputs are zeros

SIMULATION RESULT

The output voltage

SIMULATION RESULT

Up and Down current matching

LOOP FILTER

To efficiently suppress the ripples we have to use a second capacitor.Where C2=0.25 C1

LOOP FILTER

ℑ =1

2

IpC1 !

2πM

$ =Ip !

2πMC1

R1 =95 Ω, C1=12.7 nF , C2=3.175nF

KVCO = 5.051GHz/V M=140 and ℑ =0.9

%& = tan*+ 4- 1 ++

./−tan*+ 4-

012

031 +

+

./

PM=39.5° which ensures the stability of the system

PLL BUILDING BLOCKS

VOLTAGE-CONTROLLED OSCILLATORS

CHALLENGES IN THE DESIGN OF VCOS FOR

THE TV TUNER SYSTEM

• Wide Tuning Range (48MHz to 862MHz in a direct conversion

receiver) (1:20)

• Strict Phase Noise Requirements

• Large VCO gain

• Output sensitivity to noise on the control line

• Common solution: using multiple VCOs

• Drawbacks: more power dissipation, larger chip size,

complex control circuit, etc…

DISCRETE TUNING LC VCO USING SWITCHED

CAPACITORS

Implemented by Yu-Che Yang and Shey-Shi Lu, 2010.

Drawbacks: • Large Chip Area

(inductors)

• Complex Control circuit

required (AFC)

• Bad frequency

Pushing (Separate

Supply)

• Large Bank of

Capacitors

• Switches degrade the quality

factor (high phase noise)

FIRST ATTEMPT: THE PMOS-LOAD THREE-

STAGE RING VCO

Amplifier Stage Current Tuning Stage using a

Current-Folding Differential

Amplifier

Drawbacks: • Variable Current (Power

dissipation)

• Very high Phase Noise

• Variable Signal Power

Level.

• Variable Common-Mode

Level (Output Swing)

FIRST ATTEMPT: SIMULATION RESULTS

Current Tuning Frequency Tuning (1:24)

Phase Noise @1MHz Offset Frequency

SECOND ATTEMPT: A THREE-STAGE RING VCO WITH

POSITIVE RESISTANCE AND INTERPOLATION

Positive Feedback using

a Cross-coupled Pair

Interpolation between

fast and a slow paths

SECOND ATTEMPT: A THREE-STAGE RING VCO WITH

POSITIVE RESISTANCE AND INTERPOLATION

Combination of the Positive Feedback using

a cross-coupled pair and interpolation

between the fast and slow paths

SECOND ATTEMPT: SIMULATION RESULTS

Frequency Tuning (1:30) Phase Noise at 1MHz offset

frequency

Drawbacks: • Very high sensitivity • Phase Noise decreased by

10dB but is still high

THIRD ATTEMPT: A FOUR-STAGE RING VCO WITH

POSITIVE RESISTANCE AND INTERPOLATION (WITH ADDITIONAL TAIL CAPACITANCE)

Note: the additional tail capacitance is not

shown in the drawing.

THIRD ATTEMPT: SIMULATION RESULTS

Frequency Tuning (1:20) Phase Noise at 1MHz offset

frequency

Advantages: • Appropriate sensitivity attainable • Constant Common-Mode

Level (Output Swing)

• Phase Noise decreased further by

10dB and is now satisfactory

(More Noise Immune)

• Constant Signal Power

Level across

FIRST ATTEMPT SECOND ATTEMPT THIRD ATTEMPT *

PMOS-Load 3-stage3-stage with Interpolation

and Positive Feedback

4-stage with Interpolation

and Positive Feedback

41 MHz 980 MHz 43 MHz 1.295 GHz 42 MHz 867 MHz

Tuning Range 983 MHz (1:24) 1.252GHz (1:30) 825MHz (1:20)

Differential

Peak Swing0.4V 0.8V 0.43 0.1 0.52 0.37

Max

Sensitivity1.788 X109 3.377 X109 5.051 X109

Power

Dissipation

-41.11dB

(77µW)

-27.1dB

(1.95mW)

-20.95dB

(8mW)

-22.96dB

(5mW)

-20.97dB

(8mW)

-20.84dB

(8.2mW)

Signal Level -23.9dBm -7.33dBm 3.516dBm 4.13dBm -9.916dBm -14.92dBm

Output

Phase Noise

@

1MHzoffset

-101.5dBc/Hz -84.55dBc/Hz -110.4dBc/Hz -91.87dBc/Hz -121.1dBc/Hz -105dBc/Hz

Frequency

Pushing

(max-min)

4MHz 54.2MHz 5.5MHz 219MHz 3.24MHz 131MHz

Figure of

Merit (FOM)171.50dB 174.79dB 179.59dB

* Recommended Design for the Digital TV Tuner System.

COMPARISON OF SIMULATION RESULTS

PLL BUILDING BLOCKS

FREQUENCY DIVIDERS

Master-Slave D Flip-Flop

FREQUENCY DIVIDER BASIC

UNIT (÷2)

CML

• High Speed (10 GHz) – Differential

• Large Power and Area

BASIC UNIT (÷2) DESIGN

APPROACHES

TSPC

• Small Power and Area – Compatibility with CMOS

• Moderate Speed (4 GHz) – Single Ended

BASIC UNIT (÷2) DESIGN

APPROACHES

Divide-by-2N

• High Modulus-to-Size Ratio

• Asynchronous (High Propagation Delay)

GENERAL MODULUS

FREQUENCY DIVIDER (÷M)

Divide-by-2N

• Synchronous (Low Delay) – 50% Duty Cycle

• Relatively Low Modulus-to-Size Ratio

GENERAL MODULUS

FREQUENCY DIVIDER (÷M)

Divide-by-N

• Synchronous (Low Delay)

• Low Modulus-to-Size Ratio – NOT 50% Duty Cycle

GENERAL MODULUS

FREQUENCY DIVIDER (÷M)

Divide-by-[m(2N–r)+kr]

Can be modified to divide by 2 16 with 4 FFs only!

GENERAL MODULUS

FREQUENCY DIVIDER (÷M)

Divide-by-[S+NP]

PULSE SWALLOW DIVIDER

TV TUNER FREQUENCY PLANNING

AND DIVIDER DESIGN

P

PS-

Counter

bits

S M = S + P fVCO (MHz) = M 6 MHz

From Step To From Step To From Step To

8 3-bit 0 1 7 8 1 15 48 6 90

16 4-bit 0 1 15 16 1 31 96 6 186

32 5-bit 0 1 31 32 1 63 192 6 378

64 6-bit 0 1 63 64 1 128 384 6 762

128 7-bit 0 1 12 128 1 140 768 6 840

P P16 P32 P64 P128

8 1 1 1 1

16 0 1 1 1

32 0 0 1 1

64 0 0 0 1

128 0 0 0 0

TV TUNER FREQUENCY

DIVIDER SIMULATION

TV TUNER FREQUENCY

DIVIDER SIMULATION

PLL BUILDING BLOCKS

∑∆∑∆∑∆∑∆-MODULATOR

FRACTIONAL-N PLL

ROLE OF ∑∆∑∆∑∆∑∆-MODULATOR

Noise Shaping

Modulus Randomization

Noise Level Reduction

FIRST ORDERDIGITAL ∑∆∑∆∑∆∑∆-MODULATOR

3-bit at input 2/8 3-bit at input 5/8

SECOND ORDERDIGITAL ∑∆∑∆∑∆∑∆-MODULATOR

3-bit at input 2/8 3-bit at input 5/8

MASH 1-1DIGITAL ∑∆∑∆∑∆∑∆-MODULATOR

Yout Modulus

11 N-1

00 N

01 N+1

10 N+2

TV TUNER FREQUENCY PLANNING

AND PROPOSED DIVIDER DESIGN

Modulus MC1 MC2 MC3 MC4

0.75 0 1 1 1

1 0 0 1 1

1.25 0 0 0 1

1.5 0 0 0 0

1.75 1 0 0 0

2 1 1 0 0

2.25 1 1 1 0

N 2N1+a a fVCO (MHz) = 2N(1+a)

From Step To From Step To From Step To

0 1 1 1/8 15/8 0 1/8 7/8 48 6 90

1 2 1 1/16 31/16 0 1/16 15/16 96 6 186

2 4 1 1/32 63/32 0 1/32 31/32 192 6 378

3 8 1 1/64 127/64 0 1/64 128 384 6 762

4 16 1 1/128140/12

80 1/128 140 768 6 840

TV TUNER PROPOSED∑∆∑∆∑∆∑∆-MODULATOR DESIGN

Dithering

VARIABLE GAIN AMPLIFIER

(VGA)

WHY VGA ?

1. Wide dynamic gain range

2. Precise gain control

3. Good linearity

4. Low noise figure

PRE-DISTORTION COMPENSATION TECHNIQUE

• CMOS dB-linear VGAs are based on a pseudo-exponential function.

Errors to the ideal one is 5% when |x|<0.32

• Using Taylor expansion, the second-order approximation can be expressed as

The approximation error of can be less than 5% when -0.575 < x < 0.815

is satisfied.

INTRODUCTION

56 ≅1 + 8

1 − 8

56 ≅ 1 + 8 +8

2

CIRCUIT DESCRIPTION

A. Differential linear variable gain amplifier:

There are three methods to control the gain of a VGA by varying

a) The tranconductance of a MOS device in the saturation region.

b) The load resistance.

c) The source degeneration resistance which is often implemented by

a MOS device operated in the linear region.

The last method has the advantages of good linearity, low noise figure

and low power dissipation because the source degeneration does not

impose any penalty on voltage headroom in a simple differential pair.

A. DIFFERENTIAL LINEAR VGA

• M3 and M4 form the linear transconductance pair.

• M5 and M6 act as the active load

to provide high gain.

• M7 and M8 are used to improve

the linearity.

• The common-mode feedback

Circuit consists of R1, R2

and M10-M13.

• The source degeneration

transistor M14 is used to adjust

gain.

A. DIFFERENTIAL LINEAR VGA

Therefore, the gain of the VGA can be linearly controlled by the gate

voltage of M14.

= −9:;

+ 9:

9: = <=>6

?@: − ?AB

≫ 9: and@D

@DEFG≅ 1

= −9:;

+ 9:≈ −<=>6

+?@:+ − ?AB

B. EXPONENTIAL FUNCTION GENERATION

CIRCUIT

IJK = 2L?M=!

I0 = 4I

Using this condition −0.575 <@SJTU

V

KW< 0.815 and Taylor series

expansion, the o/p current can be re-written as

IYA ≈1

8I2 4I

58Z2L?M=

!

4I= 4I58Z

L?M=!

2I

?0A[\ = ]IYA = 4]I58ZL?M=

!

2I

This voltage is used to control the gain of the linear VGA and hence a

dB-linear VGA is realized.

B. EXPONENTIAL FUNCTION GENERATION

CIRCUIT

DB LINEARITY COMPENSATION

Practically, there is a problem that affects the linearity which is the non-zero

source and the threshold Voltage.

Considering the effect of gate-source voltage and the threshold voltage of

M14. After taking logarithm, the gain is given by

20 ^_ = 20 ^_; + 20 ^_ 4]I 58ZL?M=

!

2I− ?:A

Where ?:A=?:+?AB

Since Vst is not zero, the gain of the VGA will not be dB-linearly proportional

to ?M=! .

THE NON-ZERO SOURCE AND THE

THRESHOLD VOLTAGE

To compensate this nonlinearity, a fixed current Icm1=J:A

`]

is added to Iout

and the control voltage becomes

?0A[\a = IYA + I0b+ ] = ?0A[\ + ?:A

By substituting in gain equation

20 log = 20 log; + 20 log 4]I expL?M=

!

2I

Therefore, the effect of ?:A is removed.

SIMULATION RESULTS

The simulation result for the

exponential circuit with the pre-

distortion technique when ICM1 is

set to zero.

Results of the both dB-linear

uncompensated and compensated VGA.

SUMMARY

Reference Measurements

Supply Voltage 3 V

I/P Frequency Range > 10 MHz

Gain Error ± 1dB

Power Consumption 35 mw

Gain Range 60 dB

LOW GAIN

HIGH GAIN

84 DB-LINEAR LOW POWER

84 DB-LINEAR LOW POWER

A New Exponential Approximation Equation where a very low power,

small chip size and a wide control gain range can be obtained.

5h6 =5h6

5*h6≅

i + 1 + j8

i + 1 − j8

As can be seen in Fig. 1, for k = 0.15 (the solid line), the dB-linear range

extends to more than 60dB with a linearity error of less than ±0.5dB,

which is a serious improvement compared to the Taylor series

approximation and pseudo-exponential functions.

INTRODUCTION

CIRCUIT IMPLEMENTATION

A. The control circuit block:

The current ratio is a function of ?! and the value of k can be changed by

adjusting I resulting in different dB-linear ranges.

?! is from ?kl= to (1.8 - |?klm|).

I0

I0+=

I ? − ?kl

+ 1 +?0

? − ?kl

I ? − ?kl

+ 1 −?0

? − ?kl

=i + 1 + j8

i + 1 − j8

Where i =KW

n Joo* Jpq/ , j =

+

Joo* Jpqj$s8 = ?0

A. THE CONTROL CIRCUIT BLOCK

The currents in the loads and the input pair are respectively controlled

by IC1 and IC2 from the control block and they are mirrored to (M13 and

M14).

The CMFB is also controlled by ?!.

B. VGA CIRCUIT

The gain is a function of ?!. By adjusting I to get k = 0.15, the

amplifying block can provide more than 60dB of the gain variation.

=*M=mYA

*\h;

= ⁄ M=mYAI0

⁄ \h;I0+

=*M=mYA

*\h;

= ⁄ M=mYA

⁄ \h;

∗i + 1 + j8

i + 1 − j8

B. VGA CIRCUIT

MEASUREMENT RESULTS

?kl==|?klm|= 0.4v and ?! is from 0.4 to 1.4V

Total gain range is of 84dB and with a linearity error of less than ±1dB.

MAXIMUM GM

MINIMUM GM