parallel stateful logic in rram: theoretical analysis and

Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design

Feng Wang, Guojie Luo, Guangyu Sun, Jiaxi Zhang, Peng Huang, Jinfeng Kang

[email protected]

2019/07/16

mailto:[email protected]

OUTLINE

Background

Theoretical Analysis

Integer Addition

Extension

Experimental Evaluation

Conclusion

RRAM Resistance for Representing Logic Values

[1] Akinaga, H., & Shima, H. (2010). Resistive random access memory (ReRAM) based on metal oxides. Proceedings of the IEEE.

3

HRS (logical 0)

LRS(logical 1)

SET (𝑈𝑊𝐿 − 𝑈𝐵𝐿 > 𝑉𝑆𝐸𝑇 )

RESET (𝑈𝐵𝐿 − 𝑈𝑊𝐿 > 𝑉𝑅𝐸𝑆𝐸𝑇 )

metal

metal

insulator

WL

BL

RRAM State Switching as Primitive Logic Operations

[2] Kvatinsky, S., Member, S., Belousov, D., Liman, S., Satat, G., Member, S., … Weiser, U. C. (2014). MAGIC — Memristor-Aided Logic. TCAS-II.

4

MAGIC NOR implementation 𝑍 = NOR(𝑋, 𝑌)

– 𝑉𝐺 > 2 ⋅ 𝑉𝑅𝐸𝑆𝐸𝑇

Parallel execution over rows and columns

– WL parallelism: 𝑅𝑖𝑚 = NOR 𝑅𝑖1, 𝑅𝑖2 𝑖 ∈ [1,𝑚]

– BL parallelism: 𝑅𝑚𝑖 = NOR(𝑅1𝑖 , 𝑅2𝑖) 𝑖 ∈ [1, 𝑚]

VG VG GND R1

R1

R1

R1 R1

R1

R1

R1

R1

BL voltage controller

WL1

WL2

WLm

BL1 BL2 BLm

R11 R12 R1m

R21 R22 R2m

Rm1 Rm2 Rmm

RRAM cell

RRAM-based Stateful Logic Families

[3] Borghetti, J., Snider, G. S., Kuekes, P. J., Yang, J. J., Stewart, D. R., & Williams, R. S. (2010). “Memristive” switches enable “stateful” logic operations via

material implication. Nature.

[4] Huang, P., Kang, J., Zhao, Y., Chen, S., Han, R., Zhou, Z., … Liu, X. (2016). Reconfigurable Nonvolatile Logic Operations in Resistance Switching Crossbar

Array for Large-Scale Circuits. Advanced Materials.

[5] Avati, V., Eggert, K., & Taylor, C. (2018). FELIX: Fast and Energy-Efficient Logic in Memory. In ICCAD.

[6] Xu, L., Bao, L., Zhang, T., Yang, K., Cai, Y., Yang, Y., & Huang, R. (2018). Nonvolatile memristor as a new platform for non-von Neumann computing. In

ICSICT.

5

Support parallel execution

Functionally complete

Work Stateful logic operations

[3] IMP

[2] NOR, NOT

[4] NAND, NIMP

[5] NOR, NAND, Min, OR

[6] NOR, NOT, NAND, NIMP, XOR

OUTLINE

Background


Integer Addition

Extension


Conclusion

SIML Computation Model7

All of the stateful logic families satisfy the four assumptions

– The latency of a single stateful logic operation is identical.

– The input number of a single operation cannot exceed a constant.

– The latency of WL and BL operations is identical.

– The degree of parallelism can reach the crossbar size. The crossbar size scales with the problem size.

Lower Bounds of the Time Complexity (1)8

(a) Theorem 1 (b) Theorem 2

Condition bitwise functions most arithmetic functions

Parallelismupper bound

max(𝑤, ℎ) 𝑂𝑇

𝑤 + ℎ

Time complexity lower bound

trivial bound: 𝑂𝑇

max(𝑤,ℎ)shape bound: 𝑂(𝑤 + ℎ)

Example function 𝑌𝑖 = 𝑋𝑖1 NOR 𝑋𝑖2 (𝑖 = 1, 2,… , 𝑛) 𝑌𝑖 = NOR𝑘=1𝑖 𝑋𝑘1 NOR 𝑋𝑖2 (𝑖 = 1, 2, … , 𝑛)

Example algorithm (netlist)

Example layout in RRAM

𝑋11 𝑋21 … 𝑋𝑛1

𝑋12 𝑋22 … 𝑋𝑛2

𝑌1 𝑌2 … 𝑌𝑛

𝑋11 𝑋21 … 𝑋𝑛1

𝑋12 𝑋22 … 𝑋𝑛2

𝑌1 𝑌2 … 𝑌𝑛

𝑋11

𝑋12

𝑌1 … 𝑋𝑛1

𝑋𝑛2

𝑌𝑛

#1

#1 #1 #1

#n-1

#n #n #n

𝑋11

𝑋21 𝑋𝑛1

…

𝑋𝑛2

𝑌𝑛

𝑂(𝑇): total cycles in the series implementation, 𝑤: width of layout (# of BLs), ℎ: height of layout (# of WLs), 𝑙𝑒𝑛𝑚𝑎𝑥: length of the critical path.

Lower Bounds of the Time Complexity (2)9

(c) Corollary 1 (d) Theorem 3

Condition square layout a given algorithm

Parallelismupper bound

𝑂(𝑇

𝑤ℎ) 𝑂

𝑇

𝑙𝑒𝑛𝑚𝑎𝑥

Time complexity lower bound

function bound: 𝑂( 𝑤ℎ) algorithm bound: 𝑙𝑒𝑛𝑚𝑎𝑥

Example function — 𝑌 = NOR𝑘=1𝑛 𝑋𝑘1

Example algorithm (netlist)

—

Example layout in RRAM

—

𝑂(𝑇): total cycles in the series implementation, 𝑤: width of layout (# of BLs), ℎ: height of layout (# of WLs), 𝑙𝑒𝑛𝑚𝑎𝑥: length of the critical path.

𝑋1 𝑋2 … 𝑋𝑛 𝑌𝑛

𝑋1

𝑋2 𝑋𝑛

𝑌…

#1 #n-1

OUTLINE

Background


Integer Addition

Extension


Conclusion

Ripple Carry Adder11

One-bit full adder

Pulse Logic operation

1 𝑇1 = NOR(𝐴, 𝐵)

2 𝑇2 = NOR(𝐴, 𝑇1)

3 𝑇3 = NOR 𝐵, 𝑇1

4 𝑇4 = NOR(𝑇1, 𝑇2)

5 𝑇5 = NOR(𝑇4, 𝐶𝑖)

6 𝐶𝑜 = NOR(𝑇1, 𝑇5)

7 𝑇6 = NOR(𝑇4, 𝑇5)

8 𝑇7 = NOR(𝑇5, 𝐶𝑖)

9 𝑆 = NOR(𝑇5, 𝑇7)

𝑨𝟏𝟏 𝑨𝟏𝟐 … 𝑨𝟏𝒏

𝑨𝟐𝟏 𝑨𝟐𝟐 … 𝑨𝟐𝒏

𝑇11 𝑇12 … 𝑇1𝑛

… … … …

𝑇41 𝑇42 … 𝑇4𝑛

𝑇51 𝑇52 … 𝑇5𝑛

𝐶𝑖1 𝐶𝑜2 … 𝐶𝑜𝑛

𝐶𝑜1 𝐶𝑜1(𝐶𝑖2) … 𝐶𝑜 𝑛−1 (𝐶𝑖𝑛)

𝑇61 𝑇62 … 𝑇6𝑛

… … … …

𝑺𝟏 𝑺𝟐 … 𝑺𝒏

②

③

①

①③ add 𝑛 BLs in parallel ② generate and propagate carries in series

time complexity: 𝑂(𝑛)shape / algorithm lower bound

Carry Select Adder12

𝑨𝟏𝟏 … 𝑨𝟏 𝒏 𝑨𝟐𝟏 … 𝑨𝟐 𝒏 0 𝑆1 … 𝑆 𝑛

𝑨𝟏( 𝒏+𝟏) … 𝑨𝟏(𝟐 𝒏) 𝑨𝟐( 𝒏+𝟏) … 𝑨𝟐(𝟐 𝒏) 0 𝑆 𝑛+1 … 𝑆2 𝑛

… … … … … … … … … …

𝑨𝟏(𝒏− 𝒏+𝟏) … 𝑨𝟏𝒏 𝑨𝟐(𝒏− 𝒏+𝟏) … 𝑨𝟐𝒏 0 𝑆𝑛− 𝑛+1 … 𝑆𝑛′

𝐴1( 𝑛+1)′ … 𝐴1(2 𝑛)′ 𝐴2( 𝑛+1)′ … 𝐴2(2 𝑛)′ 1 𝑆 𝑛+1′ … 𝑆2 𝑛′

… … … … … … … … … …

𝐴1(𝑛− 𝑛+1)′ … 𝐴1𝑛′ 𝐴2(𝑛− 𝑛+1)′ … 𝐴2𝑛′ 1 𝑆𝑛− 𝑛+1′ … 𝑆𝑛′

… … … … … … 𝑺𝟏 … 𝑺 𝒏

… … … … … … 𝑺 𝒏+𝟏 … 𝑺𝟐 𝒏

… … … … … … … … …

… … … … … … 𝑺𝒏− 𝒏+𝟏 … 𝑺𝒏

①

③

②

① copy the input ② add 2 𝑛 − 1 WLs in parallel ③ select the correct result

time complexity: 𝑂( 𝑛)function / algorithm lower bound

Carry Save Adder13

𝑨𝟏𝟏 𝑨𝟏𝟐 … 𝑨𝟏𝒏

𝑨𝟐𝟏 𝑨𝟐𝟐 … 𝑨𝟐𝒏

𝑨𝟑𝟏 𝑨𝟑𝟐 … 𝑨𝟑𝒏

… … … …

𝐶𝑜1 𝐶𝑜2 … 𝐶𝑜𝑛

𝑃𝑆1 𝑃𝑆2 … 𝑃𝑆𝑛

0 𝐶𝑜1 … 𝐶𝑜(𝑛−1)

𝑃𝑆1 𝑃𝑆2 … 𝑃𝑆𝑛

… … … …

𝑺𝟏 𝑺𝟐 … 𝑺𝒏

shift 𝐶𝑜1, …,𝐶𝑜𝑛 right

①

③

① add 𝑛 BLs in parallel ③ add the last two addends 𝐶𝑜, 𝑃𝑆

②

time complexity: 𝑂( 𝑀)function lower bound

𝑎1 … 𝑎 𝑀 𝐴1

𝑎 𝑀+1 … 𝑎2 𝑀 𝐴2

… … … …

𝑎𝑀− 𝑀+1 … 𝑎𝑀 𝐴 𝑀

… … … 𝒂

① accumulate each WL in parallel② accumulate the sums in the same BLs

①②

Adder Summary14

Function two 𝒏-bit integer addition 𝑴 integer addition

Algorithm ripple carry adder carry select adder carry select adder

Layout 𝑂 𝑛 × 𝑂(1) 𝑂 𝑛 × 𝑂( 𝑛) 𝑂 𝑀 × 𝑂( 𝑀)

Time complexity 𝑂(𝑛) 𝑂( 𝑛) 𝑂( 𝑀)

Lower bound type shape / algorithm bound function / algorithm bound function bound

OUTLINE

Background


Integer Addition

Extension


Conclusion

Dot Product16

𝒂𝟏𝟏 … 𝒂𝟏 𝑴 𝒂𝟐𝟏 … 𝒂𝟐 𝑴 𝑃1 … 𝑃 𝑀 𝑆1

𝒂𝟏( 𝑴+𝟏) … 𝒂𝟏(𝟐 𝑴) 𝒂𝟐( 𝑴+𝟏) … 𝒂𝟐(𝟐 𝑴) 𝑃 𝑀+1 … 𝑃2 𝑀 𝑆2

… … … … … … … … … …

𝒂𝟏(𝑴− 𝑴+𝟏) … 𝒂𝟏𝑴 𝒂𝟐(𝑴− 𝑴+𝟏) … 𝒂𝟐𝑴 𝑃𝑀− 𝑀+1 … 𝑃𝑀 𝑆 𝑀

… … … … … … … … … …

… … … … … … … … … …

… … … … … … … … … 𝐶𝑜

… … … … … … … … … 𝑃𝑆

… … … … … … … … … …

… … … … … … … … … …

… … … … … … … … … 𝑨𝟏 ⋅ 𝑨𝟐

①

③

① element-wise multiplication ② accumulate 𝑀 WLs in parallel ③ accumulate 𝑆𝑘s using the carry save adder

②

time complexity: 𝑂( 𝑀)function lower bound

Real Data Type Comparison

[7] Köster, U., Webb, T. J., Wang, X., Nassar, M., Bansal, A. K., Constable, W. H., … Rao, N. (2017). Flexpoint: An Adaptive Numerical Format for Efficient Training of

Deep Neural Networks. arXiv.

17

···

···

······

···

···

··· ···

···

fixed-point flex-point

float-point

exponent mantissa

Flex-point Support18

𝒂𝟏𝟏 𝒂𝟐𝟏 … 𝑎31

𝒂𝟏𝟐 𝒂𝟐𝟐 … 𝑎32

… … … …

𝒂𝟏𝒏 𝒂𝟐𝒏 … 𝑎3𝑛

Co

ntr

olle

r𝒆𝒙𝒑𝟏 𝒆𝒙𝒑𝟐 … 𝑒𝑥𝑝3

① input exponent

② arithmetic instruction

③ output status

④ shift instruction

⑤ output exponent

Crossbar

OUTLINE

Background


Integer Addition

Extension


Conclusion

Integer Algorithm Evaluation20

0

200

400

600

800

8 16 24 32 40 48 56 64

cycl

e

bit width n

MAGIC-adder [8]

ripple carry

carry select

100

1000

10000

100000

1000000

16 32 64 128 256 512 10242048

cycl

e

integer number M

MAGIC-adder [8]

APIM [9]

carry save

0

20000

40000

60000

80000

16 32 64 128 256 512 1024 2048

max

imal

M

crossbar size

APIM [9]

carry save

0

1000

2000

3000

4000

64 128 256 512

cycl

e

vector dimension M

IMAGING [10] Proposed

[8] Talati, N., Gupta, S., Mane, P., & Kvatinsky, S. (2016). Logic design within memristive memories using memristor-aided loGIC (MAGIC). TNANO.

[9] Imani, M., Gupta, S., & Rosing, T. (2017). Ultra-Efficient Processing In-Memory for Data Intensive Applications. In DAC.

Flex-support Evaluation21

0

2

4

6

8

10

100 400 700 1000

Late

ncy

(s)

Matrix size M

RRAM ARM

0

1

2

3

4

100 400 700 1000

Ener

gy /

M³

(nJ)

Matrix size M

RRAM ARM

OUTLINE

Background


Integer Addition

Extension


Conclusion

Conclusion23

Theoretical analysis

– SIML model

– time complexity lower bound

Integer addition

– ripple carry adder

– carry select adder

– carry save adder

Extension

– multiplication support

– flex-point support

parallel stateful logic in rram: theoretical analysis and

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