Paging • Paging is a memory-management scheme that permits the physical-address space

of a process to be noncontiguous.

• Paging avoids the considerable problem of fitting the varying-sized memory chunks onto the backing store, from which most of the previous memory-management schemes suffered.

• When a process is to be executed, its pages are loaded into any available memory frames from the backing store.

• Physical memory is broken down into fixed-sized blocks (equal size), called frames.

• logical memory is divided into blocks of the same size, called pages. (At the time of process execution process address space will be created.)

• Size of page=size of frame=offset

• The following snapshots show process address space with pages (i.e., logical address space), physical address space with frames, loading of paging into frames, and storing mapping of pages into frames in a page table.

Mapping paging in the logical into the frames in the physical address space and keeping this mapping in the page table

Paging

Example • Page size = 4 bytes • Process address space = 4 pages • Physical address space = 8 frames • Logical address: (1,3) = 0111 • Physical address: (6,3) = 11011

00000 000001 100010 200011 300100 400101 500110 600111 701000 801001 901010 1001011 1101100 1201101 1301110 1401111 1510000 1610001 1710010 1810011 1910100 2010101 2110110 2210111 2311000 2411001 2511010 2611011 2711100 2811101 2911110 3011111 31

0000000100100011010001010110011110001001101010111100110111101111

Logical address: (1,0) = 0100 (page no., offset)

Physical address: (6,0) = 11000 (frame no, offset)

(Offset will be same for both addresses)

Address mapping• Using a page size of 4 bytes and • physical memory of 32 bytes (8 frames ), • we show how the user's view of memory can be mapped into physical

memory. • Logical address 0 (0000) is (0,0) page 0, offset 0. Indexing into the page

table, we find that page 0 is in frame 5. Thus, logical address 0 maps to physical address 20 (= (5 x 4) + 0).

• Logical address 3 (0011) (page 0, offset 3) maps to physical address 23 (= (5 x 4) + 3).

• Logical address 4 (0100) is (1,0) page 1, offset 0; according to the page table, page 1 is mapped to frame 6. Thus, logical address 4 maps to physical address 24 (= (6 x 4) + 0).

• Logical address 13 maps to physical address 9 and so on.

• Physical address= (frame no* frame size)+ offset

Protection Memory protection implemented by associating protection bit with each frame.Valid-invalid bit attached to each entry in the page table: 1. “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page. 2. “invalid” indicates that the page is not in the process’ logical address space.

Paging issues • When we use a paging scheme, we have no external fragmentation: Any

free frame can be allocated to a process that needs it. However, we may have some internal fragmentation.

• For example, if pages are 2,048 bytes, a process of 72,766 bytes would need 35 pages plus 1,086 bytes. It would be allocated 36 frames, resulting in an internal fragmentation of 2048 -1086 = 962 bytes. In the worst case, a process would need n pages plus one byte. It would be allocated n + 1 frames, resulting in an internal fragmentation of almost an entire frame.

• The problem with this approach is the time required to access a user memory location. With this scheme, two memory accesses are needed to access a byte (one for the page-table entry, one for the byte).

• The standard solution to this problem is to use a special, small, fast lookup hardware cache, called translation look-aside buffer (TLB). The TLB is associative, high-speed memory.

Translation look-aside buffer (TLB)

Effective memory-access time

• Effective access time or average access time=h*(TTLB+TMM)+(1-h)*(TTLB+TMM+TMM)

• TLB Hit ratio: h*(TTLB+TMM)• TLB Miss ratio: (1-h)*(TTLB+TMM+TMM)

• TTLB= Time to search in TLB• TMM= Time to search in RAM

Example

• Tmm=100 nsec• TTLB=20 nsec• Hit ratio is 80%• TEAT=?• TEAT= (80%)(20+100)+(20%)(20+2*100)

= 0.8*120+0.2*220= 140 nsec

Page table issues• In such an environment, the page table itself becomes

excessively large. For example, consider a system with a 32-bit logical-address space. If the page size in such a system is 4 KB (212), then a page table may consist of up to 1 million entries (232/212). Assuming that each entry consists of 4 bytes, each process may need up to 4 MB of physical-address space for the page table alone.

• Means calculated page table size (4MB) is grater then available page size (4KB) (available frame size in memory) that’s way, clearly, we would not want to allocate the page table contiguously in main memory. One simple solution to this problem is to divide the page table into smaller pieces.

• One way is to use a two-level paging or multilevel paging algorithm, in which the page table itself is also paged.

Multi level paging• Page table needed for keeping track of pages of

the page table called the outer page table or page directory.

• Paging level (structure) depends on size of logical address space and size of page size.

• In previous example : – No. of pages in the outer page table is 4M/4K=1K=210

pages=10 bits • Size of the outer page table is – 1K*4 byte= 4Kbytes -----outer page will fit in one page

because page size is 4Kbytes.

10 bit 10 bit

32 bit

12 bit

Size of outer table 1K*4Bytes

Example (VAX architecture)• Given Logical address 32 bits• So size of logical address space 232 bytes• Given Page size 512 bytes=29 bytes=offset• Given size of page table entry=4 bytes• Logical address space of process divided into 4 equal

sections means (22 )required 2 bit to represent each section.

• Size of each section is 232 bytes/22 = 230 bytes• Each section has 230 bytes/29 bytes=221 pages, So 21

bits required to index page table for a section.• Size of page table=221 bytes*4 bytes=223 bytes=8MB

• Page table size is grater then page size so required multilevel paging

• then 8MB page table is paged into 8MB/512 bytes=~ 2K pages= 211 pages. (number of pages in outer page table, needed 11 bits)

• Size of outer page table is 2K *4 bytes=8KB• 8KB is grater then page size so outer page table is

further paged. Result is 3-level paging required in each sections.

Section2 bits

Page no21 bits

Offset 9 bits

Other example • Given logical address 64 bits• Then size of logical address space= 264 bytes• Given page size 4KB= 212 bytes=needed 12 bits

------64 bits-------

• Then page table consist of 252 entries.• And size of page table is 252 *4bytes(given)= 254 bytes• Size of page table is grater then memory page size so required

multilevel paging means page table is divided into pages.• Page table is paged into 254 bytes/ 212 bytes= 242 pages (no. of pages

in outer page table, required bit 42 for outer page table)• 52 bits page no divided into 42 bit outer page and 10 bit inner

pages

Page no52 bits

Offset 12 bits

• Then outer page table size is 242 *4 bytes= 244 bytes.• Outer page table size is grater then page size then further divides outer page table

into second outer page table 244 bytes/ 212 bytes= 232 pages.

• Size of second outer page table is 232*4bytes= 234 bytes.• Second outer page table size is grater then page size then further divides second

outer page table into third outer page table 234 bytes/ 212 bytes= 222 pages.22----10------10-------10-----12

• Size of third outer page table is 222*4bytes= 224 bytes.• third outer page table size is grater then page size then further divides third outer

page table into forth outer page table 224 bytes/ 212 bytes= 212 pages.12----------10 --------10------------10--------------10--------------12

• Finally page table size equal to page size then exit .

Shared pages

• Reentrant (read only) code pages of a process address space can be shared.

Questions (paging) • Logical address space of 16 pages of 1024 words each, mapped into a physical

memory of 32 frames, find (1 word=2bytes)– Logical address size– Physical address size– Number of bits for p, f and d.

• A system uses 32 bit physical address, 24 bit logical address and size of frame 1 Kbyte. Find– Size of logical address space– Size of physical address space– No. of pages in LAS– No of frames in PAS– Size of page table

• In a computer system logical address space is divided into 256 pages with page size 2048 bytes, size of physical address space 232 bytes. Find – Size of logical address space– No of frame in physical address– Size of page table where are extra bit valid/invalid is also store with each page table entry.

Questions (EAT)

• Suppose to access main memory (search page table or pages) system

required 200ns. If most recent access page and corresponding frames

number are stored in TLB (cache or associative memory). Then time

required to search at cache is 10ns. If 90% is TLB access to search a page

number corresponding to frame number then what will be the EAT.

• On a paged system, associative register hold most active page entries and

the page table stored in the main memory. If references satisfied by the

associative registers take 90ns and reference through the main memory

page table takes 220ns. So what is the effective access time if 60% of all

memory reference find there entries in the associative registers.

Solution 1

• Tmm=200 nsec• TTLB=10 nsec• TLB hit ratio is 80%• TEAT=?• TEAT= (90%)(10+200)+(10%)(10+2*200)

= 0.9*210+0.1*410= 230 nsec

Solution 2

• Tmm=220 nsec• TTLB=90 nsec• TLB Hit ratio is 60%• TEAT=?• TEAT= (60%)(90+220)+(40%)(90+2*220)

= 0.6*310+0.4*440= 398 nsec