package technology trends and lead free challenges c. michael garner, fay hua, nagesh vodrahalli,...

Package Technology Trends and Package Technology Trends and Lead Free ChallengesLead Free Challenges

C. Michael Garner, Fay Hua, Nagesh C. Michael Garner, Fay Hua, Nagesh Vodrahalli, Ashay Dani, Tom Debonis, Vodrahalli, Ashay Dani, Tom Debonis,

Raiyo Aspandiar, and Gary Brist Raiyo Aspandiar, and Gary Brist

Intel CorporationIntel Corporation

22 C. Michael Garner Feb. 13, 2005C. Michael Garner Feb. 13, 2005

AgendaAgenda

• Technology Trends & DriversTechnology Trends & Drivers

• Lead FreeLead Free

• Package Technology TrendsPackage Technology Trends

• Lead Free Technology ChallengesLead Free Technology Challenges

• SummarySummary


Key MessagesKey Messages

• Moore’s Law is alive and wellMoore’s Law is alive and well

• New technologies will require improved New technologies will require improved materialsmaterials

• The lead free transition is underwayThe lead free transition is underway

• Significant technology progress has been Significant technology progress has been mademade

• Lead free challenges remain…Lead free challenges remain…


1000010000

10001000

100100

1010

1010

11

0.10.1

0.010.01

MicronMicron NanometerNanometer

1970 1980 1990 2000 2010 2020

Nominal feature sizeNominal feature size

NanotechnologyNanotechnology

130nm130nm90nm90nm

70nm70nm50nm50nm

Gate WidthGate Width

Technology ScalingTechnology Scaling


Intel’s Transistor Research inIntel’s Transistor Research inDeep Nanotechnology SpaceDeep Nanotechnology Space

65nm process65nm process2005 production2005 production

30nm30nm20nm20nm

45nm process45nm process2007 production2007 production 32nm process32nm process

2009 production 2009 production

15nm15nm

Experimental transistors for future process generationsExperimental transistors for future process generations

22nm process22nm process2011 production 2011 production

10nm10nm

Transistors will be improved Transistors will be improved for productionfor production

Transistors will be improved Transistors will be improved for productionfor production

Source: IntelSource: Intel

Delay vs. Technology GenerationDelay vs. Technology Generation

0

5

10

15

20

25

30

35

40

45

0.65 0.5 0.35 0.25 0.18 0.13 0.1Generation

Del

ay in

ps

Gate Delay

Sum of Delays, Al & SiO2

Sum of Delays, Cu & Low K

Interconnect Delay, Al & SiO2

Interconnect Delay, Cu & Low K

Data From: Bohr, Mark T; “Interconnect Scaling -The Real Limiter to High Performance ULSI”; Proceedings of the 1995, IEEE International Electron Devices Meeting; pp241-242

Gate wi CuGate wi Cu& Low K& Low K

•Interconnect WillDominate Timing

•Cu / Low-k Buys1-2 Generations

•What is Required Beyond 0.1u ?

Gate w Al& SiO2

Gate

6


Source: Intel

Copper lines

Low k dielectric

Transistors

New Materials New Materials for High Performance for High Performance

InterconnectsInterconnects


0

2

4

6

8

10

1.61.822.22.42.62.83

k

GPa

ModulusHardness

Lines do not represent any fitting. They are added tohelp read the data points

Lower K ILD Required for Future TechnologiesLower K ILD Required for Future Technologies

•Mechanical strength dropping dramatically with lower K•Reducing K below 2.4 achieved with pores

•Mechanical strength dropping dramatically with lower K•Reducing K below 2.4 achieved with pores


Lead FreeLead Free


Lead Free TransitionLead Free Transition

• Lead Free Solders require higher assembly temperaturesLead Free Solders require higher assembly temperatures

50 C

100 C

150 C

200 C

250 C

300 C

63Sn/37Pb

52In/48Sn

58Bi/42Sn

91Sn/9Zn

96.5Sn/3.5Ag93.6Sn/4.7Ag/1.7Cu

97In/3Ag

99.3Sn/0.7Cu

90Sn/5Sb

Binary Systems95Sn/3.5Ag/1.5In

77.2Sn/20In/2.8Ag

95.2Sn/3.5Ag/0.8Cu/0.5Sb

91.8Sn/4.8Bi/3.4Ag

Ternary & Quaternary Systems

CastinTM

Indalloy 227

Temperature

All Compositions in wt%

Ag: SilverBi: BismuthCu: CopperIn: Indium

Sb: AntimonySn: TinZn: Zinc

Element Symbols


mPGA socket

Where’s the Lead?Where’s the Lead?

FCPGA CPU Package

FCBGA CPU/Chipset Package

PC Motherboard

Other Packages Containing Lead-Wirebond BGA: Balls-Surface Mount Leaded Pkgs: Leads

Pins

C4 Bumps

Caps

Level 1Interconnects

Exempt if high Pb content

LEGEND

No Lead

Description

Lead

Definition

Actives;Passives

Balls

Level 2Interconnects

C4 Bumps Balls

Exempt if high Pb content

Board Surface

Lead is pervasive through-out an assembled PCB- Replacing this 40+ year old technology must be done cautiously and methodically -

Objectives andBackground


Eliminating the Eliminating the Pb in Intel Pb in Intel ComponentsComponents

Lead

Lead

Flip-Chip Ball Grid Array (FC-BGA)

PGA socketPGA socket

Flip-Chip Pin Grid Array (FC-PGA)

Lead

Lead

Capacitors

Solder Balls

CapacitorsFlip-Chip

Bump

Printed Circuit Board

Lead

Flip-Chip Bump

X

X

X

^RoHS Exempt

^RoHS Exempt

^EU approves temporary exemption for Flip Chip Pb-Sn Solder

**95% of the Pb Content Removed from Flip-chip 95% of the Pb Content Removed from Flip-chip PackagesPackages*Percentage based on weight


Lead Free PackageLead Free Package

• Early issues were package material high Early issues were package material high temperature compatibilitytemperature compatibilityPolymers, adhesives, substratesPolymers, adhesives, substrates

• Lead Free solder mechanical propertiesLead Free solder mechanical properties

• Flip Chip lead free solder challengeFlip Chip lead free solder challenge


Solder Properties

Lower is better

Higher is better

Solders Tm( C )

Modulus(Gpa)

Yield Stress(Mpa)

Ductility (Total elongation, %)

95Pb5Sn 308/312 19 7.8 40%Sn-0.7Cu 227 50 15 40%

Sn-3.5Ag 221 45-55 41 24%Sn-(3.5-4.0)Ag-(0.5-0.7)Cu** 217 52 50 35%Sn-63Pb 183 35 27.2 50%


Intel Lead-free Technology Intel Lead-free Technology ProgressProgress

2001 / 20022001 / 2002 20032003 20042004

Wire bond Leadframe &

BGA

Flip-Chip SLI

Wire bond Chip-scale

Pac

kag

e T

ech

no

log

yP

acka

ge

Tec

hn

olo

gy

TBDTBD

Done

Flip-Chip FLI

SLI: Second Level InterconnectSLI: Second Level Interconnect(package-to-board)(package-to-board)

FLI: First Level InterconnectFLI: First Level Interconnect(die-to-package)(die-to-package)

12/04: EU TAC approved exemption for lead in flip-chip FLI12/04: EU TAC approved exemption for lead in flip-chip FLI

Done

Done


Product & Package TrendsProduct & Package Trends

High Integration PackageHigh Integration Package

ComputingComputing Converged Communication & ComputingConverged Communication & Computing

High Performance PackageHigh Performance Package

Market & Technology are driving new package solutionsMarket & Technology are driving new package solutions


High Performance PackageHigh Performance Package


Flip Chip BGA Package

Pb-free Flip-Chip Package Technology Pb-free Flip-Chip Package Technology ChallengesChallenges

Many Challenges exist to remove the remaining 5% of Lead (Pb)

DiePolyimide

SubstrateSubstrate

Solder Resist

Flip-Chip Bump

Flip Chip Joint Integrity

Silicon Protection

Die Under Fill Process

Silicon Integration


Integrated Assembly ChallengesIntegrated Assembly Challenges

Tin-Lead Solder Profile Reflow @ 183CPeak Temp. = 205 to 220C

Lead Free Solder ProfileReflow @ 217CPeak Temp = 235 to 245C

Time in Minutes

Tem

pera

ture

, Deg

C

At room temperature

The Package shrinksmore than the chip

Intel continues to work with the Industry to develop new technologies Intel continues to work with the Industry to develop new technologies that meet performance and reliability requirements needed to that meet performance and reliability requirements needed to

complete the transition to lead-free (if possible)complete the transition to lead-free (if possible)

HeatingHeating CoolingCooling

At reflow temperature

Silicon Chip

High leadFlip Chip Bump

Package(Copper Laminate)

Typical Assembly Reflow Profile


High Integration PackagesHigh Integration Packages


High Integration PackagesHigh Integration Packages

4 Die Stack with Large Overhang

Substrate1.5mm

Die Attach AdhesiveAdhesion (Low T cure)ShrinkageCure TemperatureModulusTgMoisture AbsorptionThickness

Die Attach AdhesiveAdhesion (Low T cure)ShrinkageCure TemperatureModulusTgMoisture AbsorptionThickness

Molding CompoundCTELocal CTEAdhesionMoisture AbsorptionFuture Thermal ConductivityLow Stress

Molding CompoundCTELocal CTEAdhesionMoisture AbsorptionFuture Thermal ConductivityLow Stress

Technology Trends• More chips per package Thinner chips, adhesive & substrate • Lead Free All materials must be stable with 260C board assembly

Technology Trends• More chips per package Thinner chips, adhesive & substrate • Lead Free All materials must be stable with 260C board assembly


BGA ChallengeBGA Challenge


BGA Solder Ball TrendBGA Solder Ball Trend

• BGA size may accentuate Lead Free mechanical propertiesBGA size may accentuate Lead Free mechanical properties


Laminate Substrates & Printed Laminate Substrates & Printed Wiring Boards Wiring Boards


PerformancePerformance

SignalingSignaling80

88

802

86

803

86

804

86

Pen

tiu

m®

Pro

cess

or

Pen

tiu

m®

II

Pro

cess

or

Pen

tiu

m®

III

Pro

cess

or

Pen

tiu

m®

4P

roce

sso

r

8bit

DR

AM

16b

itD

RA

M

32b

itD

RA

M

32b

itD

RA

M

64b

itD

RA

ME

DO

64b

itS

DR

AM

PC

66/1

0064

bit

SD

RA

M10

0/13

3

64b

it D

DR

333

128b

it D

DR

400

1

10

100

1000

10000

100000

1980 1985 1990 1995 2000 2005 2010Ban

dw

idth

(M

B/s

ec),

Co

re F

req

(M

Hz)

I/F, DRAM BWRDRAM BWCore Freq

Advanced metrologyNon-Cu medium?

~20G

Ts

• Higher frequencies require higher I/O performanceHigher frequencies require higher I/O performance

point-to-point

~10G

Ts

+advanced pkg/IO

2GT

s

+differential

Challenges


• Laminate MaterialLaminate Material Insignificant change in electrical propertiesInsignificant change in electrical properties FR-4 laminate acceptable except for High Layer count (18 Layers or more) and thick FR-4 laminate acceptable except for High Layer count (18 Layers or more) and thick

boards (0.093 inches or more)boards (0.093 inches or more) Via hole integrity as via hole plating has tendency to crack for thicker boards as Z- axis Via hole integrity as via hole plating has tendency to crack for thicker boards as Z- axis

expansion is greater at Peak Reflow Temperatures (PRT) for Lead free then compared to expansion is greater at Peak Reflow Temperatures (PRT) for Lead free then compared to SnPb SnPb

• Large Size boards (12 inches x 15 inches) need support frame during reflowLarge Size boards (12 inches x 15 inches) need support frame during reflow solderingsoldering

Exp

ansi

on in

the

Z A

xis

Temperature

Tg

Z axis

X axisBarrel plating

Crack

PR

T S

nP

b

PR

T S

nA

gC

u

Board Laminate Considerations for Lead Free Board Laminate Considerations for Lead Free SolderingSoldering


Processing & Use Thermal Mechanical Processing & Use Thermal Mechanical ChallengeChallenge

• Via Reliability Concerns Via Reliability Concerns 260C Board Assembly (> 0.07” thick boards)260C Board Assembly (> 0.07” thick boards) Max Operating Temps >130CMax Operating Temps >130C Thermal Cycle StressThermal Cycle Stress

Modulus vs TemperatureModulus vs Temperature CTE vs TemperatureCTE vs Temperature Adhesion vs TemperatureAdhesion vs TemperatureToughnessToughness

Grade AGrade BGrade C

Flexural Strength (Grain) at Elevated TemperatureAbsolute (Thousand PSI)

0

10

20

30

40

50

60

70

80

90

100

25 45 65 85 105 125 145 165 185

Temperature (Celsius)

Grade D

Interconnect: Barrel And Post

Interconnect: Barrel And Post


Challenges SummaryChallenges Summary

• Packages must be compatible with 250-Packages must be compatible with 250-260C assembly260C assembly

• Flip Chip solder requirements are very Flip Chip solder requirements are very complexcomplex

• BGA trend to smaller size may be more BGA trend to smaller size may be more challengingchallenging

• Thick lead free assembly challenging for Thick lead free assembly challenging for thick PCBsthick PCBs


Key MessagesKey Messages

• Moore’s Law is alive and wellMoore’s Law is alive and well

• New technologies will require improved New technologies will require improved materialsmaterials

• The Lead Free transition is underwayThe Lead Free transition is underway

• Significant lead free technology progress Significant lead free technology progress has been madehas been made

• Significant lead free challenges remain…Significant lead free challenges remain…


For further information on Intel's silicon technology and Moore’s Law, please visit the Silicon Showcase

at www.intel.com/research/silicon

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package technology trends and lead free challenges c. michael garner, fay hua, nagesh vodrahalli,...

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