p. bakowski - polytech2go · shift -add multiplier generic booth multiplier sequential divider...
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P.Bakowski 1
VHDLVHDLarithmetic circuits synthesisarithmetic circuits synthesis
P. BakowskiP. Bakowski
P.Bakowski 2
Arithmetic circuits synthesisArithmetic circuits synthesis
half and full adder synthesishalf and full adder synthesis
nn--bit adders/subtractorsbit adders/subtractors
shifters shifters
sequential adders sequential adders
binary multiplication and division binary multiplication and division
shiftshift--add multiplier add multiplier
generic Booth multiplier generic Booth multiplier
sequential divider sequential divider
parallel multiplierparallel multiplier
P.Bakowski 3
Arithmetic circuits synthesisArithmetic circuits synthesis
half and full adder synthesishalf and full adder synthesis
nn--bit adders/subtractorsbit adders/subtractors
shifters shifters
sequential adders sequential adders
binary multiplication and division binary multiplication and division
shiftshift--add multiplier add multiplier
generic Booth multiplier generic Booth multiplier
sequential divider sequential divider
parallel multiplierparallel multiplier
P.Bakowski 4
Arithmetic circuits synthesisArithmetic circuits synthesis
half and full adder synthesishalf and full adder synthesis
nn--bit adders/subtractorsbit adders/subtractors
shifters shifters
sequential adders sequential adders
binary multiplication and division binary multiplication and division
shiftshift--add multiplier add multiplier
generic Booth multiplier generic Booth multiplier
sequential divider sequential divider
parallel multiplierparallel multiplier
P.Bakowski 5
Arithmetic circuits synthesisArithmetic circuits synthesis
half and full adder synthesishalf and full adder synthesis
nn--bit adders/subtractorsbit adders/subtractors
shifters shifters
sequential adders sequential adders
binary multiplication and division binary multiplication and division
shiftshift--add multiplier add multiplier
generic Booth multiplier generic Booth multiplier
sequential divider sequential divider
parallel multiplierparallel multiplier
P.Bakowski 6
Arithmetic circuits synthesisArithmetic circuits synthesis
half and full adder synthesishalf and full adder synthesis
nn--bit adders/subtractorsbit adders/subtractors
shifters shifters
sequential adders sequential adders
binary multiplication and division binary multiplication and division
shiftshift--add multiplier add multiplier
generic Booth multiplier generic Booth multiplier
sequential divider sequential divider
parallel multiplierparallel multiplier
P.Bakowski 7
Arithmetic circuits synthesisArithmetic circuits synthesis
half and full adder synthesishalf and full adder synthesis
nn--bit adders/subtractorsbit adders/subtractors
shifters shifters
sequential adders sequential adders
binary multiplication and division binary multiplication and division
shiftshift--add multiplier add multiplier
generic Booth multiplier generic Booth multiplier
sequential divider sequential divider
parallel multiplierparallel multiplier
P.Bakowski 8
Arithmetic circuits synthesisArithmetic circuits synthesis
half and full adder synthesishalf and full adder synthesis
nn--bit adders/subtractorsbit adders/subtractors
shifters shifters
sequential adders sequential adders
binary multiplication and division binary multiplication and division
shiftshift--add multiplier add multiplier
generic Booth multiplier generic Booth multiplier
sequential divider sequential divider
parallel multiplierparallel multiplier
P.Bakowski 9
Arithmetic circuits synthesisArithmetic circuits synthesis
half and full adder synthesishalf and full adder synthesis
nn--bit adders/subtractorsbit adders/subtractors
shifters shifters
sequential adders sequential adders
binary multiplication and division binary multiplication and division
shiftshift--add multiplier add multiplier
generic Booth multiplier generic Booth multiplier
sequential divider sequential divider
parallel multiplierparallel multiplier
P.Bakowski 10
Arithmetic circuits synthesisArithmetic circuits synthesis
half and full adder synthesishalf and full adder synthesis
nn--bit adders/subtractorsbit adders/subtractors
shifters shifters
sequential adders sequential adders
binary multiplication and division binary multiplication and division
shiftshift--add multiplier add multiplier
generic Booth multiplier generic Booth multiplier
sequential divider sequential divider
parallel multiplierparallel multiplier
P.Bakowski 11
Arithmetic circuits synthesisArithmetic circuits synthesis
The arithmetical circuits are in the heart of all digital The arithmetical circuits are in the heart of all digital
processing systems the processing systems the building blocksbuilding blocks of arithmetical of arithmetical
circuits are: circuits are:
adders/subtractors adders/subtractors
shifters shifters
multipliers/dividers multipliers/dividers
specific operators (e.g. square root) specific operators (e.g. square root)
The arithmetical functions may be implemented through: The arithmetical functions may be implemented through:
combinational circuits combinational circuits
sequential circuits sequential circuits
combinational/sequential circuits combinational/sequential circuits
P.Bakowski 12
Arithmetic circuits synthesisArithmetic circuits synthesis
The arithmetical circuits are in the heart of all digital The arithmetical circuits are in the heart of all digital
processing systems the processing systems the building blocksbuilding blocks of arithmetical of arithmetical
circuits are: circuits are:
adders/subtractors adders/subtractors
shifters shifters
multipliers/dividers multipliers/dividers
specific operators (e.g. square root) specific operators (e.g. square root)
The arithmetical functions may be implemented through: The arithmetical functions may be implemented through:
combinational circuits combinational circuits
sequential circuits sequential circuits
combinational/sequential circuits combinational/sequential circuits
P.Bakowski 13
Arithmetic circuits synthesisArithmetic circuits synthesis
The arithmetical circuits are in the heart of all digital The arithmetical circuits are in the heart of all digital
processing systems the processing systems the building blocksbuilding blocks of arithmetical of arithmetical
circuits are: circuits are:
adders/subtractors adders/subtractors
shifters shifters
multipliers/dividers multipliers/dividers
specific operators (e.g. square root) specific operators (e.g. square root)
The arithmetical functions may be implemented through: The arithmetical functions may be implemented through:
combinational circuits combinational circuits
sequential circuits sequential circuits
combinational/sequential circuits combinational/sequential circuits
P.Bakowski 14
Arithmetic circuits synthesisArithmetic circuits synthesis
The arithmetical circuits are in the heart of all digital The arithmetical circuits are in the heart of all digital
processing systems the processing systems the building blocksbuilding blocks of arithmetical of arithmetical
circuits are: circuits are:
adders/subtractors adders/subtractors
shifters shifters
multipliers/dividers multipliers/dividers
specific operators (e.g. square root) specific operators (e.g. square root)
The arithmetical functions may be implemented through: The arithmetical functions may be implemented through:
combinational circuits combinational circuits
sequential circuits sequential circuits
combinational/sequential circuits combinational/sequential circuits
P.Bakowski 15
Arithmetic circuits synthesisArithmetic circuits synthesis
The arithmetical circuits are in the heart of all digital The arithmetical circuits are in the heart of all digital
processing systems the processing systems the building blocksbuilding blocks of arithmetical of arithmetical
circuits are: circuits are:
adders/subtractors adders/subtractors
shifters shifters
multipliers/dividers multipliers/dividers
specific operators (e.g. square root) specific operators (e.g. square root)
The arithmetical functions may be implemented through: The arithmetical functions may be implemented through:
combinational circuits combinational circuits
sequential circuits sequential circuits
combinational/sequential circuits combinational/sequential circuits
P.Bakowski 16
Arithmetic circuits synthesisArithmetic circuits synthesis
The arithmetical circuits are in the heart of all digital The arithmetical circuits are in the heart of all digital
processing systems the processing systems the building blocksbuilding blocks of arithmetical of arithmetical
circuits are: circuits are:
adders/subtractors adders/subtractors
shifters shifters
multipliers/dividers multipliers/dividers
specific operators (e.g. square root) specific operators (e.g. square root)
The arithmetical functions may be implemented through: The arithmetical functions may be implemented through:
combinational circuits combinational circuits
sequential circuits sequential circuits
combinational/sequential circuits combinational/sequential circuits
P.Bakowski 17
Arithmetic circuits synthesisArithmetic circuits synthesis
The arithmetical circuits are in the heart of all digital The arithmetical circuits are in the heart of all digital
processing systems the processing systems the building blocksbuilding blocks of arithmetical of arithmetical
circuits are: circuits are:
adders/subtractors adders/subtractors
shifters shifters
multipliers/dividers multipliers/dividers
specific operators (e.g. square root) specific operators (e.g. square root)
The arithmetical functions may be implemented through: The arithmetical functions may be implemented through:
combinational circuits combinational circuits
sequential circuits sequential circuits
combinational/sequential circuits combinational/sequential circuits
P.Bakowski 18
Arithmetic circuits synthesisArithmetic circuits synthesis
The arithmetical circuits are in the heart of all digital The arithmetical circuits are in the heart of all digital
processing systems the processing systems the building blocksbuilding blocks of arithmetical of arithmetical
circuits are: circuits are:
adders/subtractors adders/subtractors
shifters shifters
multipliers/dividers multipliers/dividers
specific operators (e.g. square root) specific operators (e.g. square root)
The arithmetical functions may be implemented through: The arithmetical functions may be implemented through:
combinational circuits combinational circuits
sequential circuits sequential circuits
combinational/sequential circuits combinational/sequential circuits
P.Bakowski 19
SingleSingle--bit half adderbit half adder
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
entityentity half_adder half_adder isis
portport (a,b: (a,b: inin std_logic; sum,cout: std_logic; sum,cout: outout std_logic); std_logic);
endend half_adder; half_adder;
architecturearchitecture first of half_adder first of half_adder isis
beginbegin
sum <= a sum <= a xorxor b; b;
cout <= a cout <= a andand b ; b ;
endend first; first;
aa bb
sumsumcoutcout
P.Bakowski 20
SingleSingle--bit half adderbit half adder
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
entityentity half_adder half_adder isis
portport (a,b: (a,b: inin std_logic; sum,cout: std_logic; sum,cout: outout std_logic); std_logic);
endend half_adder; half_adder;
architecturearchitecture first of half_adder first of half_adder isis
beginbegin
sum <= a sum <= a xorxor b; b;
cout <= a cout <= a andand b ; b ;
endend first; first;
aa bb
sumsumcoutcout
P.Bakowski 21
SingleSingle--bit full adderbit full adder
librarylibrary IEEE; IEEE; useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
entityentity full_adder full_adder isis
portport (a,b,cin: (a,b,cin: inin std_logic; sum,cout: std_logic; sum,cout: outout std_logic); std_logic);
endend full_adder; full_adder;
architecturearchitecture first first ofof full_adder full_adder isis
beginbegin
sum <= (a sum <= (a xorxor b) b) xorxor cin; cin;
cout <= (a cout <= (a andand b) b) oror (cin (cin andand a) a) oror (cin (cin andand b) ;b) ;
endend first;first;
aa bb
sumsumcoutcout
cincin
P.Bakowski 22
SingleSingle--bit full adderbit full adder
librarylibrary IEEE; IEEE; useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
entityentity full_adder full_adder isis
portport (a,b,cin: (a,b,cin: inin std_logic; sum,cout: std_logic; sum,cout: outout std_logic); std_logic);
endend full_adder; full_adder;
architecturearchitecture first first ofof full_adder full_adder isis
beginbegin
sum <= (a sum <= (a xorxor b) b) xorxor cin; cin;
cout <= (a cout <= (a andand b) b) oror (cin (cin andand a) a) oror (cin (cin andand b) ;b) ;
endend first;first;
aa bb
sumsumcoutcout
cincin
P.Bakowski 23
SingleSingle--bit full adderbit full adder
full adder simulation waveformfull adder simulation waveform
P.Bakowski 24
Half adders and full adderHalf adders and full adder
architecturearchitecture second second ofof full_adder full_adder isis
componentcomponent half_adder half_adder
portport (a,b: (a,b: inin std_logic; sum,cout: std_logic; sum,cout: outout std_logic); std_logic);
end componentend component; ;
signalsignal sum1,cout1,cout2: std_logic; sum1,cout1,cout2: std_logic;
beginbegin
hadd1: half_adder hadd1: half_adder port mapport map(a,b,sum1,cout1); (a,b,sum1,cout1);
hadd2: half_adder hadd2: half_adder port mapport map(cin,sum1,sum,cout2); (cin,sum1,sum,cout2);
cout <= cout1 cout <= cout1 oror cout2;cout2;
endend second;second;
P.Bakowski 25
Half adders and full adderHalf adders and full adder
architecturearchitecture second second ofof full_adder full_adder isis
componentcomponent half_adder half_adder
portport (a,b: (a,b: inin std_logic; sum,cout: std_logic; sum,cout: outout std_logic); std_logic);
end componentend component; ;
signalsignal sum1,cout1,cout2: std_logic; sum1,cout1,cout2: std_logic;
beginbegin
hadd1: half_adder hadd1: half_adder port mapport map(a,b,sum1,cout1); (a,b,sum1,cout1);
hadd2: half_adder hadd2: half_adder port mapport map(cin,sum1,sum,cout2); (cin,sum1,sum,cout2);
cout <= cout1 cout <= cout1 oror cout2;cout2;
endend second;second;
P.Bakowski 26
NN--bit adders/subtractorsbit adders/subtractors
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall;;
entityentity addsub8 addsub8 isis
portport(sel,cin: (sel,cin: inin std_logic; a,b: std_logic; a,b: inin unsigned(7 unsigned(7 downtodownto 0) 0)
sum: sum: outout unsigned(7 unsigned(7 downtodownto 0); cout: 0); cout: outout std_logic); std_logic);
endend addsub8;addsub8;
P.Bakowski 27
NN--bit adders/subtractorsbit adders/subtractors
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall;;
entityentity addsub8 addsub8 isis
portport(sel,cin: (sel,cin: inin std_logic; a,b: std_logic; a,b: inin unsigned(7 unsigned(7 downtodownto 0) 0)
sum: sum: outout unsigned(7 unsigned(7 downtodownto 0); cout: 0); cout: outout std_logic); std_logic);
endend addsub8;addsub8;
cincincoutcout
selsel
P.Bakowski 28
NN--bit adders/subtractorsbit adders/subtractors
architecturearchitecture first first ofof addsub8 addsub8 isis
constantconstant width_in: integer:=8; width_in: integer:=8;
componentcomponent full_adder full_adder
portport (a,b,cin: (a,b,cin: inin std_logic; sum,cout: std_logic; sum,cout: outout std_logic); std_logic);
end componentend component; ;
signalsignal add_inv: unsigned(width_inadd_inv: unsigned(width_in--1 1 downtodownto 0); 0);
signalsignal cout_tmp: unsigned(width_incout_tmp: unsigned(width_in--1 1 downtodownto 0); 0);
signalsignal add_tmp: unsigned(width_inadd_tmp: unsigned(width_in--1 1 downtodownto 0); 0);
beginbegin invert_sel: invert_sel: processprocess(sel,b) (sel,b)
variablevariable add_inv_var: unsigned(width_inadd_inv_var: unsigned(width_in--1 1 downtodownto 0); 0);
beginbegin
forfor i i inin 0 0 toto width_in width_in looploop add_inv_var := sel add_inv_var := sel xorxor b(i);b(i);
end loopend loop; add_inv <= add_in_var; ; add_inv <= add_in_var;
end processend process;;
P.Bakowski 29
NN--bit adders/subtractorsbit adders/subtractors
architecturearchitecture first first ofof addsub8 addsub8 isis
constantconstant width_in: integer:=8; width_in: integer:=8;
componentcomponent full_adder full_adder
portport (a,b,cin: (a,b,cin: inin std_logic; sum,cout: std_logic; sum,cout: outout std_logic); std_logic);
end componentend component; ;
signalsignal add_inv: unsigned(width_inadd_inv: unsigned(width_in--1 1 downtodownto 0); 0);
signalsignal cout_tmp: unsigned(width_incout_tmp: unsigned(width_in--1 1 downtodownto 0); 0);
signalsignal add_tmp: unsigned(width_inadd_tmp: unsigned(width_in--1 1 downtodownto 0); 0);
beginbegin invert_sel: invert_sel: processprocess(sel,b) (sel,b)
variablevariable add_inv_var: unsigned(width_inadd_inv_var: unsigned(width_in--1 1 downtodownto 0); 0);
beginbegin
forfor i i inin 0 0 toto width_in width_in looploop add_inv_var := sel add_inv_var := sel xorxor b(i);b(i);
end loopend loop; add_inv <= add_in_var; ; add_inv <= add_in_var;
end processend process;;
P.Bakowski 30
NN--bit adders/subtractorsbit adders/subtractors
architecturearchitecture first first ofof addsub8 addsub8 isis
constantconstant width_inwidth_in: integer:=8; : integer:=8;
componentcomponent full_adder full_adder
portport (a,b,cin: (a,b,cin: inin std_logic; sum,cout: std_logic; sum,cout: outout std_logic); std_logic);
end componentend component; ;
signalsignal add_inv: unsigned(add_inv: unsigned(width_inwidth_in--1 1 downtodownto 0); 0);
signalsignal cout_tmp: unsigned(cout_tmp: unsigned(width_inwidth_in--1 1 downtodownto 0); 0);
signalsignal add_tmp: unsigned(add_tmp: unsigned(width_inwidth_in--1 1 downtodownto 0); 0);
beginbegin invert_sel: invert_sel: processprocess(sel,b) (sel,b)
variablevariable add_inv_var: unsigned(width_inadd_inv_var: unsigned(width_in--1 1 downtodownto 0); 0);
beginbegin
forfor i i inin 0 0 toto width_in width_in looploop add_inv_var := sel add_inv_var := sel xorxor b(i);b(i);
end loopend loop; add_inv <= add_in_var; ; add_inv <= add_in_var;
end processend process;;
P.Bakowski 31
NN--bit adders/subtractorsbit adders/subtractors
architecturearchitecture first first ofof addsub8 addsub8 isis
constantconstant width_in: integer:=8; width_in: integer:=8;
componentcomponent full_adder full_adder
portport (a,b,cin: (a,b,cin: inin std_logic; sum,cout: std_logic; sum,cout: outout std_logic); std_logic);
end componentend component; ;
signalsignal add_inv: unsigned(width_inadd_inv: unsigned(width_in--1 1 downtodownto 0); 0);
signalsignal cout_tmp: unsigned(width_incout_tmp: unsigned(width_in--1 1 downtodownto 0); 0);
signalsignal add_tmp: unsigned(width_inadd_tmp: unsigned(width_in--1 1 downtodownto 0); 0);
beginbegin invert_selinvert_sel: : processprocess(sel,b) (sel,b)
variablevariable add_inv_var: unsigned(width_inadd_inv_var: unsigned(width_in--1 1 downtodownto 0); 0);
beginbegin
forfor i i inin 0 0 toto width_in width_in looploop add_inv_var := sel add_inv_var := sel xorxor b(i);b(i);
end loopend loop; add_inv <= add_in_var; ; add_inv <= add_in_var;
end processend process;;
P.Bakowski 32
NN--bit adders/subtractorsbit adders/subtractors
adder_blockadder_block: : block beginblock begin
u_fa_all: u_fa_all: forfor j j inin 0 0 toto width_inwidth_in--1 1 generategenerate
u1: u1: ifif (j=0) (j=0) generategenerate
ifa:full_adder ifa:full_adder port mapport map(a(j), add_inv(j), sel,(a(j), add_inv(j), sel,
add_tmp(j), cout_tmp(j));add_tmp(j), cout_tmp(j));
end generateend generate u1; u1;
u2: u2: ifif (j>0) (j>0) generategenerate
ifa:full_adder ifa:full_adder port mapport map(a(j),add_inv(j), cout_tmp(j(a(j),add_inv(j), cout_tmp(j--1), 1),
add_tmp(j),cout_tmp(j));add_tmp(j),cout_tmp(j));
end generateend generate u2; u2;
cout <= cout_tmp(j); sum <= add_tmp;cout <= cout_tmp(j); sum <= add_tmp;
end blockend block adder_blockadder_block; ;
endend first; first;
P.Bakowski 33
NN--bit adders/subtractorsbit adders/subtractors
adder_block: adder_block: block beginblock begin
u_fa_all: u_fa_all: forfor j j inin 0 0 toto width_inwidth_in--1 1 generategenerate
u1: u1: ifif (j=0) (j=0) generategenerate
ifa:full_adder ifa:full_adder port mapport map(a(j), add_inv(j), sel,(a(j), add_inv(j), sel,
add_tmp(j), cout_tmp(j));add_tmp(j), cout_tmp(j));
end generateend generate u1; u1;
u2: u2: ifif (j>0) (j>0) generategenerate
ifa:full_adder ifa:full_adder port mapport map(a(j),add_inv(j), cout_tmp(j(a(j),add_inv(j), cout_tmp(j--1), 1),
add_tmp(j),cout_tmp(j));add_tmp(j),cout_tmp(j));
end generateend generate u2;u2;
end generateend generate u_fa_all; u_fa_all;
cout <= cout_tmp(j); sum <= add_tmp;cout <= cout_tmp(j); sum <= add_tmp;
end blockend block adder_block; adder_block;
endend first; first;
P.Bakowski 34
NN--bit adders/subtractorsbit adders/subtractors
adder_block: adder_block: block beginblock begin
u_fa_all: u_fa_all: forfor j j inin 0 0 toto width_inwidth_in--1 1 generategenerate
u1: u1: ifif (j=0) (j=0) generategenerate
ifa:full_adder ifa:full_adder port mapport map(a(j), add_inv(j), sel,(a(j), add_inv(j), sel,
add_tmp(j), cout_tmp(j));add_tmp(j), cout_tmp(j));
end generateend generate u1; u1;
u2: u2: ifif (j>0) (j>0) generategenerate
ifa:full_adder ifa:full_adder port mapport map(a(j),add_inv(j), cout_tmp(j(a(j),add_inv(j), cout_tmp(j--1), 1),
add_tmp(j),cout_tmp(j));add_tmp(j),cout_tmp(j));
end generateend generate u2;u2;
end generateend generate u_fa_all; u_fa_all;
cout <= cout_tmp(j); sum <= add_tmp;cout <= cout_tmp(j); sum <= add_tmp;
end blockend block adder_block; adder_block;
endend first; first;
P.Bakowski 35
ShiftersShifters
Shifters may be implemented using: Shifters may be implemented using:
a purely combinational logic a purely combinational logic
combinational shifters are synthetised with multiplexors combinational shifters are synthetised with multiplexors
sequential logicsequential logic
P.Bakowski 36
ShiftersShifters
Shifters may be implemented using: Shifters may be implemented using:
a purely combinational logic a purely combinational logic
combinational shifters are synthetised with multiplexors combinational shifters are synthetised with multiplexors
sequential logicsequential logic
P.Bakowski 37
ShiftersShifters
Shifters may be implemented using: Shifters may be implemented using:
a purely combinational logic a purely combinational logic
combinational shifters are synthetised with multiplexors combinational shifters are synthetised with multiplexors
sequential logicsequential logic
P.Bakowski 38
ShiftersShifters
entityentity cshift4bit cshift4bit isis
portport (sel: (sel: inin integer integer rangerange 0 0 toto 3; a: 3; a: inin unsigned(3 unsigned(3 downtodownto 0); 0);
b: b: outout unsigned(3 unsigned(3 downtodownto 0)); 0));
endend cshift4bit ; cshift4bit ;
architecturearchitecture first first ofof cshift4bit cshift4bit isis
beginbegin processprocess(sel,a) (sel,a)
begin begin
casecase (sel) is (sel) is
whenwhen 0 => b <= "0000"; 0 => b <= "0000";
whenwhen 1 => b <= 1 => b <= shift_leftshift_left(a,1); (a,1);
whenwhen 2 => b <= 2 => b <= shift_rightshift_right(a,1); (a,1);
when otherswhen others => b <= a;=> b <= a;
end caseend case;;
end processend process; ; endend first;first;
P.Bakowski 39
ShiftersShifters
entityentity cshift4 cshift4 isis
portport (sel: (sel: inin integer integer rangerange 0 0 toto 3; a: 3; a: inin unsigned(3 unsigned(3 downtodownto 0); 0);
b: b: outout unsigned(3 unsigned(3 downtodownto 0)); 0));
endend cshift4 ; cshift4 ;
architecturearchitecture first first ofof cshift4 cshift4 isis
beginbegin processprocess(sel,a) (sel,a)
begin begin
casecase (sel) is (sel) is
whenwhen 0 => b <= "0000"; 0 => b <= "0000";
whenwhen 1 => b <= 1 => b <= shift_leftshift_left(a,1); (a,1);
whenwhen 2 => b <= 2 => b <= shift_rightshift_right(a,1); (a,1);
when otherswhen others => b <= a;=> b <= a;
end caseend case;;
end processend process; ; endend first;first;
defined in defined in
IEEE.numeric_stdIEEE.numeric_std
P.Bakowski 40
Barrel shiftersBarrel shifters
entityentity bshift4 bshift4 isis
portport(rot:(rot:inin integer integer rangerange 0 0 toto 3; a:3; a:inin unsigned(3 unsigned(3 downtodownto 0); 0);
b: b: outout unsigned(3 unsigned(3 downtodownto 0)); 0));
endend bshift4 ; bshift4 ; architecturearchitecture first first ofof bshift4 bshift4 isis
beginbegin processprocess(rot,a) (rot,a)
begin begin
casecase (rot) (rot) isis
whenwhen 0 => b <= a; 0 => b <= a;
whenwhen 1 => b <= a 1 => b <= a rolrol 1; 1;
whenwhen 2 => b <= a 2 => b <= a rolrol 2; 2;
whenwhen 3 => b <= a 3 => b <= a rolrol 3; 3;
when otherswhen others => b <= a;=> b <= a;
end caseend case;;
end processend process; ; endend first;first;
P.Bakowski 41
Barrel shiftersBarrel shifters
entityentity bshift4 bshift4 isis
portport(rot:(rot:inin integer integer rangerange 0 0 toto 3; a:3; a:inin unsigned(3 unsigned(3 downtodownto 0); 0);
b: b: outout unsigned(3 unsigned(3 downtodownto 0)); 0));
endend bshift4 ; bshift4 ; architecturearchitecture first first ofof bshift4 bshift4 isis
beginbegin processprocess(rot,a) (rot,a)
begin begin
casecase (rot) (rot) isis
whenwhen 0 => b <= a; 0 => b <= a;
whenwhen 1 => b <= a 1 => b <= a rolrol 1; 1;
whenwhen 2 => b <= a 2 => b <= a rolrol 2; 2;
whenwhen 3 => b <= a 3 => b <= a rolrol 3; 3;
when otherswhen others => b <= a;=> b <= a;
end caseend case;;
end processend process; ; endend first;first;
rolrol operator operator ––
rotate left n rotate left n
bits VHDL'93bits VHDL'93
P.Bakowski 42
Loadable shift registersLoadable shift registers
librarylibrary IEEE; IEEE; useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall; ;
entityentity rshift4 rshift4 isis
portport(clk, rst, ld: (clk, rst, ld: inin std_logic; std_logic;
rot: rot: inin integer integer rangerange 0 0 toto 3; 3;
a: a: inin unsigned(3 unsigned(3 downtodownto 0) ; 0) ;
b: b: outout unsigned(3 unsigned(3 downtodownto 0)); 0));
endend rshift4 ;rshift4 ;
P.Bakowski 43
Loadable shift registersLoadable shift registers
librarylibrary IEEE; IEEE; useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall; ;
entityentity rshift4 rshift4 isis
portport(clk, rst, ld: (clk, rst, ld: inin std_logic; std_logic;
rot: rot: inin integer integer rangerange 0 0 toto 3; 3;
a: a: inin unsigned(3 unsigned(3 downtodownto 0) ; 0) ;
b: b: outout unsigned(3 unsigned(3 downtodownto 0)); 0));
endend rshift4 ;rshift4 ;
ldld
clkclk
rotrot
rstrst
aa
bb
P.Bakowski 44
Loadable shift registersLoadable shift registers
architecturearchitecture first first ofof rshift4 rshift4 isis
beginbegin processprocess (clk, rst) (clk, rst)
variablevariable sr: unsigned(3 sr: unsigned(3 downtodownto 0) 0)
begin begin
ifif (rst='1') (rst='1') thenthen sr :=(sr :=(othersothers =>'0'); =>'0');
elsifelsif rising_edgerising_edge(clk) (clk) thenthen
ifif (ld ='1') (ld ='1') thenthen sr := a; sr := a; else else
casecase (rot) (rot) isis
whenwhen 0 => sr := sr; 0 => sr := sr; whenwhen 1 => sr := sr 1 => sr := sr rolrol 1; 1;
whenwhen 2 => sr := sr 2 => sr := sr rolrol 2; 2; whenwhen 3 => sr := sr 3 => sr := sr rolrol 3; 3;
whenwhen othersothers => sr := sr;=> sr := sr;
end caseend case; ;
end ifend if; ; end ifend if; b <= sr; ; b <= sr;
end processend process; ; endend first;first;
P.Bakowski 45
Loadable shift registersLoadable shift registers
loadable shift register waveformloadable shift register waveform
P.Bakowski 46
Sequential addersSequential adders
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall; ;
entityentity seqadd seqadd isis
portport(clk, rst: (clk, rst: inin std_logic; std_logic;
cins: cins: inin std_logic; std_logic;
as, bs: as, bs: inin unsigned(7 unsigned(7 downtodownto 0); 0);
sum, cout: sum, cout: outout std_logic;); std_logic;);
endend seqadd;seqadd;
P.Bakowski 47
Sequential addersSequential adders
architecturearchitecture first first ofof seqadd seqadd isis
signalsignal ra, rb: unsigned(7 ra, rb: unsigned(7 downtodownto 0); 0);
signalsignal nc: std_logic; nc: std_logic;
componentcomponent full_adder full_adder
portport(a, b, cin: (a, b, cin: inin std_logic; sum, cout: std_logic; sum, cout: outout std_logic); std_logic);
end componentend component; ;
beginbegin stepstep: : processprocess(rst, clk) (rst, clk)
begin begin
ifif rising_edgerising_edge(clk) (clk) thenthen
ifif rst='1' rst='1' thenthen ra <= as; rb <= bs; nc<= cins; ra <= as; rb <= bs; nc<= cins;
elseelse ra <= ra <= rotate_rightrotate_right(ra,1); rb <= (ra,1); rb <= rotate_rightrotate_right(rb,1);(rb,1);
nc <= nc; nc <= nc; end ifend if; ;
end ifend if; ;
end processend process stepstep;;
P.Bakowski 48
Sequential addersSequential adders
add_i: full_adder add_i: full_adder ---- instantiation of the full_adder instantiation of the full_adder
port mapport map (ra(0),rb(0),nc,sum,cout);(ra(0),rb(0),nc,sum,cout);
endend first;first;asas bsbs
ra(0)ra(0)
rbrb
ncnc
sumsum
rstrst
clkclk
cinscins
coutcout
rb(0)rb(0)
rara
P.Bakowski 49
Sequential addersSequential adders
add_i: full_adder add_i: full_adder ---- instantiation of the full_adder instantiation of the full_adder
port mapport map (ra(0),rb(0),nc,sum,cout);(ra(0),rb(0),nc,sum,cout);
endend first;first;
add_iadd_i
asas bsbs
ra(0)ra(0)
rbrb
ncnc
sumsum
rstrst
clkclk
cinscins
coutcout
rb(0)rb(0)
rara
P.Bakowski 50
Binary multiplicationBinary multiplication
...15 ...15
...10 ...10
----------
....0 ....0
..15. ..15.
----------
..150..150
....1111....1111 multiplicand multiplicand
....1010....1010 multiplier multiplier
----------------
....0000....0000 partial product 1 partial product 1
...1111....1111. partial product 2 partial product 2
..0000....0000.. partial product 3 partial product 3
.1111....1111... partial product 4 partial product 4
----------------
1001011010010110 final productfinal product
Decimal multiplicationDecimal multiplicationBinary multiplicationBinary multiplication
Basic shift and add algorithmBasic shift and add algorithm
P.Bakowski 51
Binary multiplicationBinary multiplication
...15 ...15
...10 ...10
----------
....0 ....0
..15. ..15.
----------
..150..150
........11111111 multiplicand multiplicand
....101....10100 multiplier multiplier
----------------
........00000000 partial product 1partial product 1
...1111....1111. partial product 2 partial product 2
..0000....0000.. partial product 3 partial product 3
.1111....1111... partial product 4 partial product 4
----------------
0000000000000000 final productfinal product
Decimal multiplicationDecimal multiplicationBinary multiplicationBinary multiplication
Basic shift and add algorithmBasic shift and add algorithm
P.Bakowski 52
Binary multiplicationBinary multiplication
...15 ...15
...10 ...10
----------
....0 ....0
..15. ..15.
----------
..150..150
........11111111 multiplicand multiplicand
....10....101100 multiplier multiplier
----------------
....0000....0000 partial product 1 partial product 1
......11111111.. partial product 2partial product 2
..0000....0000.. partial product 3 partial product 3
.1111....1111... partial product 4 partial product 4
----------------
0001111000011110 final productfinal product
Decimal multiplicationDecimal multiplicationBinary multiplicationBinary multiplication
Basic shift and add algorithmBasic shift and add algorithm
P.Bakowski 53
Binary multiplicationBinary multiplication
...15 ...15
...10 ...10
----------
....0 ....0
..15. ..15.
----------
..150..150
........11111111 multiplicand multiplicand
....1....1001010 multiplier multiplier
----------------
....0000....0000 partial product 1 partial product 1
...1111....1111. partial product 2 partial product 2
....00000000.... partial product 3partial product 3
.1111....1111... partial product 4 partial product 4
----------------
0001111000011110 final productfinal product
Decimal multiplicationDecimal multiplicationBinary multiplicationBinary multiplication
Basic shift and add algorithmBasic shift and add algorithm
P.Bakowski 54
Binary multiplicationBinary multiplication
...15 ...15
...10 ...10
----------
....0 ....0
..15. ..15.
----------
..150..150
........11111111 multiplicand multiplicand
........11010010 multiplier multiplier
----------------
....0000....0000 partial product 1 partial product 1
...1111....1111. partial product 2 partial product 2
..0000....0000.. partial product 3 partial product 3
..11111111...... partial product 4partial product 4
----------------
1001011010010110 final productfinal product
Decimal multiplicationDecimal multiplicationBinary multiplicationBinary multiplication
Basic shift and add algorithmBasic shift and add algorithm
P.Bakowski 55
Multiplication Multiplication –– 2nd complement2nd complement
..5 ..5
..--6 6
------
--3030
....0101....0101
1111110101111010
----------------
00000000 00000000
0000101. 0000101.
000000.. 000000..
00101... 00101...
0101.... 0101....
101..... 101.....
01...... 01......
1....... 1.......
----------------
1111000101100010
--2277
((--128)128)
(122)(122)2266+2+255+2+244+2+233+2+211
P.Bakowski 56
Multiplication Multiplication –– 2nd complement2nd complement
..5 ..5
..--6 6
------
--3030
....0101....0101
1111110101111010
----------------
00000000 00000000
0000101. 0000101.
000000.. 000000..
00101... 00101...
0101.... 0101....
101..... 101.....
01...... 01......
1....... 1.......
----------------
1111000101100010
--2277
((--128)128)
(122)(122)2266+2+255+2+244+2+233+2+211
P.Bakowski 57
Multiplication Multiplication –– 2nd complement2nd complement
..5 ..5
..--6 6
------
--3030
....0101....0101
1111110101111010
----------------
00000000 00000000
0000101. 0000101.
000000.. 000000..
00101... 00101...
0101.... 0101....
101..... 101.....
01...... 01......
1....... 1.......
----------------
1111000101100010
--2277
((--128)128)
(122)(122)2266+2+255+2+244+2+233+2+211
--2277
((--128)128)
2266+2+255+2+211 (98)(98)
P.Bakowski 58
Multiplication Multiplication –– 2nd complement2nd complement
..5 ..5
..--6 6
------
--3030
....0101....0101
1111110101111010
----------------
00000000 00000000
0000101. 0000101.
000000.. 000000..
00101... 00101...
0101.... 0101....
101..... 101.....
01...... 01......
1....... 1.......
----------------
1111000101100010
basic shift and add basic shift and add
algorithmalgorithm
P.Bakowski 59
Binary divisionBinary division
Binary division algorithm generates the quotient digits Binary division algorithm generates the quotient digits
(0 or 1) by using a simple (0 or 1) by using a simple comparatorcomparator::
the most significant bits of the dividend are the most significant bits of the dividend are
compared with the divisor compared with the divisor
if the divisor is greater than the compared part ofif the divisor is greater than the compared part of
the dividend, the smallest quotient digit is '0' the dividend, the smallest quotient digit is '0'
otherwise it is '1' otherwise it is '1' --> and partial remainder is> and partial remainder is
produced produced
P.Bakowski 60
Binary divisionBinary division
Binary division algorithm generates the quotient digits Binary division algorithm generates the quotient digits
(0 or 1) by using a simple comparator:(0 or 1) by using a simple comparator:
the most significant bits of the dividend are the most significant bits of the dividend are
comparedcompared with the divisor with the divisor
if the divisor is greater than the compared part of if the divisor is greater than the compared part of
the dividend, the smallest quotient digit is '0' the dividend, the smallest quotient digit is '0'
otherwise it is '1' otherwise it is '1' --> and partial remainder is > and partial remainder is
produced produced
P.Bakowski 61
Binary divisionBinary division
Binary division algorithm generates the quotient digits Binary division algorithm generates the quotient digits
(0 or 1) by using a simple comparator:(0 or 1) by using a simple comparator:
the most significant bits of the dividend arethe most significant bits of the dividend are
compared with the divisor compared with the divisor
if the divisor is greater than the compared part of if the divisor is greater than the compared part of
the dividend, the the dividend, the smallest quotient digitsmallest quotient digit is '0' is '0'
otherwise it is '1' otherwise it is '1' --> and partial remainder is> and partial remainder is
produced produced
P.Bakowski 62
Binary divisionBinary division
Next, the Next, the new partial remainder is producednew partial remainder is produced by the by the
subtraction of the divisor from the current partial subtraction of the divisor from the current partial
remainder: remainder:
the divisor is shifted one place to the right andthe divisor is shifted one place to the right and
compared with the partial remainder compared with the partial remainder
the process continues down to the last bit of the the process continues down to the last bit of the
dividend dividend
the last partial remainder is the final remainderthe last partial remainder is the final remainder
P.Bakowski 63
Binary divisionBinary division
Next, the Next, the new partial remainder is producednew partial remainder is produced by the by the
subtraction of the divisor from the current partial subtraction of the divisor from the current partial
remainder: remainder:
the the divisor is shifted one placedivisor is shifted one place to the right andto the right and
compared with the partial remainder compared with the partial remainder
the process continues down to the last bit of the the process continues down to the last bit of the
dividend dividend
the last partial remainder is the final remainderthe last partial remainder is the final remainder
P.Bakowski 64
Binary divisionBinary division
Next, the Next, the new partial remainder is producednew partial remainder is produced by the by the
subtraction of the divisor from the current partial subtraction of the divisor from the current partial
remainder: remainder:
the divisor is shifted one place to the right andthe divisor is shifted one place to the right and
compared with the partial remainder compared with the partial remainder
the process continues down to the the process continues down to the last bit of the last bit of the
dividend dividend
the last partial remainder is the final remainderthe last partial remainder is the final remainder
P.Bakowski 65
Binary divisionBinary division
Next, the Next, the new partial remainder is producednew partial remainder is produced by the by the
subtraction of the divisor from the current partial subtraction of the divisor from the current partial
remainder: remainder:
the divisor is shifted one place to the right andthe divisor is shifted one place to the right and
compared with the partial remainder compared with the partial remainder
the process continues down to the the process continues down to the last bit of the last bit of the
dividend dividend
the last partial remainder is the the last partial remainder is the final remainderfinal remainder
P.Bakowski 66
Binary division Binary division -- exampleexample
1010000101 1010000101
10010 10010
----------
000100010 000100010
....10010 ....10010
--------------------
....100001 ....100001
.....10010 .....10010
--------------------
.....01111
..
..
..
partial remainderpartial remainder
..
..
partial remainderpartial remainder
final remainderfinal remainder
quotient: quotient: ....100001
dividend: dividend: 1010000101
divisor: divisor: 10010
P.Bakowski 67
Binary division Binary division -- exampleexample
1010000101 1010000101
1001010010
----------
000100010000100010
....10010 ....10010
--------------------
....100001 ....100001
.....10010 .....10010
--------------------
.....01111
..
..
..
partial remainderpartial remainder
..
..
partial remainderpartial remainder
final remainderfinal remainder
quotient: quotient: ....100001
dividend: dividend: 1010000101
divisor: divisor: 10010
P.Bakowski 68
Binary division Binary division -- exampleexample
1010000101 1010000101
1001010010
----------
000100010000100010
........1001010010
--------------------
........100001100001
.....10010 .....10010
--------------------
.....01111
..
..
..
partial remainderpartial remainder
..
..
partial remainderpartial remainder
final remainderfinal remainder
quotient: quotient: ....100001
dividend: dividend: 1010000101
divisor: divisor: 10010
P.Bakowski 69
Binary division Binary division -- exampleexample
1010000101 1010000101
1001010010
----------
000100010000100010
........1001010010
--------------------
........100001100001
..........1001010010
--------------------
.....01111
..
..
..
partial remainderpartial remainder
..
..
partial remainderpartial remainder
final remainderfinal remainder
quotient: quotient: ....100001
dividend: dividend: 1010000101
divisor: divisor: 10010
P.Bakowski 70
Binary multiplier Binary multiplier -- exampleexample
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall; ;
entityentity mul8by8 mul8by8 isis
portport (a,b: (a,b: inin unsigned(7 unsigned(7 downtodownto 0); 0);
prod: prod: outout unsigned(15 unsigned(15 downtodownto 0)); 0));
endend mul8by8;mul8by8;
prodprod
aa bb
P.Bakowski 71
Binary multiplier Binary multiplier -- exampleexample
architecturearchitecture first first ofof mul8by8 mul8by8
beginbegin processprocess(a,b) (a,b)
variablevariable sum: unsigned(16 sum: unsigned(16 downtodownto 0); 0);
beginbegin
sum:= (others=>'0'); sum:= (others=>'0');
sh_add: sh_add: forfor i i inin 7 7 downtodownto 0 0 looploop
ifif b(i) ='1' b(i) ='1' thenthen ---- compute partial product compute partial product
sum:= sum + ("000000000" sum:= sum + ("000000000" && a);a);
end ifend if; ;
um:= sum(15 um:= sum(15 downtodownto 0) 0) && '0';'0';
end loopend loop sh_add; sh_add;
prod <= sum(16 prod <= sum(16 downtodownto 1);1);
end processend process;;
endend first; first;
P.Bakowski 72
Binary multiplier Binary multiplier -- exampleexample
architecturearchitecture first first ofof mul8by8 mul8by8
beginbegin processprocess(a,b) (a,b)
variablevariable sum: unsigned(16 sum: unsigned(16 downtodownto 0); 0);
beginbegin
sum:= (others=>'0'); sum:= (others=>'0');
sh_add: sh_add: forfor i i inin 7 7 downtodownto 0 0 looploop
ifif b(i) ='1' b(i) ='1' thenthen ---- compute partial product compute partial product
sum:= sum + ("000000000" sum:= sum + ("000000000" && a);a);
end ifend if; ;
um:= sum(15 um:= sum(15 downtodownto 0) 0) && '0';'0';
end loopend loop sh_add; sh_add;
prod <= sum(16 prod <= sum(16 downtodownto 1);1);
end processend process;;
endend first; first;
P.Bakowski 73
Binary multiplier Binary multiplier -- exampleexample
architecturearchitecture first first ofof mul8by8 mul8by8
beginbegin processprocess(a,b) (a,b)
variablevariable sum: unsigned(16 sum: unsigned(16 downtodownto 0); 0);
beginbegin
sum:= (others=>'0'); sum:= (others=>'0');
sh_add: sh_add: forfor i i inin 7 7 downtodownto 0 0 looploop
ifif b(i) ='1' b(i) ='1' thenthen ---- compute partial product compute partial product
sum:= sum + ("000000000" sum:= sum + ("000000000" && a);a);
end ifend if; ;
sum:= sum(15 sum:= sum(15 downtodownto 0) 0) && '0';'0';
end loopend loop sh_add; sh_add;
prod <= sum(16 prod <= sum(16 downtodownto 1);1);
end processend process;;
endend first; first;
P.Bakowski 74
Binary multiplier Binary multiplier -- exampleexample
architecturearchitecture first first ofof mul8by8 mul8by8
beginbegin processprocess(a,b) (a,b)
variablevariable sum: unsigned(16 sum: unsigned(16 downtodownto 0); 0);
beginbegin
sum:= (others=>'0'); sum:= (others=>'0');
sh_add: sh_add: forfor i i inin 7 7 downtodownto 0 0 looploop
ifif b(i) ='1' b(i) ='1' thenthen ---- compute partial productcompute partial product
sum:= sum + ("000000000" sum:= sum + ("000000000" && a);a);
end ifend if; ;
sum:= sum(15 sum:= sum(15 downtodownto 0) 0) && '0';'0';
end loopend loop sh_add; sh_add;
prod <= sum(16 prod <= sum(16 downtodownto 1);1);
end processend process;;
endend first; first;
P.Bakowski 75
Binary multiplier Binary multiplier -- exampleexample
architecturearchitecture first first ofof mul8by8 mul8by8
beginbegin processprocess(a,b) (a,b)
variablevariable sum: unsigned(16 sum: unsigned(16 downtodownto 0); 0);
beginbegin
sum:= (others=>'0'); sum:= (others=>'0');
sh_add: sh_add: forfor i i inin 7 7 downtodownto 0 0 looploop
ifif b(i) ='1' b(i) ='1' thenthen ---- compute partial product compute partial product
sum:= sum + ("000000000" sum:= sum + ("000000000" && a);a);
end ifend if; ;
sum:= sum(15 sum:= sum(15 downtodownto 0) 0) && '0';'0';
end loopend loop sh_add; sh_add;
prod <= sum(16 prod <= sum(16 downtodownto 1);1);
end processend process;;
endend first; first;
11--bit shift leftbit shift left
P.Bakowski 76
Binary multiplier Binary multiplier -- exampleexample
architecturearchitecture first first ofof mul8by8 mul8by8
beginbegin processprocess(a,b) (a,b)
variablevariable sum: unsigned(16 sum: unsigned(16 downtodownto 0); 0);
beginbegin
sum:= (others=>'0'); sum:= (others=>'0');
sh_add: sh_add: forfor i i inin 7 7 downtodownto 0 0 looploop
ifif b(i) ='1' b(i) ='1' thenthen ---- compute partial product compute partial product
sum:= sum + ("000000000" sum:= sum + ("000000000" && a);a);
end ifend if; ;
sum:= sum(15 sum:= sum(15 downtodownto 0) 0) && '0';'0';
end loopend loop sh_add; sh_add;
prod <= sum(16 prod <= sum(16 downtodownto 1);1);
end processend process;;
endend first; first; send out the productsend out the product
P.Bakowski 77
Binary multiplier Binary multiplier -- exampleexample
simple shift and add multiplier waveform simple shift and add multiplier waveform
(in decimal: 15*15=225)(in decimal: 15*15=225)
P.Bakowski 78
Generic Booth multiplier Generic Booth multiplier
aa qq
bb
11 00
a term a term
aq aq –– final accumulatorfinal accumulator
b termb term
P.Bakowski 79
Generic Booth multiplier Generic Booth multiplier
aa qq
bb
11 00
a term a term
aq aq –– final accumulatorfinal accumulator
b termb term
aq(1) and aq(1) and
aq(0) aq(0) ––
positions to positions to
be testedbe tested
P.Bakowski 80
Generic Booth multiplier Generic Booth multiplier
aa qq
bb
11 00
01 => aq + b 01 => aq + b
10 => aq 10 => aq -- bb+ / + / --
depending on the aq(1) and depending on the aq(1) and
aq(0) values the b term is aq(0) values the b term is
added or subtractedadded or subtracted
P.Bakowski 81
Generic Booth multiplier Generic Booth multiplier
aa qq
11 00
01 => aq + b 01 => aq + b
10 => aq 10 => aq -- bb
sar sar –– shift arithmetically rightshift arithmetically rightbb
+ / + / --
P.Bakowski 82
Generic Booth multiplier Generic Booth multiplier
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall; ;
entityentity gen_mul_booth gen_mul_booth isis
genericgeneric(w:positive:=8); (w:positive:=8);
portport(a,b:(a,b:inin unsigned(wunsigned(w--1 1 downtodownto 0); 0);
prod :prod :outout unsigned( 2*wunsigned( 2*w--1 1 downtodownto 0)); 0));
endend gen_mul_booth;gen_mul_booth;
prodprod
aa bb
P.Bakowski 83
Generic Booth multiplier Generic Booth multiplier
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall; ;
entityentity gen_mul_booth gen_mul_booth isis
genericgeneric((ww:positive:=8); :positive:=8);
portport(a,b:(a,b:inin unsigned(unsigned(ww--11 downtodownto 0); 0);
prod :prod :outout unsigned( 2*wunsigned( 2*w--1 1 downtodownto 0)); 0));
endend gen_mul_booth;gen_mul_booth;
prodprod
aa bb
generic parameter generic parameter
widthwidth
P.Bakowski 84
Generic Booth multiplier Generic Booth multiplier
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall; ;
entityentity gen_mul_booth gen_mul_booth isis
genericgeneric((ww:positive:=8); :positive:=8);
portport(a,b:(a,b:inin unsigned(unsigned(ww--11 downtodownto 0); 0);
prod :prod :outout unsigned( unsigned( 2*w2*w--11 downtodownto 0)); 0));
endend gen_mul_booth;gen_mul_booth;
prodprod
aa bb
generic parameter generic parameter
widthwidth
P.Bakowski 85
Generic Booth multiplier Generic Booth multiplier
architecturearchitecture first first ofof gen_mul_booth gen_mul_booth isis
beginbegin
processprocess(a,b) (a,b)
variablevariable aq: unsigned(2*w aq: unsigned(2*w downtodownto 0); 0);
beginbegin
aq(2*w aq(2*w downtodownto 0):=(0):=(othersothers=>'0'); =>'0');
aq(w aq(w downtodownto 1):= a; 1):= a;
sa: sa: forfor i i inin ww--1 1 downtodownto 0 0 looploop
ifif (aq(1)='0' (aq(1)='0' andand aq(0)='1') aq(0)='1') thenthen
aq(2*w aq(2*w downtodownto w+1):= aq(2*w w+1):= aq(2*w downtodownto w+1)+b;w+1)+b;
elsifelsif (aq(1)='1' (aq(1)='1' andand aq(0)='0') aq(0)='0') thenthen
aq(2*waq(2*w--1 1 downtodownto w+1):= aq(2*w w+1):= aq(2*w downtodownto w+1)+w+1)+notnot b+1;b+1;
end ifend if;;
… …
initialisationinitialisation
P.Bakowski 86
Generic Booth multiplier Generic Booth multiplier
architecturearchitecture first first ofof gen_mul_booth gen_mul_booth isis
beginbegin
processprocess(a,b) (a,b)
variablevariable aq: unsigned(2*w aq: unsigned(2*w downtodownto 0); 0);
beginbegin
aq(2*w aq(2*w downtodownto 0):=(0):=(othersothers=>'0'); =>'0');
aq(w aq(w downtodownto 1):= a; 1):= a;
sa: sa: forfor i i inin ww--1 1 downtodownto 0 0 looploop
ifif (aq(1)='0' (aq(1)='0' andand aq(0)='1') aq(0)='1') thenthen
aq(2*w aq(2*w downtodownto w+1):= aq(2*w w+1):= aq(2*w downtodownto w+1)+b;w+1)+b;
elsifelsif (aq(1)='1' (aq(1)='1' andand aq(0)='0') aq(0)='0') thenthen
aq(2*waq(2*w--1 1 downtodownto w+1):= aq(2*w w+1):= aq(2*w downtodownto w+1)+w+1)+notnot b+1;b+1;
end ifend if;;
… …
test of a(1) and test of a(1) and
a(0)a(0)
P.Bakowski 87
Generic Booth multiplier Generic Booth multiplier
architecturearchitecture first first ofof gen_mul_booth gen_mul_booth isis
beginbegin
processprocess(a,b) (a,b)
variablevariable aq: unsigned(2*w aq: unsigned(2*w downtodownto 0); 0);
beginbegin
aq(2*w aq(2*w downtodownto 0):=(0):=(othersothers=>'0'); =>'0');
aq(w aq(w downtodownto 1):= a; 1):= a;
sa: sa: forfor i i inin ww--1 1 downtodownto 0 0 looploop
ifif (aq(1)='0' (aq(1)='0' andand aq(0)='1') aq(0)='1') thenthen
aq(2*w aq(2*w downtodownto w+1):= aq(2*w w+1):= aq(2*w downtodownto w+1)+b;w+1)+b;
elsifelsif (aq(1)='1' (aq(1)='1' andand aq(0)='0') aq(0)='0') thenthen
aq(2*waq(2*w--1 1 downtodownto w+1):= aq(2*w w+1):= aq(2*w downtodownto w+1)+w+1)+notnot b+1;b+1;
end ifend if;;
… …
addition if addition if
aq(1)=‘0’ and aq(1)=‘0’ and
aq(0)=‘1’aq(0)=‘1’
P.Bakowski 88
Generic Booth multiplier Generic Booth multiplier
architecturearchitecture first first ofof gen_mul_booth gen_mul_booth isis
beginbegin
processprocess(a,b) (a,b)
variablevariable aq: unsigned(2*w aq: unsigned(2*w downtodownto 0); 0);
beginbegin
aq(2*w aq(2*w downtodownto 0):=(0):=(othersothers=>'0'); =>'0');
aq(w aq(w downtodownto 1):= a; 1):= a;
sa: sa: forfor i i inin ww--1 1 downtodownto 0 0 looploop
ifif (aq(1)='0' (aq(1)='0' andand aq(0)='1') aq(0)='1') thenthen
aq(2*w aq(2*w downtodownto w+1):= aq(2*w w+1):= aq(2*w downtodownto w+1)+b;w+1)+b;
elsifelsif (aq(1)='1' (aq(1)='1' andand aq(0)='0') aq(0)='0') thenthen
aq(2*waq(2*w--1 1 downtodownto w+1):= aq(2*w w+1):= aq(2*w downtodownto w+1)+w+1)+notnot b+1;b+1;
end ifend if;;
… …
subtraction if subtraction if
aq(1)=‘1’ and aq(1)=‘1’ and
aq(0)=‘0’aq(0)=‘0’
P.Bakowski 89
Generic Booth multiplier Generic Booth multiplier
sa: sa: forfor i i inin ww--1 1 downtodownto 0 0 looploop
ifif (aq(1)='0' (aq(1)='0' andand aq(0)='1') aq(0)='1') thenthen
aq(2*w aq(2*w downtodownto w+1):= aq(2*w w+1):= aq(2*w downtodownto w+1)+b;w+1)+b;
elsifelsif (aq(1)='1' (aq(1)='1' andand aq(0)='0') aq(0)='0') thenthen
aq(2*waq(2*w--1 1 downtodownto w+1):= aq(2*w w+1):= aq(2*w downtodownto w+1)+w+1)+notnot b+1;b+1;
end ifend if;;
aq(2*w aq(2*w downtodownto 0 ):= aq(2*w 0 ):= aq(2*w downtodownto 1); 1);
aq(2*w) := aq(2*waq(2*w) := aq(2*w--1); 1);
end loopend loop sa;sa;
prod <= aq(2*w prod <= aq(2*w downtodownto 1); 1);
end processend process ; ;
endend first; first; shift right shift right
arithmeticallyarithmetically
P.Bakowski 90
Generic Booth multiplier Generic Booth multiplier
sa: sa: forfor i i inin ww--1 1 downtodownto 0 0 looploop
ifif (aq(1)='0' (aq(1)='0' andand aq(0)='1') aq(0)='1') thenthen
aq(2*w aq(2*w downtodownto w+1):= aq(2*w w+1):= aq(2*w downtodownto w+1)+b;w+1)+b;
elsifelsif (aq(1)='1' (aq(1)='1' andand aq(0)='0') aq(0)='0') thenthen
aq(2*waq(2*w--1 1 downtodownto w+1):= aq(2*w w+1):= aq(2*w downtodownto w+1)+w+1)+notnot b+1;b+1;
end ifend if;;
aq(2*w aq(2*w downtodownto 0 ):= aq(2*w 0 ):= aq(2*w downtodownto 1); 1);
aq(2*w) := aq(2*waq(2*w) := aq(2*w--1); 1);
end loopend loop sa;sa;
prod <= aq(2*w prod <= aq(2*w downtodownto 1); 1);
end processend process ; ;
endend first; first;
output of the final output of the final
resultresult
P.Bakowski 91
Generic Booth multiplier Generic Booth multiplier
Booth multiplier: multiplication of 1*1 and (Booth multiplier: multiplication of 1*1 and (--1)*(1)*(--1)1)
--1 * 1 * --11
P.Bakowski 92
Generic divider for unsigned integers Generic divider for unsigned integers
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall; ;
entityentity seq_div seq_div isis
genericgeneric(w: positive:=4); (w: positive:=4);
---- dividend (a); divisor (b) dividend (a); divisor (b)
portport( ( a:ina:in unsigned(2*wunsigned(2*w--1 1 downtodownto 0); 0);
b:b:inin unsigned(wunsigned(w--1 1 downtodownto 0); 0);
quot :quot :outout unsigned(wunsigned(w--1 1 downtodownto 0)); 0));
endend seq_div;seq_div;
P.Bakowski 93
Generic divider for unsigned integers Generic divider for unsigned integers architecturearchitecture first first ofof seq_div seq_div isis
beginbegin processprocess(a,b) (a,b)
variablevariable aq: unsigned(2*w aq: unsigned(2*w downtodownto 0); 0);
variablevariable tb: unsigned(w tb: unsigned(w downtodownto 0);0);
beginbegin
aq(2*waq(2*w--1 1 downtodownto 0):=a(2*w0):=a(2*w--1 1 downtodownto 0); aq(2*w):='0';0); aq(2*w):='0';
tb(w):='0'; tb(wtb(w):='0'; tb(w--1 1 downtodownto 0):=b(w0):=b(w--1 1 downtodownto 0);0);
sas: sas: forfor i i inin 0 0 toto w w looploop
aq(2*w aq(2*w downtodownto w):= aq(2*w w):= aq(2*w downtodownto w) + w) + notnot tb +1; tb +1;
ifif (aq(2*w)='1') (aq(2*w)='1') thenthen
aq(2*w aq(2*w downtodownto w):= aq(2*w w):= aq(2*w downtodownto w) + tb; aq(0):='0'; w) + tb; aq(0):='0';
elseelse aq(0):='1'; aq(0):='1'; end ifend if; ;
aq(2*w aq(2*w downtodownto 1):= aq(2*w1):= aq(2*w--1 1 downtodownto 0); aq(0):= '0'; 0); aq(0):= '0';
end loopend loop sas; quot <= aq(w sas; quot <= aq(w downtodownto 1); 1);
end processend process ; ; endend first;first;
P.Bakowski 94
Generic divider for unsigned integers Generic divider for unsigned integers architecturearchitecture first first ofof seq_div seq_div isis
beginbegin processprocess(a,b) (a,b)
variablevariable aq: unsigned(2*w aq: unsigned(2*w downtodownto 0); 0);
variablevariable tb: unsigned(w tb: unsigned(w downtodownto 0);0);
beginbegin
aq(2*waq(2*w--1 1 downtodownto 0):=a(2*w0):=a(2*w--1 1 downtodownto 0); aq(2*w):='0';0); aq(2*w):='0';
tb(w):='0'; tb(wtb(w):='0'; tb(w--1 1 downtodownto 0):=b(w0):=b(w--1 1 downtodownto 0);0);
sas: sas: forfor i i inin 0 0 toto w w looploop
aq(2*w aq(2*w downtodownto w):= aq(2*w w):= aq(2*w downtodownto w) + w) + notnot tb +1; tb +1;
ifif (aq(2*w)='1') (aq(2*w)='1') thenthen
aq(2*w aq(2*w downtodownto w):= aq(2*w w):= aq(2*w downtodownto w) + tb; aq(0):='0'; w) + tb; aq(0):='0';
elseelse aq(0):='1'; aq(0):='1'; end ifend if; ;
aq(2*w aq(2*w downtodownto 1):= aq(2*w1):= aq(2*w--1 1 downtodownto 0); aq(0):= '0'; 0); aq(0):= '0';
end loopend loop sas; quot <= aq(w sas; quot <= aq(w downtodownto 1); 1);
end processend process ; ; endend first;first;
P.Bakowski 95
Generic divider for unsigned integers Generic divider for unsigned integers architecturearchitecture first first ofof seq_div seq_div isis
beginbegin processprocess(a,b) (a,b)
variablevariable aq: unsigned(2*w aq: unsigned(2*w downtodownto 0); 0);
variablevariable tb: unsigned(w tb: unsigned(w downtodownto 0);0);
beginbegin
aq(2*waq(2*w--1 1 downtodownto 0):=a(2*w0):=a(2*w--1 1 downtodownto 0); aq(2*w):='0';0); aq(2*w):='0';
tb(w):='0'; tb(wtb(w):='0'; tb(w--1 1 downtodownto 0):=b(w0):=b(w--1 1 downtodownto 0);0);
sas: sas: forfor i i inin 0 0 toto w w looploop
aq(2*w aq(2*w downtodownto w):= aq(2*w w):= aq(2*w downtodownto w) + w) + notnot tb +1; tb +1;
ifif (aq(2*w)='1') (aq(2*w)='1') thenthen
aq(2*w aq(2*w downtodownto w):= aq(2*w w):= aq(2*w downtodownto w) + tb; aq(0):='0'; w) + tb; aq(0):='0';
elseelse aq(0):='1'; end if; aq(0):='1'; end if;
aq(2*w aq(2*w downtodownto 1):= aq(2*w1):= aq(2*w--1 1 downtodownto 0); aq(0):= '0'; 0); aq(0):= '0';
end loopend loop sas; quot <= aq(w sas; quot <= aq(w downtodownto 1); 1);
end processend process ; ; endend first;first;
P.Bakowski 96
Generic divider for unsigned integers Generic divider for unsigned integers architecturearchitecture first first ofof seq_div seq_div isis
beginbegin processprocess(a,b) (a,b)
variablevariable aq: unsigned(2*w aq: unsigned(2*w downtodownto 0); 0);
variablevariable tb: unsigned(w tb: unsigned(w downtodownto 0);0);
beginbegin
aq(2*waq(2*w--1 1 downtodownto 0):=a(2*w0):=a(2*w--1 1 downtodownto 0); aq(2*w):='0';0); aq(2*w):='0';
tb(w):='0'; tb(wtb(w):='0'; tb(w--1 1 downtodownto 0):=b(w0):=b(w--1 1 downtodownto 0);0);
sas: sas: forfor i i inin 0 0 toto w w looploop
aq(2*w aq(2*w downtodownto w):= aq(2*w w):= aq(2*w downtodownto w) + w) + notnot tb +1; tb +1;
ifif (aq(2*w)='1') (aq(2*w)='1') thenthen
aq(2*w aq(2*w downtodownto w):= aq(2*w w):= aq(2*w downtodownto w) + tb; aq(0):='0'; w) + tb; aq(0):='0';
elseelse aq(0):='1'; aq(0):='1'; end ifend if; ;
aq(2*w aq(2*w downtodownto 1):= aq(2*w1):= aq(2*w--1 1 downtodownto 0); aq(0):= '0'; 0); aq(0):= '0';
end loopend loop sas; quot <= aq(w sas; quot <= aq(w downtodownto 1); 1);
end processend process ; ; endend first;first;
P.Bakowski 97
Generic divider for unsigned integers Generic divider for unsigned integers architecturearchitecture first first ofof seq_div seq_div isis
beginbegin processprocess(a,b) (a,b)
variablevariable aq: unsigned(2*w aq: unsigned(2*w downtodownto 0); 0);
variablevariable tb: unsigned(w tb: unsigned(w downtodownto 0);0);
beginbegin
aq(2*waq(2*w--1 1 downtodownto 0):=a(2*w0):=a(2*w--1 1 downtodownto 0); aq(2*w):='0';0); aq(2*w):='0';
tb(w):='0'; tb(wtb(w):='0'; tb(w--1 1 downtodownto 0):=b(w0):=b(w--1 1 downtodownto 0);0);
sas: sas: forfor i i inin 0 0 toto w w looploop
aq(2*w aq(2*w downtodownto w):= aq(2*w w):= aq(2*w downtodownto w) + w) + notnot tb +1; tb +1;
ifif (aq(2*w)='1') (aq(2*w)='1') thenthen
aq(2*w aq(2*w downtodownto w):= aq(2*w w):= aq(2*w downtodownto w) + tb; aq(0):='0'; w) + tb; aq(0):='0';
elseelse aq(0):='1'; aq(0):='1'; end ifend if; ;
aq(2*w aq(2*w downtodownto 1):= aq(2*w1):= aq(2*w--1 1 downtodownto 0); aq(0):= '0'; 0); aq(0):= '0';
end loopend loop sas; quot <= aq(w sas; quot <= aq(w downtodownto 1); 1);
end processend process ; ; endend first;first;
P.Bakowski 98
Generic divider for unsigned integers Generic divider for unsigned integers architecturearchitecture first first ofof seq_div seq_div isis
beginbegin processprocess(a,b) (a,b)
variablevariable aq: unsigned(2*w aq: unsigned(2*w downtodownto 0); 0);
variablevariable tb: unsigned(w tb: unsigned(w downtodownto 0);0);
beginbegin
aq(2*waq(2*w--1 1 downtodownto 0):=a(2*w0):=a(2*w--1 1 downtodownto 0); aq(2*w):='0';0); aq(2*w):='0';
tb(w):='0'; tb(wtb(w):='0'; tb(w--1 1 downtodownto 0):=b(w0):=b(w--1 1 downtodownto 0);0);
sas: sas: forfor i i inin 0 0 toto w w looploop
aq(2*w aq(2*w downtodownto w):= aq(2*w w):= aq(2*w downtodownto w) + w) + notnot tb +1; tb +1;
ifif (aq(2*w)='1') (aq(2*w)='1') thenthen
aq(2*w aq(2*w downtodownto w):= aq(2*w w):= aq(2*w downtodownto w) + tb; aq(0):='0'; w) + tb; aq(0):='0';
elseelse aq(0):='1'; aq(0):='1'; end ifend if; ;
aq(2*w aq(2*w downtodownto 1):= aq(2*w1):= aq(2*w--1 1 downtodownto 0); aq(0):= '0'; 0); aq(0):= '0';
end loopend loop sas; quot <= aq(w sas; quot <= aq(w downtodownto 1); 1);
end processend process ; ; endend first;first;
P.Bakowski 99
Generic divider for unsigned integers Generic divider for unsigned integers
binary division: (100 / 9 => 11)binary division: (100 / 9 => 11)
P.Bakowski 100
Parallel multiplier Parallel multiplier
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall; ;
entityentity comb_mul comb_mul isis
portport(a,b: (a,b: inin unsigned(3 unsigned(3 downtodownto 0); 0);
prod: prod: outout unsigned(7 unsigned(7 downtodownto 0)); 0));
endend comb_mul;comb_mul;
p0p0
p1p1
p2p2
p3p3
aa
bb
+++
+++
+++
+++prodprod
P.Bakowski 101
Parallel multiplier Parallel multiplier
architecturearchitecture first first ofof comb_mul comb_mul isis
signalsignal p0,p1,p2,p3: unsigned (7 p0,p1,p2,p3: unsigned (7 downtodownto 0); 0);
---- partial products partial products
beginbegin
p0 <= ("0000" & a) p0 <= ("0000" & a) whenwhen b(0)='1' b(0)='1' elseelse "00000000"; "00000000";
p1 <= ("000" & a & '0') p1 <= ("000" & a & '0') whenwhen b(1)='1' b(1)='1' elseelse "00000000"; "00000000";
p2 <= ("00" & a & "00") p2 <= ("00" & a & "00") whenwhen b(2)='1' b(2)='1' elseelse "00000000"; "00000000";
p3 <= ('0' & a & "000") p3 <= ('0' & a & "000") whenwhen b(3)='1' b(3)='1' elseelse "00000000"; "00000000";
prod <= (p0 + p1) + (p2 + p3); prod <= (p0 + p1) + (p2 + p3);
endend first;first;
P.Bakowski 102
Parallel multiplier Parallel multiplier
architecturearchitecture first first ofof comb_mul comb_mul isis
signalsignal p0,p1,p2,p3: unsigned (7 p0,p1,p2,p3: unsigned (7 downtodownto 0); 0);
---- partial products partial products
beginbegin
p0 <= ("0000" & a) p0 <= ("0000" & a) whenwhen b(0)='1' b(0)='1' elseelse "00000000"; "00000000";
p1 <= ("000" & a & '0') p1 <= ("000" & a & '0') whenwhen b(1)='1' b(1)='1' elseelse "00000000"; "00000000";
p2 <= ("00" & a & "00") p2 <= ("00" & a & "00") whenwhen b(2)='1' b(2)='1' elseelse "00000000"; "00000000";
p3 <= ('0' & a & "000") p3 <= ('0' & a & "000") whenwhen b(3)='1' b(3)='1' elseelse "00000000"; "00000000";
prod <= (p0 + p1) + (p2 + p3); prod <= (p0 + p1) + (p2 + p3);
endend first;first;
P.Bakowski 103
Parallel multiplier Parallel multiplier
Parallel multiplier: (3 * 12 => 36)Parallel multiplier: (3 * 12 => 36)
partial products: p0,p1,p2,p3partial products: p0,p1,p2,p3
P.Bakowski 104
SummarySummary
In this lecture we have presented some basic models In this lecture we have presented some basic models
arithmetical circuits.arithmetical circuits.
All presented models are synthetisable and exploit the All presented models are synthetisable and exploit the
standard synthesis libraries: standard synthesis libraries:
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall;;
Next lecture illustrates how to model simple processors.Next lecture illustrates how to model simple processors.
Several examples will be given including I8051 and Several examples will be given including I8051 and
AVR controllers.AVR controllers.
P.Bakowski 105
SummarySummary
In this lecture we have presented some basic models In this lecture we have presented some basic models
arithmetical circuits.arithmetical circuits.
All presented models are synthetisable and exploit the All presented models are synthetisable and exploit the
standard synthesis libraries: standard synthesis libraries:
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall;;
Next lecture illustrates how to model simple processors.Next lecture illustrates how to model simple processors.
Several examples will be given including I8051 and Several examples will be given including I8051 and
AVR controllers.AVR controllers.
P.Bakowski 106
SummarySummary
In this lecture we have presented some basic models In this lecture we have presented some basic models
arithmetical circuits.arithmetical circuits.
All presented models are synthetisable and exploit the All presented models are synthetisable and exploit the
standard synthesis libraries: standard synthesis libraries:
librarylibrary IEEE; IEEE;
useuse IEEE.std_logic_1164.IEEE.std_logic_1164.allall; ;
useuse IEEE.numeric_std.IEEE.numeric_std.allall;;
Next lecture illustrates how to model simple processors.Next lecture illustrates how to model simple processors.
Several examples will be given including Several examples will be given including I8051I8051 and and
AVRAVR controllers.controllers.