P. 4.1

Digital Technology and Computer Fundamentals

Chapter 4

Digital Components

P. 4.2

Objectives

At the end of this chapter, you should be able to: remember the function and logic

circuit of a half adder; describe the function of a full adder; draw the logic circuit of a full adder

with two half adders and an OR gate; distinguish the functions of an encoder

and a decoder;

P. 4.3

Objectives (Cont’d)

use truth table to define the function of a specific encoder / decoder circuit.

explain the operations of shift register circuits; and

explain the operations of the asynchronous and synchronous counter circuits employing flip-flops.

P. 4.4

References

Thomas C. Bartee, "Digital Computer Fundamentals," sixth edition, McGraw-Hill Publishing Company.

Richard S. Sandige, "Modern Digital Design," McGraw-Hill Publishing Company.

Theodore F. Bogart Jr., "Introduction to Digital Circuits,"” McGraw-Hill Publishing Company.

P. 4.5

Adders

The function of the adder circuits is to perform binary arithmetic.

A major component in the CPU. All kinds of arithmetic employ adders. Half adder and full adder.

P. 4.6

Half Adder

It performs half of the one bit addition. It adds two bits to give a sum and a

carry. It does not consider any carry input. Therefore it called a half adder.

P. 4.7

Half Adder (Cont’d)

Different conditions for the addition of two binary digits A and B:

P. 4.8

Half Adder (Cont’d)

Carry = A . B Sum = A B The logic circuit:

Half Adder

Carry

Sum

A

B

P. 4.9

Full Adder

The full adder circuit is able to complete the full addition process.

There are three inputs, the in carry, Ci, and the two binary digits, A and B.

Outputs are sum, S, and an out carry, Co.

P. 4.10

Full Adder (Cont’d)

The function of the full adder circuit.

P. 4.11

Full Adder (Cont’d)

Rearranging:

P. 4.12

Full Adder (Cont’d)

We can build a full adder circuit with two half adders and an OR gate.

P. 4.13

Encoder

The encoder produces a binary output corresponding to an input value. There are 2n or less input and n output lines in an encoder.

Example: decimal-to-binary encoder.

P. 4.14

Encoder (Cont’d)

P. 4.15

Decoder

The function of a decoder is the reverse process of an encoder.

A decoder converts binary information from n coded inputs to a maximum of 2n unique outputs.

Example: binary-to-decimal decoder.

P. 4.16

Decoder (Cont’d)

P. 4.17

Counters

Used for the control of sequence and program execution.

Two categories of counters: asynchronous and synchronous.

The asynchronous counters produce the outputs in sequence

The outputs of the synchronous counters are available at the same time.

P. 4.18

Counters (Cont’d)

Counters are made with either J-K or T-type flip-flops.

1 J

K

Q

Q

Clk

P. 4.19

Counters (Cont’d)

Q produces one pulse for every two clock pulses input.

The counter counts once for every two clock pulses.

The frequency at Q is half of that at the clock.

Sometimes called a divider. A J-K flip-flop can be regarded as a

divide-by-2 counter.

P. 4.20

Divide-by-16 Ripple (Asynchronous) Counter

J0

K0

Clk

Q0

FF0

J1

K1

Clk

Q1

FF1

J2

K2

Clk

Q2

FF2

J3

K3

Clk

Q3

FF3

1

1

1

1

1

1

1

1

Q0 Q1 Q2 Q3

Clock

P. 4.21

Divide-by-16 Ripple Counter (Cont’d)

Clock

Q0

Q1

Q2

Q3

P. 4.22

Divide-by-16 Ripple Counter (Cont’d) Q0 produces one clock pulse for every

two input clocks. At Q3, only one clock pulse is

generated for every 16 input clocks. The output sequence in Q3, Q2, Q1

and Q0, forms the binary numbers from 0 to 15

It counts the binary numbers.

P. 4.23

Divide-by-16 Ripple Counter (Cont’d) Propagation delay happens in

operations of flip-flops. Time delay for all output clocks

compared with their input clocks. Outputs are not available at the same

time, it is an asynchronous counter.

P. 4.24

Divide-by-16 Ripple Counter (Cont’d) A divide-by-2n counter can be built

with n J-K (or T-type) flip-flops. Disadvantage: Output clock transitions

do not happen at the same time. The time required for the outputs to be

available is equal to n propagation delay of one flip-flop, not suitable for high-speed circuits

P. 4.25

Divide-by-16 Synchronous Counter All output clock transitions happen at

the same time. Clocks are connected together. Input connections are more

complicated.

P. 4.26

Divide-by-16 Synchronous Counter (Cont’d)

P. 4.27

Divide-by-16 Synchronous Counter (Cont’d) FF0 is configured to change output

state for every transition of the clock. FF1 changes output state when the

output of FF0 is 1. When both Q0 and Q1 are at logical 1,

the output FF2 changes state after the clock.

FF3 changes state after the clock pulse when all other outputs are at logical 1.

P. 4.28

Divide-by-16 Synchronous Counter (Cont’d) A divide-by-2n synchronous counter

can be configured using n flip-flops and (n-2) AND gates.

The inputs of the mth flip-flop is connected to the output of an AND gate with its inputs being the outputs of the flip-flop 0 to the (m-1)th flip-flip.

P. 4.29

Shift Registers

Store a vector of binary digits - a simple memory array.

Parallel and serial input methods. Serial input method shifts the data into

the shift register one bit by one bit. Right-shift: LSB first, MSB last. Left-shift:MSB first, LSB last. Parallel input method: stores the data

into the register all at a time.

P. 4.30

Shift Registers (Cont’d)

The data in the shift register can be retrieved either in series or in parallel.

Example: 4-bit Left-Shift Register Built with J-K flip-flops with direct

inputs (preset and clear). Under normal operation, values at the

direct inputs are all at logical 1, so that they have no effect on the outputs.

P. 4.31

Shift Registers (Cont’d)

P. 4.32

Shift Registers (Cont’d)

For each flip-flop, the values at their two input terminals are always complemented to each other.

Equivalent to D-type flip-flop configuration.

In figure 4.. The register is initially cleared to 0000 via the clear input by giving a 0 to the clear input line.

P. 4.33

Shift Registers (Cont’d)

The waveform for input data 1101

P. 4.34

Shift Registers (Cont’d)

The data to be stored in the register is 1101.

At the end of the forth clock, the data 1011 will be shifted into the register.

Because the data are shifted into the register serially from LSB to MSB, it is a left-shifted register.

P. 4.35

Shift Registers (Cont’d)

At this time, the data can be read from the four Q outputs in parallel. This is called the serial in parallel out operation.

The data can also be read from the Q3 serially by providing four more clock pulses. Such operation is called serial in serial out operation.

P. 4.36

Shift Registers (Cont’d)

Data can also be entered in parallel using the preset terminals with suitable modifications on the circuit.

In that case, we can operate the register in Parallel in parallel out, and parallel in serial out modes.