overview on cbm daq boards development

Overview on CBM DAQ Overview on CBM DAQ Boards DevelopmentBoards Development

Walter F.J. Müller, GSI, Darmstadtfor the CBM Collaboration

Workshop on Silicon Detector Systemsfor the CBM Experiment at FAIR

GSI, 18-20 April 2007

18-20 April 2007 Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

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n-XYTER – seen from the DAQ n-XYTER – seen from the DAQ sideside The N-XYTER is quickly becoming the designated read-out solution

for many CBM detector system prototypes: obvious cases:

STS - Silicon strip detectors MUCH/TRD – GEM chambers

plausible cases: MUCH Silicon Pad chambers RICH PMT

potential cases: MUCH/TRD - MWPC chambers

The CBM-XYTER development just started. For several years to come the N-XYTER is thus the designated work horse for CBM detector prototyping.

We need a N-XYTER read-out chain to support simple lab desk-top setups medium-size test beam configurations with multiple sub-systems.


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32 MHzreadoutrate

n-XYTER Architecturen-XYTER Architecture

PreAmpPreAmp fast shaperfast shaper

peaking timefast: 20 nsslow: 140 ns

slow shaperslow shaper

timewalk

comp.

comparatorcomparator

tokencell

timestamp

counter

tokenmanager

1 ns step

32 MHzreadoutrate

outputdrivers

digitalFIFO

analogFIFO

peakdetect& hold

outputs:1 analog differential 8 digital LVDS (4*32 MHz)


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Basic n-XYTER Readout ChainBasic n-XYTER Readout ChainDetector

FEB ROCX

YTER

XY

TER

XY

TER

AD

C

XY

TER

Tag data

Tag data

Tag data

Tag data

ADC data

clockFP

GA

control

SFPMGT

ABB

FP

GA

SFP MGT

MGTMGT

Front-EndBoard

Read-OutController

Active BufferBoard

Bond orcable

connection

up to 8 N-XYTER1024 ch.

LVDSsignalcable

2.5 Gbpsoptical

link

1-4 lanePCIe

interface


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Basic n-XYTER Readout Chain – Basic n-XYTER Readout Chain – cont.cont.Detector

FEB ROCX

YTER

XY

TER

XY

TER

AD

C

XY

TER

Tag data

Tag data

Tag data

Tag data

ADC data

clockFP

GA

control

SFPMGT

ABB

FP

GA

SFP MGT

MGTMGT

Front-EndBoard

Read-OutController

Active BufferBoard

Siliconor

GEM dets

likelydifferent

form factorsneeded

keep thisinterfacecommon

one ROC

for all


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Scalable n-XYTER Readout Scalable n-XYTER Readout ChainChainDetector

FEB ROCX

YTER

XY

TER

XY

TER

AD

C

XY

TER

Tag data

Tag data

Tag data

Tag data

ADC data

clockFP

GA

control

SFPMGT

DCB

FP

GA

SFP MGT

MGT

Front-EndBoard

Read-OutController

Data CombinerBoard

to otherROC's

to ABB

SFP

SFP MGT

MGT

data andtime syncover sameserial link


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PC

Some ConfigurationsSome Configurations

Detector FEB ROC ABB

PCDCB ABB

Detector FEB ROC

Detector FEB ROC

Detector FEB ROC

Detector FEB ROC

Minimal Configuration

Expandable Configuration


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ROC ROC → SysCore based→ SysCore based

to FEB

to ABBor

DCB

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Basic Components and Interfaces

Xilinx Virtex4 FPGA

320 up to 576 user I/Os

LAN interfaces

SD-Card connector

LAN, USB, JTAG programming capability via CPLD

RS232 interface

High Speed Serial Ports (MGTs)

DDR SDRAM

user definable I/O

Watchdogslide courtesy D.

Gottschalk

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SysCore Features

(Remote) Configuration: via standard JTAG or select map configuration

via USB to JTAG bridge

via LAN Watchdog triggered

Radiation tolerant by fast configuration/reboot

Linux on FPGA

Fast Boot

All features together in one design

slide courtesy D. Gottschalk

memory image plus processor state after boot is stored and

reloaded.


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FPGA SEFI MitigationFPGA SEFI Mitigation

Most common FPGA's store the configuration in an internal SRAM A SEU (single event upset) of a config SRAM cell can thus lead to

a change on the functional behavior of the FPGA, called a SEFI (single event functional interrupt).

Upset rates are of the order of 1 SEFI per 108 p/cm2 Note:

most config SRAM bits are not used (a single SEU doesn't matter) multiple flipped unused config SRAM bits can lead to functional errors

Thus strategy: scrubbing – rewrite config SRAM periodically Xilinx Virtex-2, -4, and -5 devices allow glitch-free config update refresh config memory periodically during normal operation

FPGAVirtex-4

ControllerActel ProAsic3

FlashMemory

watch dog

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Enhanced FPGA refresh technology for radiation tolerance

Mode 1: Initial configuration

Mode 2: Refresh of the configuration memory (SRAM) either: continuously overwriting with the correct configuration or: overwriting on demand (after error detection)

Mode 3: Error detection: Read back of the configuration memory Checking (compare or checksum) Virtex 4: internal Hamming functionality

Mode 4: Watchdog triggers start of the failsafe configuration if design fails.

slide courtesy D. Gottschalk

as was developed for the Alice RCU

board


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DCB DCB → use 'HTX-Board'→ use 'HTX-Board'

six

V-4

MG

T b

ased

op

tical lin

ks

any board with manySPF's on V-4 MGT's

will do, e.g. ALICE GTU


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ABB ABB → V1 ready soon→ V1 ready soon

V-4 MGT based

optical link

V-4 MGT basedPCIe interface

(4 lanes)


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The EndThe End

Thanks for Thanks for your attentionyour attention

We acknowledge the support of the European Community-Research Infrastructure Activity under the

FP6 "Structuring the European Research Area" programme (HadronPhysics, contract number RII3-CT-

2004-506078).


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The EndThe End

Thanks for Thanks for your attentionyour attention


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tokencell

digitalFIFO

analogFIFO

tokencell

digitalFIFO

analogFIFO

Token Ring Token Ring ReadoutReadout

tokenmanager

outputdrivers

Token Cell Processes:on token, check for data,either initiate readout in clockcycle or pass forward token Token asynchronously passes from

channel to channel in search of data Within one clock cycle token could

pass through all channels use 2 stage logic design to keep logic

path short and allow scan of 128 channels in one clock cycle

If token encounters occupied channel, data readout is initiated (1 clock cycle)

After readout of one hitof one hit the token passes to the next occupied channel.

Token manager ensures that there is one and only one token is circling

Readout clock: 32 MHz


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.

Putting it together: n-XYTER Putting it together: n-XYTER ASICASIC

128 channels timestamp

counter

tokenmanager

outputdrivers

.

.

I2Cinterface

DACsslow

control

outputs:1 analog differential 8 digital LVDS (4*32 MHz)

Note: there is also a 32 channel version for MSGC readout called MSGCROC

overview on cbm daq boards development

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