overview of the 8051

8/2/2019 Overview of the 8051

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Chapter 2

8051 ArchitectureOverview of the 8051

In 1981 Intel Corporation introduced 8051. 8051 is an 8-bit, single-chip microcontroller optimized for control

applications It had 128 bytes RAM, 4096 bytes (4KB) ROM, 2 timers, 1 serial port, 4 I/O

ports(each 8-bit wide) all on a single chip. A System On Chip Packaged in a 40 pin dual in-line package (DIP) layout

8051 ArchitectureGeneral Physical Features

The 8051 architecture provides the following functions(CPU, RAM, ROM, I/O, interrupt logic, timer, etc.) in a single package.

8051 is an 8-bit processor.

The CPU can work on only 8 bits of data at a time It has 8-bit ALU, Accumulator and 8-bit Registers

8-bit data bus It can access 8 bits of data in one operation.

16-bit address bus It can access 216 memory locations 64 KB (65536locations) each of RAM and ROM

4KB of On chip ROM (Program Memory) 128 bytes of On chip RAM (data Memory)

4 register banks of 8 bytes each (R0-R7) 4 x 8 = 32 16 bytes of bit-addressable area 16 80 bytes of general purpose memory

80------------

128 128 bytes of Special Function Registers(only 21 are used)

Four 8-bit I/O ports 32 bidirectional I/O lines used as four 8-bit ports or individually

addressable I/O lines. Two 16-bit timers/Counters (Timer0 & Timer1) One Full duplex serial receiver-transmitter interface

Five interrupt sources (2 external & 3 internal)

One oscillator (generates clock signal)

Memory of 8051 can be increased externally: Increase memory space for codes (programs) by 64K bytes Increase memory space for data by 64K bytes.

The CPU of 8051 has the following registers and components:

8-bit ALU 16-bit Program counter (PC) 16-bit Data pointer (DPTR) Accumulator (A) register

B register Flags and 8-bit Program status word (PSW)

8-bit stack pointer (SP) Special function register (SFRs)

The block diagram of 8051 is shown in figure (1) and 1A.(Any one figure (1) and (1A) can be used).

The 8051 microcontroller is available in a 40-pin DIL (Dual-In-Line)package; The Pin assignments are shown in Figure.2
http://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Random_access_memoryhttp://en.wikipedia.org/wiki/Read-only_memoryhttp://en.wikipedia.org/wiki/Input/outputhttp://en.wikipedia.org/wiki/Interrupthttp://en.wikipedia.org/wiki/Timerhttp://en.wikipedia.org/wiki/Integrated_circuit_packaginghttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Data_bushttp://en.wikipedia.org/wiki/Address_bushttp://en.wikipedia.org/wiki/Kilobytehttp://en.wikipedia.org/wiki/Random_access_memoryhttp://en.wikipedia.org/wiki/Read-only_memoryhttp://en.wikipedia.org/wiki/Input/outputhttp://en.wikipedia.org/wiki/Interrupthttp://en.wikipedia.org/wiki/Timerhttp://en.wikipedia.org/wiki/Integrated_circuit_packaginghttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Data_bushttp://en.wikipedia.org/wiki/Address_bushttp://en.wikipedia.org/wiki/Kilobytehttp://en.wikipedia.org/wiki/Central_processing_unit


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The dual functions of pins are shown in figure 3

Figure 1

Figure 2 : The 8051 Pin Assignments


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Figure 1A

Figure 3: Dual Functions of Pins


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Pin Descriptions of 8051Pins 1-8: Port-1(P1.O-P1.7)Port 1 is a Quasi bi directional port. Each of these pins can be configured as I/P orO/P pins.This port does not offer any alternate functions

Pin-9: RST (Reset)Micro controller use Reset mechanism to establish initial conditions during initialpower-on or thereafter.When RESET pin is made high for two machine cycles (a pulse), microcontrollerwill terminate all its activities and reset. All registers are initialized to defaultvalues. Program counter is loaded with 0000H.


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Pin10-17: Port-3(P3.O-P3.7)Port 3 is a Quasi bi directional port with internal pull up.Each of these pins can be configured as I/P or O/P pins.Some alternate functions like interrupt input, timer/counter input and serialcommunication signals are shared with this port pins. Control signals necessaryfor external data memory interface, namely RDbar and WRbar, are also availablefrom this port.

Pins 10 & 11: RXD & TXD8051 has Full duplex serial data communication circuits .The data is transmitted out of 8051 through TXD line.The data is received by 8051 through the RXD line.

Pin 12 & 13:INT0 & INT1Interrupt-0 and Interrupt-1 are two interrupt pins that are triggered by externalcircuits.

Pins 14 & 15: T0 & T1

The 8051 has two 16-bit timers/counters.T0 is the Timer 0 external input.T1 is the Timer 1 external input.

Pins 16 &17: (WR and RD)When (pin 17) RD = 0, microcontroller reads the data from external RAM.When (pin 16) WR = 0, microcontroller writes the data into external RAM.

Pins 18 & 19: XTAL-2 & XTAL-1XTAL 1(pin 19) and XTAL 2 (pin 18) provide connecting resonant circuit (crystal)to form oscillator. In case of an external clock it must applied to XTAL- 2 and

XTAL-1 must be connected to GND.

Pin 20: VssIt is a ground pin.

Pins 21-28: Port-2(P2.O-P2.7)If external memory is not used, these pins can be configured as I/P or O/P pins.

If external memory is used then the higher address i.e. A8-A15 will appear on thisport.

Pin 29: PSEN(Program Store Enable)

This pin provides an output read strobe to external programmemory(ROM).

The output is active low during the fetch stage of an instruction.(and code bytefrom the ROM is placed on the data bus).

The signal is not activated during a fetch from internal memory.

Pin 30: ALE (Address Latch Enable)The ALE signal is an output pulse used to latch the low byte of an address duringaccess to external memory.

When ALE = 1, port 0 is providing lower order address (A0-A7)When ALE = 0, port 0 is used as data lines.

Pin 31: EAbar (External Access)This pin is used whenever external memory is used.


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When EAbar is connected to VCC i.e. EAbar = 1, code is stored ininternal ROM.

The device will execute programs from internal memory in the addressrange 0000h to 0FFFh. If address is larger than 0FFFh code is fetched fromexternal memory.

When EAbar is connected to GND i.e. EAbar = 0, code is stored inexternal ROM. The program is fetched from address location 0000h to FFFFh ofexternal memory.

Pins 32-39: Port-0(P0.7-P0.0)

This is a dual purpose port. The port may be used with external memory toprovide a multiplexed address and data bus.If external memory is not used, these pins can be configured as I/P or O/P pins.If external memory is used then the lower address i.e. A0-A7 will appear on thisport.

Pin 40: VCCDC power supply +5V is connected to this pin.

2.3 Functional Blocks of 8051Functions of architectural blocks of 8051 shown in figure (1) are described in nextsections

The OscillatorThe heart of 8051 is the circuitry that generates the clock pulses by which all

internal operations are synchronized.Pins XTAL1 and XTAL2 are provided for connecting resonator circuit

(Crystal) to form an oscillator.The crystal frequency is the basic internal frequency of the microcontroller.

8051 is designed to operate between 1MHz to 16MHz and generally operates witha crystal frequency 11.04962 MHz.

Machine Cycle

The smallest interval of time to accomplish any simple instruction, or part of acomplex instruction, is the machine cycle.

A machine cycle consists of a fixed number of clock cycles (pulses).

The 8051 family needs 12 clock cycles for a machine cycle.In 8051 the machine cycle is itself made up of six states. Two oscillator

pulses define each state.

A state is the basic time interval for discrete operations of themicrocontroller such as fetching an opcode byte, decoding an opcode, executingan opcode, or writing a data byte.

The CPU takes one or more machine cycles to complete an instruction.More complex instructions require more number of machine cycles to

complete the instruction. The numbers of machine cycles of the 8051 instructionsare ranging from 1 to 4.


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To calculate the time any particular instruction will lake to be executed,

Find the number of machine cycles(C) for the instruction, (from the datasheet/programmers manual).

The time to execute that instruction is then found by multiplying C by 12(clock pulses/machine cycle) and dividing the product by the crystalfrequency:

FrequencyCrystal

12dCTinst

=

Example 4-1Find the elapse time of the machine cycle for:

(a)XTAL = 11.0592 MHz(b)XTAL = 16 MHz(c)XTAL = 20 MHz

Solution:

(a)11.0592 MHz / 12 = 921.6 kHzMachine cycle = 1 / 921.6 kHz = 1.085 s

(b)16 MHz / 12 = 1.333 MHz

Machine cycle = 1 / 1.333 MHz = 0.75 s(c)20 MHz / 12 = 1.667 MHz

Machine cycle = 1 / 1.667 MHz = 0.60 s

Central Processing Unit (CPU):The 8051 CPU consists of 8-bit arithmetic and logic unit with associatedregisters.The 8051s ALU can perform arithmetic and logic functions on 8-bit variables.

The arithmetic unit performs addition, subtraction, multiplication and division.The logic unit can perform logical operations such as AND, OR and X-OR aswell as rotate, clear and complement.A Boolean processor performs bit wise operations. Set or clear bit,Compliment bit etc

CPU Registers


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Register are used to store information temporarily.The information to be stored could be1. A byte of data to be processed, or2. An address pointing to the data to be fetched

The majority of 8051 register are 8-bit registersThe 8 bits of a register are shown from MSB D7 to the LSB D0

The most widely used registers PC (program counter) , A (Accumulator), B, DPTR (data pointer), Stack

Pointer (SP) and and bank register R0, R1, R2, R3, R4, R5, R6, R7

Program Counter (PC) Program Counter (PC) is a 16-bit register. Holds the address of the memory location to fetch the program instruction. PC is the only register that does not have an internal address.

Program ROM may be on the chip at addresses 0000H to 0FFFH (4Kbytes),external to the chip for addresses that exceed 0FFFH

Program ROM may be totally external for all addresses from 1000H toFFFFH

PC is automatically incremented (+1) after every instruction byte is fetched

Data Pointer (DPTR) DPTR is a 16-bit register

DPTR is made up of two 8-bit registers: DPH and DPL DPTR holds the memory addresses for

internal and external code access

external data access(eg. MOVC A,@A+DPTR MOVX A,@DPTR MOVX @DPTR,A )

DPTR is under the control of program instructions and can be specified byits 16-bit name, or by each individual byte name, DPH and DPL

DPTR does not have a single internal address; DPH and DPL are eachassigned an address (83H and 82H)

Accumulator (A Register) In 8051 a 8 bit accumulator is used for many operations, including

addition, integer multiplication and division, and Boolean bit manipulations A register is a general-purpose register used for storing intermediate

results obtained during operation. Prior to executing an instruction upon any number or operand it is

necessary to store it in the accumulator first. All results obtained fromarithmetical operations performed by the ALU are stored in theaccumulator..

Data to be moved from one register to another must go through theaccumulator.

Access to accumulator is faster than access to memory.

Has direct path to ALU and can immediately store the result of operation. A register is also used for all data transfer between the 8051 and any

external memory

B Register


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B register is a 8- bit register used with the A register for multiplication anddivision operations. One of the operand is stored in B.

Higher order byte of Product after Multiplication, and Remainder afterDivision are stored in B.(eg. MUL AB DIV AB)

No other special function other than as a location where data may bestored

Program Status Word (PSW)PSW contains the math flags, user program flag F0, and the register select bits(RS1, RS0) that identify which of the four general-purpose register banks iscurrently in use by the program

PSW

Flags Flags are1-bit registers provided to store the status that reflects the

current state of the CPU. Flags are Set or Reset as result of certain program instructions.

Other instructions can test the condition of the flags and make decisions

based on the flag states Flags are grouped inside the program status word (PSW) for convenient

addressing Math flags respond automatically to the outcomes of math operations.

8051 has four Math flags namelyCary(CY) , Auxiliary Cary( AC), Overflow( OV), Parity(P) Flags

RS0, RS1 - Register bank selects bits. These two bits are used to selectone of four register banks of RAM. By setting and clearing these bits,registers R0-R7 are stored in one of four banks of RAM.

Table (1) shows the details different flags and RS0,RS1 bits.

Example 2Show the status of the CY, AC and P flag after the addition of 38Hand 2FH in the following instructions.MOV A, #38HADD A, #2FH ;after the addition A=67H, CY=0

Solution:38 00111000

+ 2F 00101111------ ---------------67 0 01100111

CY = 0 since there is no carry beyond the D7 bitAC = 1 since there is a carry from the D3 to the D4 biP = 1 since the accumulator has an odd number of 1s (it has five 1s)Example 2Show the status of the CY, AC and P flag after the addition of 9CH and 64H in thefollowing instructions.MOV A, #9CHADD A, #64H ; after the addition A=00H, CY=1Solution:

9C 10011100+ 64 01100100----- -------------100 1 00000000

CY = 1 since there is a carry beyond the D7 bitAC = 1 since there is a carry from the D3 to the D4 biP = 0 since the accumulator has an even number of 1s (it has zero 1s)


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Example Show the status of the CY, AC and P flag after the addition of 88Hand 93H in the following instructions.MOV A, #88HADD A, #93H ;after the addition A=1BH, CY=1Solution:

88 10001000+ 93 10010011

----- -----------------

11B 00011011CY = 1 since there is a carry beyond the D7 bitAC = 0 since there is no carry from the D3 to the D4 biP = 0 since the accumulator has an even number of 1s (it has four 1s)Table 1

Bit Symbol Function7 CY Carry Flag is used in arithmetic, JUMP, ROTATE, and BOOLEAN

instructions.Indicates carry out of D7 of result (accumulator) after executionof the instruction.

CY=1 If Carry exists out of D7 of accumulator. CY=0 If there is No carry out of D7 of accumulator.6 AC Auxiliary Carry Flag is used for BCD operations only.

AC=1 If there is a Carry out of D3 of the result.AC=0 If there is No Carry out of D3 of the result.

5 F0 User flag: A general-purpose flag that may be used by theprogrammer to record some event in the program

4 RS1 Register bank select bit 13 RS0 Register bank select bit 0

RS1 RS0

0 0 Select Register bank 00 1 Select Register bank 11 0 Select Register bank 21 1 Select Register bank 3

2 OV Overflow occurs when the result of an arithmetical operation islarger than 255 and cannot be stored in one register.Overflow flag is set (ie , OV=1)

if there is a1. Carry out of D6 and no carry out of D7 of result.2. Carry out from D7 (CY = 1) but no carry from D6 to D7.Else OV = 0

1 -- Reserved for future use0 P Parity Flag (P):The 8051 maintains even parity with the

accumulator A,i.e., the number of ones in the accumulator together with the

parity bit (in the program status word, PSW) is always even.

Parity flag; shows parity of register A:P = 1 if Odd Parity. (Odd number of 1s in A)P = 0 if Even Parity (Even number of 1s in A)


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Internal Memory A functioning computer must have

o memory for program code bytes, commonly in ROM, ando RAM memory for variable data that can be altered as the program runs.

Additional memory can be added externally using suitable circuits.The 8051 has Harvard architecture

o uses the same address but in different memories for code and data.

o The Internal circuitry access the correct memory based on the natureof the operation in progress

8051 has internal RAM (128 bytes) and ROM (4Kbytes).Internal RAM: The 128 bytes internal RAM is organized into 3 distinct areas.The internal RAM of 8051 is organized into three distinct areas:1. Working Registers2. Bit addressable registers3. General purpose registers

1. 32 bytes from address 00h to 1Fh that make up 32 working registersorganized as 4 memory banks of 8 registers each.

The 4 register banks are numbered 0 to 3 and are made up of 8registers named R0 to R7.

Each register can be addressed by name or by its RAM addresses.

Bits RS0 and RS1 in the PSW determine which bank of registers is

currently in use at any time when program is running. Register banks not selected can be used as general purpose RAM. Bank0 is selected by default on reset.


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Ex: Thus R0 of bank3 is R0 (if bank3 is selected ) or address 18h (wherebank3 is selected) .

PSW.3 = RS0=0 RS0=1 RS0=0 RS0=1

PSW.4 = RS1=0 RS1=0 RS1=1 RS1=1

2. A bit addressable area of 16 bytes occupies RAM byte addresses 20h to2Fh, forming total of 128 bits.

An addressable bit may be specified by its bit address of 00h to 7Fhor 8 bits may form any byte address from 20h to 2Fh.(shown in fig )

For example bit address 4fh is also bit 7 of byte address 29h.Addressable bits are useful when the program need only remember abinary event.

3. A general purpose RAM area above the bit area from 30h to 7Fh,addressable as byte.

May be used for any general-purpose storage including the stack.


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Any unused bytes of the bit-addressable area or unused register banks mayalso be used for general-purpose data storage.

Stack and Stack Pointer (SP) Stackrefers to an area of internal RAM that is used in conjunction with

certain opcodes to store and retrieve(take back) data quickly SP is a 8-bit register SP holds the internal RAM address where the last byte of data was

stored by a stack operation

An internal RAM address where last byte was stored by stack operationis called the top of the stack

When data is to be placed on the stack, the SP increments beforestoring data on the stack so that the stack grows up as data is stored.

As data is retrieved from the stack, the byte is read from the stack, andthen the SP decrements to point to the next available byte of storeddata

SP = 07H after reset.(default address stored in SP = 07h) so that thestack may start from 08H onward. (ie, Default stack is Bank 1)

The storing of a CPU register contents in to the stack is called a PUSH. Loading the contents of the stack back to the CPU register is called a

POP

Special Function Registers (SFR)

8051 has 21 SFRs which occupy the addresses from 80H to FFH (128bytes)Not all of the addresses from 80H to FFH are used for SFRsAttempt to use the empty addresses may get unpredictable result

Value of SFR at Reset


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Internal ROM Internal ROM occupies the code address space from 0000H to 0FFFH (Size

= 4K byte)

Program addresses higher than 0FFFH will automatically fetch code bytesfrom external program memory


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Code bytes can also be fetched exclusively from an external memory byconnecting the external access pin (EA) to ground

I/O Ports (P0 - P3)The 8051 has 32 Input/Output pins configured as four 8-bit parallel ports i.e.port-0, port-1, port-2 and port-3.

All ports are bidirectional (they can take input and to provide output)

Each pin can be configured as I/O or O/P under software control.

All ports have multiple functions (except P1)

All ports are bit addressable On RESET all the ports are configured as output When a bit latch is to be used as an input, a 1must be written to

the corresponding latch by the program to configure it as input (eg.MOV P1, #0FFH)

Port 0

Occupies a total of 8 pins (Pins 32-39)

It can be configured as

Input only

Output only

Input and output at the same time (i.e. some pins for input and theothers for output)

Can be used to handle both address and data

Need pull-up resistorsDual Role of Port 0

When connecting an 8051 to an external memory, port 0 provides bothaddress and data (AD0 AD7)

When ALE = 0, it provides data D0 D7

When ALE = 1, it provides data A0 A7

ALE is used for demultiplexing address and data with the help ofa 74LS373 latch

Port 1

Occupies a total of 8 pins (Pins 1-8)

Can be used as input or output

Does not need any pull-up resistors

Upon reset, port 1 is configured as an output port

No alternative functionsPort 2

Occupies a total of 8 pins (Pins 21-28) Similar function as Port 1.




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Upon reset, port 2 is configured as an output portDual Role of Port 2

When connecting an 8051 to an external memory, port 2 provides address(A8 A15)

It is used along with P0 to provide the 16-bit address

When P2 is used for the upper 8 bits of the 16-bit address, it cannot beused for I/O

Port 3

Occupies a total of 8 pins (Pins 10-17) Similar function as Port 1 and Port 2



Upon reset, port 3 is configured as an output port

Pins can be individually programmable for other uses

Most commonly be used to provide some important signals (e.g. interrupts)Port 3 Alternate Functions

P3 Bit Function Pin

P3.0 RxD 10

P3.1 TxD 11

P3.2 INT0 12

P3.3 INT1 13

P3.4 T0 14

P3.5 T1 15

P3.6 WR 16

P3.7 RD 17

Timers and Counters8051 has Two 16-bit programmable UP timers/counters. Timer 0 and Timer 1. T0 and T1 Can be configured to operate either as timers or as event

counters. The timer content is available in four 8-bit special function registers,

TL0,TH0,TL1 and TH1 respectively. In the "timer" function mode,

o the counter is incremented in every machine cycle.

o

Thus, one can think of it as counting machine cycles.o Hence the clock rate is 1/12 th of the oscillator frequency.

"counter" function mode,o the register is incremented in response to a 1 to 0 transition at its

corresponding external input pin (T0 or T1). The operation of the timers/counters is controlled by two special function

registers, TMOD and TCON respectively.

Serial Interface The serial port of 8051 is full duplex,

i.e., it can transmit and receive simultaneously. The register SBUF is used to hold the data.

The special function register SBUF is physically two registers. One is, write-only and is used to hold data to be transmitted out of the

8051 via TXD. The other is, read-only and holds the received data from external sources

via RXD.


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Both mutually exclusive registers have the same address 099H. Register SCON controls serial data communication.

Interrupts: 8051 provides 5 vectored interrupts. They are- I) INT0 2) INT1 3) TF0 4) TF1 5) RI/TI Out of these, INT0 and INT1 are external interrupts whereas Timer and

Serial port interrupts are generated internally. The external interrupts could be negative edge triggered or low level

triggered. All these interrupt, when activated, set the corresponding interrupt flags. Except for serial interrupt, the interrupt flags are cleared when the

processor branches to the Interrupt Service Routine (ISR). The external interrupt flags are cleared on branching to Interrupt Service

Routine (ISR), provided the interrupt is negative edge triggered. For low level triggered external interrupt as well as for serial interrupt, the

corresponding flags have to be cleared by software by the programmer.

overview of the 8051

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