Test Wrapper Designs for the Detection of Signal Integrity Faults on Core External Interconnects of SOCs

Qiang Xu and Yubin Zhang Krishnendu Chakrabarty The Chinese University of Hong Kong Duke University

Outline

• Introduction

• Prior work and motivation

• Overshoot detector

• Wrapper design for interconnect SI test

• Experimental results

• Conclusion

Signal Integrity

signal with acceptable

integrity

Vdd

Vss

ideal signal

t

V

Impact of Technology Scaling

Crosstalk

Serious crosstalk

Interconnect

Shrinking feature size

Signal Integrity Problem

Signal integrity is a major concern!

excessive delay

Vdd

Vss

ideal signalt

V overshoot

Testing SOC Interconnects

Test Wrapper

Core

Interconnect

Wrapper Output Cells Wrapper Input Cells

Test Wrapper

Core

Typical WOC for Interconnect SI Test

• Simultaneous aggressor transitions in test mode

• Different from functional mode

FFD Q

CTICTO

CFICFO

FFD Q

clk

Impact of Aggressor Alignment on Crosstalk

• Transition timing of aggressors/victim significantly

affects signal integrity

• Need for skewed transitions to avoid under-testing

A1

A2

A1

A2

Prior Overshoot Detector

• Cross-coupled differential

amplifier

• Test_Mode signal as

control of source current

• Hysteresis property

• Input-dependent detection

• Cannot detect overshoot in

all cases!

Source: M. Nourani and A. Attarha, TCAD’02

Vout

Vin

Vin1 Vin2

Vss

Vdd

T1

Vout

T5

T4T3

T2

Test_Mode

Motivation

• Prior SI test techniques– simultaneous transitions in test mode may

result in under-testing.– cannot detect overshoot in all cases.

• We need– wrapper input cell that can detect overshoot

and delay faults in all cases.– wrapper output cell that can apply skewed

transitions.

Proposed Overshoot Detector

• Maintain hysteresis

property

• Self-biased amplifier,

higher resolution

• Reset mechanism

• Can detect overshoot in

all cases

Buffer

Reset

Vin1 Vin2

Vss

Vdd

M1 M2

M6

M5

M4M3

Vout

Comparison of Overshoot DetectorsVO_1 VO_2 VO_3 VO_4

Time (ns)(d) Output from the overshoot detector in [20]

Vo

ltag

es (

v)V

olt

ages

(v)

Vo

ltag

es (

v)V

olt

ages

(v)

(a) Input signal with voltage overshoot

Time (ns)

Time (ns)

Time (ns)

(b) Shift signal as reset signal for the proposed overshoot detector

(c) Output from the proposed overshoot detector

0.5

0

1

0.5

0

1

0.5

0

1

0.5

0

1

0 10 3020 40

0 10 3020 40

0 10 3020 40

0 10 3020 40

Comparison of Overshoot DetectorsVO_1 VO_2 VO_3 VO_4

Time (ns)(d) Output from the overshoot detector in [20]

Vo

lta

ge

s (v

)V

olt

ag

es

(v)

Vo

lta

ge

s (v

)V

olt

ag

es

(v)

(a) Input signal with voltage overshoot

Time (ns)

Time (ns)

Time (ns)

(b) Shift signal as reset signal for the proposed overshoot detector

(c) Output from the proposed overshoot detector

0.5

0

1

0.5

0

1

0.5

0

1

0.5

0

1

0 10 3020 40

0 10 3020 40

0 10 3020 40

0 10 3020 40

Comparison of Overshoot DetectorsVO_1 VO_2 VO_3 VO_4

Time (ns)(d) Output from the overshoot detector in [20]

Vo

lta

ge

s (v

)V

olt

ag

es

(v)

Vo

lta

ge

s (v

)V

olt

ag

es

(v)

(a) Input signal with voltage overshoot

Time (ns)

Time (ns)

Time (ns)

(b) Shift signal as reset signal for the proposed overshoot detector

(c) Output from the proposed overshoot detector

0.5

0

1

0.5

0

1

0.5

0

1

0.5

0

1

0 10 3020 40

0 10 3020 40

0 10 3020 40

0 10 3020 40

Wrapper Input Cell

• Equipped with overshoot detector

• One extra FF as delay detector (FF1).

FF 1D Q

FF 2D Q

shift

FF 3D Qovershoot

detector

sicapt

sicaptSiTest

CTI

CTO

CFICFO

MODE

shift

Reset

Wrapper Input Cell

• Equipped with overshoot detector

• One extra FF as delay detector (FF1).

• Save test dataFF 1D Q

FF 2D Q

shift

FF 3D Qovershoot

detector

sicapt

sicaptSiTest

CTI

CTO

CFICFO

MODE

shift

Reset

Wrapper Input Cell

• Equipped with overshoot detector

• One extra FF as delay detector (FF1).

• Save test data

• Shift out result

FF 1D Q

FF 2D Q

shift

FF 3D Qovershoot

detector

sicapt

sicaptSiTest

CTI

CTO

CFICFO

MODE

shift

Reset

Test Strategy I

Test Wrapper

Core

Interconnect

Wrapper Output Cells Wrapper Input Cells

Test Wrapper

Core

D

D

DD D D

D D D

Test Strategy I

Test Wrapper

Core

Interconnect

Wrapper Output Cells Wrapper Input Cells

Test Wrapper

Core

D

D

D

Test Strategy I

Test Wrapper

Core

Interconnect

Wrapper Output Cells Wrapper Input Cells

Test Wrapper

Core

D

D

D

Functional path

Test Strategy II

Test Wrapper

Core

Interconnect

Wrapper Output Cells Wrapper Input Cells

Test Wrapper

Core

D

D

D

Test Strategy II

Test Wrapper

Core

Interconnect

Wrapper Output Cells Wrapper Input Cells

Test Wrapper

Core

D

D

D

Test path

Controlled-Delay Element for Skewed-Transition

C0

C0

C0

C0

C1

C1

C2

Vin Vout

B1

B2

B3

B4

B5

B6

B7

Proposed Wrapper Output Cell

FF 1D Q

FF 2D Q

delay element

C2 C1 C0

FF 3D Q

FF 4D Q

FF 5D Q

CK CKCK

Shift

WRCK

shift

SiTest

SiTest

SiTest

MODE

CTI

CTO

CFI CFO

Proposed Wrapper Output Cell

FF 1D Q

FF 2D Q

delay element

C2 C1 C0

FF 3D Q

FF 4D Q

FF 5D Q

CK CKCK

Shift

WRCK

shift

SiTest

SiTest

SiTest

MODE

CTI

CTO

CFI CFO

Experimental Setup

• 90 nm technology with 1V power supply

• 5 mm long victim with 5 aggressors, each coupling for a 1

mm length

• On the eighth metal layer with typical parameter

Victim

Aggressor j

Aggressor k

Aggressor l

Aggressor i Aggressor m

Victim

Experimental Results with Previous WOC

Vo

ltag

es (

v)

Time (ns)

Aggressors

Victim

Waveformat receiving end of interconnect

0.556 ns 0.556 ns

Experimental Results with Proposed WOCV

olt

ag

es

(v

)

Time (ns)

Victim

Aggressors Waveformat receiving end of interconnect

0.595 ns

Vo

ltag

es (

v)

Time (ns)

Victim

Aggressors Waveformat receiving end of interconnect

0.614 ns

0.595 ns 0.614 ns

with 2 delay paths with 4 delay paths

Vo

lta

ge

s (

v)

Time (ns)

Victim

AggressorsWaveform

at receiving end of interconnect

0.627 ns

Vo

ltag

es (

v)

Time (ns)

Victim

Aggressors Waveformat receiving end of interconnect

0.622 ns

Experimental Results with Proposed WOC – Cont.

0.627 ns0.622 ns

with 6 delay paths with 8 delay paths

Discussion

• Benefits– Enhanced signal-integrity fault detection

capability

• Costs– DfT area overhead– test time– Possible over-testing

Conclusion

• Signal integrity is a major concern for today’s SoC

interconnects

• We have proposed novel test wrappers that– Detect all kinds of overshoots– Apply skewed-transitions for aggressors/victim groups– Have moderate overhead

Q & A