optimizing regular expression matching with sr-nfa on multi-core systems
DESCRIPTION
Optimizing Regular Expression Matching with SR-NFA on Multi-Core Systems. Authors : Yang, Y.E. , Prasanna , V.K. Publisher : Parallel Architectures and Compilation Techniques (PACT), 2011 International Conference on Presenter : 楊皓中 Date : 2014/09/17. - PowerPoint PPT PresentationTRANSCRIPT
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Optimizing Regular Expression Matching with SR-NFA on Multi-Core Systems
Authors : Yang, Y.E. , Prasanna, V.K. Publisher : Parallel Architectures and Compilation Techniques (PACT), 2011 International Conference on Presenter : 楊皓中 Date : 2014/09/17
Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C.
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NFA(Basic modified McNaughton-Yamada Constructions)
National Cheng Kung University CSIE Computer & Internet Architecture Lab
2
\x2F(fn|s)\x3F[^\r\n]*(i|&*)
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Single-Segment SR-NFA
National Cheng Kung University CSIE Computer & Internet Architecture Lab
3
State-reachability matrix
Character-acceptance matrix
Input : \x2Ffn\x3FssiQ = 10000000 (initial state from root)V = 00000000
\x2F(fn|s)\x3F[^\r\n]*(i|&*)
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SR-NFA ARCHITECTURE
National Cheng Kung University CSIE Computer & Internet Architecture Lab
4
State-reachability matrix
Character-acceptance matrix
Input : \x2Ffn\x3FssiT = Q = 10000000 V = T and C(\x2F) = 10000000 and 10000100 = 10000000
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SR-NFA ARCHITECTURE
National Cheng Kung University CSIE Computer & Internet Architecture Lab
5
State-reachability matrix
Character-acceptance matrix
Input : \x2Ffn\x3FssiT = R(V) or Q = R(1) or Q = 01010000 or 10000000 =11010000V : T and C(f) = 11010000 and 01000100 = 01000000
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SR-NFA ARCHITECTURE
National Cheng Kung University CSIE Computer & Internet Architecture Lab
6
State-reachability matrix
Character-acceptance matrix
Input : \x2Ffn\x3FssiT = R(V) or Q = R(2) or Q = 00100000 or 10000000 = 10100000V : T and C(n) = 10100000 and 00100100 = 00100000
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SR-NFA ARCHITECTURE
National Cheng Kung University CSIE Computer & Internet Architecture Lab
7
State-reachability matrix
Character-acceptance matrix
Input : \x2Ffn\x3FssiT = R(V) or Q = R(3) or Q = 00001000 or 10000000 = 10001000V : T and C(\x3f) = 10001000 and 00001100 = 00001000
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SR-NFA ARCHITECTURE
National Cheng Kung University CSIE Computer & Internet Architecture Lab
8
State-reachability matrix
Character-acceptance matrix
Input : \x2Ffn\x3FssiT = R(V) or Q = R(5) or Q = 00000111 or 10000000 = 10000111V : T and C(s) = 10000111 and 00010100 = 00000100
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SR-NFA ARCHITECTURE
National Cheng Kung University CSIE Computer & Internet Architecture Lab
9
State-reachability matrix
Character-acceptance matrix
Input : \x2Ffn\x3FssiT = R(V) or Q = R(6) or Q = 00000111 or 10000000 = 10000111V : T and C(s) = 10000111 and 00010100 = 00000100
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SR-NFA ARCHITECTURE
National Cheng Kung University CSIE Computer & Internet Architecture Lab
10
State-reachability matrix
Character-acceptance matrix
Input : \x2Ffn\x3FssiT = R(V) or Q = R(6) or Q = 00000111 or 10000000 = 10000111V : T and C(i) = 10000111 and 00000101 = 00000101
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Single-Segment SR-NFA
National Cheng Kung University CSIE Computer & Internet Architecture Lab
11
1.memory complexity of the SRM grows quadratically in the number of states
𝑛2
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Single-Segment SR-NFA
National Cheng Kung University CSIE Computer & Internet Architecture Lab
12
2.bit-AND and bit-OR on the state vector becomes a proportionally more complex operation
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Single-Segment SR-NFA
National Cheng Kung University CSIE Computer & Internet Architecture Lab
13
3.the SRM is usually very sparse in the NFAs for most real-life regexes
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Multi-Segment SR-NFA
National Cheng Kung University CSIE Computer & Internet Architecture Lab
14
\x2F(fn|s)\x3F[^\r\n]*(i|&*)
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Multi-Segment SR-NFA
National Cheng Kung University CSIE Computer & Internet Architecture Lab
15
Segment 0
Segment 1
Segment 2
Forward-pseudo state
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Multi-Segment SR-NFA
16
F1 F2
F3
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Multi-Segment SR-NFA
17
F1 F2
F3
Segment 0 : (1,2,3)Q : 100V : 000
Segment 1 : (4,5,6)Q : 000V : 000
Segment 2 : (7,8)Q : 000V : 000
Input : \x2Ffn\x3Fssi
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Multi-Segment SR-NFA
18
F1 F2
F3
Segment 0 : (1,2,3)T = Q = 100 V = T and C(\x2F) = 100 and 100 = 100
Segment 1 : (4,5,6)T = Q = 000 V = T and C(\x2F) = 000 and 001 = 000
Segment 2 : (7,8)T = Q = 000 V = T and C(\x2F) = 000 and 000 = 000
Input : \x2Ffn\x3Fssi
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Multi-Segment SR-NFA
19
F1 F2
F3
Segment 0 : (1,2,3)T = 100V = 100
Segment 1 : (4,5,6)T = 000 V = 000
Segment 2 : (7,8)T = 000 V = 000
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 0 non
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Multi-Segment SR-NFA
20
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 010 or 100 = 110V =
Segment 1 : (4,5,6)T = 000 V =
Segment 2 : (7,8)T = 000 V =
Input : \x2Ffn\x3Fssi
F1=0,F2=1 F3 = 0 non
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Multi-Segment SR-NFA
21
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 010or100 = 110V =
Segment 1 : (4,5,6)T = 100V =
Segment 2 : (7,8)T = 000 V =
Input : \x2Ffn\x3Fssi
F1=0,F2=1 F3 = 0 non
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Multi-Segment SR-NFA
22
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 010or100 = 110V = 110 and 010 = 010
Segment 1 : (4,5,6)T = 100V = 100 and 001 = 000
Segment 2 : (7,8)T = 000 V = 000
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 0 non
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Multi-Segment SR-NFA
23
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 001or100 = 101V =
Segment 1 : (4,5,6)T = 000V =
Segment 2 : (7,8)T = 000 V =
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 0 non
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Multi-Segment SR-NFA
24
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 001or100 = 101V = 101 and 001 = 001
Segment 1 : (4,5,6)T = 000V = 000
Segment 2 : (7,8)T = 000 V = 000
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 0 non
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Multi-Segment SR-NFA
25
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 000or100 = 100V =
Segment 1 : (4,5,6)T = 000V =
Segment 2 : (7,8)T = 000 V =
Input : \x2Ffn\x3Fssi
F1=1,F2=0 F3 = 0 non
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Multi-Segment SR-NFA
26
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 000or100 = 100V =
Segment 1 : (4,5,6)T = 010V =
Segment 2 : (7,8)T = 000 V =
Input : \x2Ffn\x3Fssi
F1=1,F2=0 F3 = 0 non
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Multi-Segment SR-NFA
27
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 000or100 = 100V = 100 and 000 =000
Segment 1 : (4,5,6)T = 010V = 010 and 011 = 010
Segment 2 : (7,8)T = 000 V = 000
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 0 non
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Multi-Segment SR-NFA
28
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 000or100 = 100V =
Segment 1 : (4,5,6)T = 001V =
Segment 2 : (7,8)T = 000 V =
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 1 non
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Multi-Segment SR-NFA
29
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 000or100 = 100V =
Segment 1 : (4,5,6)T = 001V =
Segment 2 : (7,8)T = 111V =
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 1 non
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Multi-Segment SR-NFA
30
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 000or100 = 100V = 100 and 000 = 000
Segment 1 : (4,5,6)T = 001V = 001 and 101 = 001
Segment 2 : (7,8)T = 111V = 111 and 000 = 000
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 0 non
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Multi-Segment SR-NFA
31
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 000or100 = 100V =
Segment 1 : (4,5,6)T = 001V =
Segment 2 : (7,8)T = 000V =
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 1 non
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Multi-Segment SR-NFA
32
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 000or100 = 100V =
Segment 1 : (4,5,6)T = 001V =
Segment 2 : (7,8)T = 111V =
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 1 non
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Multi-Segment SR-NFA
33
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 000or100 = 100V = 100 and 000 = 000
Segment 1 : (4,5,6)T = 001V = 001 and 101 = 001
Segment 2 : (7,8)T = 111V = 111 and 000 = 000
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 0 non
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Multi-Segment SR-NFA
34
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 000or100 = 100V =
Segment 1 : (4,5,6)T = 001V =
Segment 2 : (7,8)T = 000V =
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 1 non
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Multi-Segment SR-NFA
35
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 000or100 = 100V =
Segment 1 : (4,5,6)T = 001V =
Segment 2 : (7,8)T = 111V =
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 1 non
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Multi-Segment SR-NFA
36
F1 F2
F3
Segment 0 : (1,2,3)T = R(V)orQ = 000or100 = 100V = 100 and 000 = 000
Segment 1 : (4,5,6)T = 001V = 001 and 001= 001
Segment 2 : (7,8)T = 111V = 111 and 010= 010
Input : \x2Ffn\x3Fssi
F1=0,F2=0 F3 = 0 non
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PERFORMANCE EVALUATION
National Cheng Kung University CSIE Computer & Internet Architecture Lab
37
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National Cheng Kung University CSIE Computer & Internet Architecture Lab
38
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National Cheng Kung University CSIE Computer & Internet Architecture Lab
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Throughput scaling
National Cheng Kung University CSIE Computer & Internet Architecture Lab
40