optimized on system analysis using aes and...

© 2013, IJARCSSE All Rights Reserved Page | 18

Volume 3, Issue 2, February 2013 ISSN: 2277 128X

International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com

Optimized on System Analysis Using AES and X-tea Rashi Kohli

[1] Manoj Kumar

[2]

Computer Science and Engineering Computer Science and Engineering

Amity University , India Amity University, India

Abstract— In this paper the importance of cryptographic system is analyzed which is the foremost constituent in

designing numerous amounts of applications available today. Several cryptographic algorithms and approaches have

been used so far, so the main focus lies on the minimal usage of operations. Designers have to keep in mind security

issues so as to achieve optimization in terms of area-system chip, power consumption and most important complexity.

This paper will present on system chip design and implementation of advance encryption standard that uses

substitution box which is key ingredient of security and we will introduce the hardware implementation design of Kogge

Stone adder as a component of X-tea that will help in building up the optimized solution in for small scale applications

and can be integrated along with other algorithms.

Keywords— Cryptography, S-Box, VLSI, security, multi-encryption

I. INTRODUCTION

In today’s era data is paramount, and in future it will keep on increasing as well as network is expanding at its pace, there

is need to design the secure systems. There is a growing need for designing and implementing these cryptographic

algorithms in a way reducing the complexity and mounting the security. The parameters which must be taken into

consideration are security, memory usage and minimal system-on-chip design. Cryptography seeks information from

various sources for proper conclusions on security and utilizing the minimal amount of resources. The sources can be

symmetric i.e. private cryptographic algorithm routine and asymmetric cryptographic algorithm routine.

Figure 1: Categorization of Cryptographic Algorithms

Cryptographic Algorithm’s Routine

Symmetric Routine Algorithm

Property: One Key (Secret key)

Asymmetric Routine Algorithm

Property: Two Keys (Public

key)

Cryptographic Hash function

Algorithm

Property: Hash Function

Block Cipher

Property: Partition

large blocks

Stream Cipher

Property: Partition

Small blocks

RC-4

ORYX

SEAL

…….

Diffie-Hellman

ElGamal

RSA

………. ……

SHA

MD-5

MD-4

MD-2

3DES

AES

TEA

X-TEA

RC-2

RC-6

BLOWFISH

DES

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http://www.ijarcsse.com/

Rashi et al., International Journal of Advanced Research in Computer Science and Software Engineering 3(2),

February - 2013, pp. 18-25


Many researchers have found that asymmetric approach is slower than the symmetric ones. In the former approach only

one key is used to encrypt and decrypt the data and in the latter one 2 separate keys are used for the process of encryption

and decryption .So in this paper focus entirely lies on the faster one i.e. advance encryption standard and light weight

algorithm i.e. X-tea which is known for its small size X-tea will be powerful ingredient in designing cryptographic system

for information systems before designing the multi-encryption technique, we have to analyze the hardware components so

that we can minimize the operations, but the existing methodology has definite disadvantages, the process takes

significant time for the expert to get the encryption and decryption done. In this paper we will analyze the advance

encryption standard although a powerful routine for presenting strong encryption analysis but it relies heavily on large look

up tables and pre-computations, i.e. substitution box for encryption and inverse of substitution box for decryption [5][6]

[7][8].

II. RELATED WORK

Different authors carried out extensive research and study taking into relation either the symmetric or asymmetric

cryptographic algorithms. It was analysed that latter one i.e. asymmetric ones are 1000 times slower than symmetric

algorithms. Demand for mobility and handheld devices are shooting up day by day. With the initiation of CMOS

technology and VLSI design approach, designers could design single chips using various operations and operators

depending upon the algorithmic logic. The selection of algorithms depends on the user, system and application

requirements. Because of the complexity of these operations and circuits used, it was not possible to verify these

operations on the breadboard. But due to the VLSI approach different methodologies and tools & techniques are

available for simulation and implementation routine i.e. ModelSim simulator and Xilinx FPGA kit. There are different

methodologies for implementing cryptographic algorithms, it depends whether one is designing for software or hardware

which leads to the design phase of the algorithm i.e. top-down design hierarchy, bottom-up design hierarchy hybrid

design hierarchy. In the past there are several software implementations for advance encryption standard and other

algorithms like DES, 3DES, tea, X-tea, SEA, RC-2, RC-4, and RC-6 and other’s but designing hardware

implementations which employ exclusively hardware description languages is very tiresome task. It was provided by the

researchers that AES is faster and more efficient algorithm since it imparts S-box design which is responsible for

instructing non-linearity to the system therefore design of substitution box is of allied importance. AES in the history was

demonstrated to be stronger than data encryption standard and 3DES. With some disadvantages i.e. firstly, complexity of

the key component i.e. S-Box is a main interference. Secondly it also employs P-array which is also escalating the

memory and storage area. Thirdly, dropping the number of rounds that are used throughout the encryption and decryption

routine could decline the memory and storage space but simultaneously it makes the algorithm insecure. Lastly, it was

fulfilled that advance encryption standard leads to rise in energy utilization which is one of the encumbrance towards

achieving optimization of the cryptographic algorithms [2],[3],[5].

III. COMPARATIVE ANALYSIS

TABLE 1. COMPARATIVE ANALYSIS [1],[5]

Every Cryptographic algorithm is entitled to deliver specific conditions and based on their characteristics; applications

that are needed to build utilize these algorithms that perform specific task. As network size is increasing there are certain

applications i.e. in the domain of wireless sensor network, ubiquitous computing, radio frequency identification,

Distinctive

Parameters

AES X-TEA

1. Approach Used S-box and P-array and use look

up tables

Feistel network architecture

2. Type of algorithm Symmetric block cipher algorithm Symmetric block cipher

algorithm

3. Criteria of selection High speed and low RAM

requirements

Small, secure and simplicity

4. Resource Utilization High Low

5. Memory Area chip Large adequate area chip Small area chip

6. Block Size 128,192 or 256 bit 64 bit block

7. Key size 128,192 or 256 bit size 64,128 bit key size

8. Encryption Time More since vast S-box is used Less since basic operations are

used

9. Applicability Large applications Smaller applications

10. Applications Embedded systems, Military

applications, android applications,

Security issues of digital cinema

projection equipments etc.

Wireless sensor networks,

ubiquitous computing, radio

frequency identification(RFID)

etc


February - 2013, pp. 18-25


Bluetooth technology, embedded systems, android applications etc, every application is unique and has different

distinctiveness which must be mapped correctly with the approach and technique used, for example we have moved

towards in achieving mobility which demands less memory and storage area, more secure applications etc. For these

kinds of applications it is required to use simpler algorithms such as tea, X-tea in which there are limited number of

operations and requires less memory area-chip. But there are certain applications which are very complex and demands

more memory area/chip, securing such applications will demand algorithms like DES, 3DES, IDEA, RC-6, RC4 and

many others [5],[6].

IV. DESIGN CONSTRAINTS

Before designing the algorithms i.e. AES and X-tea, we will first state the criteria for designing the same. Therefore, it is

mandatory to make few critical design decisions. While designing x-tea since it is known for its small size, we can design

encryption and decryption routine together although the process will be followed one after another but an optimized way

out will be to design it as a single unit. Since our objective is to achieve optimization in terms of low resource

requirements, minimizing the system on chip area, we will use the basic operations and registers for storage of data. The

operations which will be utilized will be adders, subtractors, xor operations and multiplexers. Adders will be utilized

during encryption process and subtractors will be utilized during the decryption process which is the reverse of

encryption. These operations are necessary to carry out in order to build on system chip design. Now we will take into

account AES for which we have design of different architectural unit’s i.e. key expansion unit, round column, S-box,

Inv-SBox etc. So in designing these we have to keep in mind all the operations and operators used, since they affect the

optimization level. For implementing any cryptographic algorithm we have to flow certain set of concurrent sequence of

steps that forms the design flow [1],[2],[4][5].

V. PROPOSED DESIGN HIERARCHY OF AES

Since Advance encryption standard is known for its strong security and it is the successor of precious versions of

cryptographic algorithms i.e. DES and 3DES. It has been taken into an account if the design requirements require

complex operations and high performance security requirements. Rijndael algorithm is a block cipher symmetric

algorithm that supports changeable data block size and to achieve security it provides different key lengths depending

upon the number of rounds. “KEY here is the main component for achieving security. The proposed architecture utilizes

polynomial multiplication in the form of xor operations so as to decrease the hardware complexity. It goes through

different phases i.e. firstly Byte substitution with the help of which substitution box is designed, secondly it encompasses

the routine of shift row and mixed column operations and lastly the key scheduling routine which is responsible for

security.[1][2][12].The proposed hardware architectural model is a 3-level hierarchical design as depicted in the figure 2.

The root or top level module is advance encryption Standard_Module which contains all the components which make up

the algorithm. Secondly diverse signals are necessary performing specific task, for example ld signal when active will

show that new set of plaintext or cipher text are available for encryption and decryption process respectively. ”rst” signal

is used to reset the states back to the initial stage. The architecture is fully pipelined reducing the critical path in terms of

frequency in comparison with the previous architecture. The following table 2 determines the usage of operations in

implementing the pipelined architecture using advance encryption standard. Since S-box occupies maximum amount of

space in the proposed approach the number of slice LUT’s (look up table utilization) is 8%. It is also showing advantage

in terms of input-output bounds (IOB) which is 122%. IOB accounts for multiple usage through single input for better

performance. In this paper the pipelined implementation of AES is shown but it is useful in large applications like

Bluetooth technology, securing embedded systems etc. but it has disadvantage in terms of S-box although it provides

security but it occupies large amount of space and increases complexity in terms of lines of code and operations, for this

we can use lightweight cryptography approach using tiny encryption algorithm, extended tiny encryption algorithm, as

per the previous work it is analysed that these algorithms require low memory requirements and thus it can help in

achieving optimization[2][11]. Table2: AES DEVICE UTILIZATION SUMMARY SHEET

Device Utilization Summary Sheet

Logic Utilization Used Available Utilization

Number of Slice Registers 1744 42000 4%

Number of Slice LUT’s 1728 21000 8%

Number of Bonded IOB’s 257 210 122%

Number of Fully Used LUT-FF Pair 1728 1744 99%

Number of Block RAM/FIFO 14 52 26%

Number of BUFG/ BUFG CTRLS 1 32 3%


February - 2013, pp. 18-25


Ld

Clk Process

Complete

Rst

Figure 2: AES Encryption Architecture Design

A. INTRODUCTION TO AES

Rijndael proposed the AES algorithm which is a symmetric iterative block cipher algorithm that contains a variable key

usually it is 128 bit key size but it can be extended to 192 or 256 bit depending upon the designer and the application for

which the algorithm implementation will be used. This paper implements the AES algorithm using VLSI technology

operating at 128 bit block and utilizing 128 bit key, we can take hexadecimal or binary form of key. Each standard round

within the algorithm passes through different phases which are in the form of transformations i.e. S-Box , shift row, mix

column and round key generation.

The number of rounds in the algorithm depends upon the block and the key size used for example as of now in

this paper since we are using 128 bit block so number of rounds will be 10 here. The final round just like other rounds

have to go through all the phases in the advance encryption algorithm except that Mix column phase cycle will not be

there. Decryption process will be reverse and it will use Inverse_S-box. In this paper we have used the pipelined

approach for implementing the encryption and decryption since it will increase its throughput time and will be suitable

for low cost silicon implementation. The functions which will be used to compute the S-Box will use affine mapping

concept for encryption and inverse_affine mapping for decryption process.

Affine mapping for encryption round will be calculated as Val_AffTrans[m] = val[m] ^ val[(m+4)%8] ^ val[(m+5)%8] ^

val[(m+6)%8]^ val[(m+7)%8] ^ c_i[m]; where c_i[m] is 01100011 is constant, leftmost bit is being MSB

Inverse Affine mapping for decryption round will be calculated as InvAffIndex[i] = index[(m+2)%8] ^

index[(m+5)%8] ^ index[(i+7)%8] ^ c_inv[m]; where c_inv[m] is 00000101 is constant, leftmost bit being MSB.

[1],[2],[3].

B. DESIGN FLOW IMPLEMENTATION

The proposed architecture was implemented using Xilinx ISE-13.2 suite using Spartan3E with targeted device as

xc7a30t-3csg324 and was simulated and synthesized using ModelSim and Xilinx. The design layout is presented

integrating all the components i.e. key generation module, substitution box, round operation and top module of the

algorithm. After this the next step after simulation and synthesis is floor planning which provides the hardware design

for the proposed pipelined approach in the AES algorithm (figure 4)

Figure 2: RTL on system Schematic (.ngr file)

AdvanceEncryptionStandard_Module

AdvanceEncryptionStandard_KeyExpansion

AdvanceEncryptionStandard_Roundconst

Plain Text or Cipher

Text (128 Bit)

Cipher Text (128

Bit)


February - 2013, pp. 18-25


Figure 3: Technology on system Schematic (.ngc file)

Figure 4: Layout of AES system chip

C. WAVEFORMS(FUNCTIONALITY)

Figure 5: Encryption waveform

Figure 6: Decryption waveform


February - 2013, pp. 18-25


VI. BRIEF INTRODUCTION OF X-TEA

X-tea is extended tiny encryption algorithm as the name suggests it is the extended version of tiny encryption algorithm

which operates on 64 bit block and key size can range from 64 to 128 bit usually but then it depends on the designer of

the algorithm. It was proposed to eliminate some deficiency that made tiny encryption algorithm insecure. It was

originally invented by David wheeler and roger Needham during 1997. It is popular cryptographic algorithm since it

was designed to keep in mind the code complexity and code size. Also in comparison to AES which utilizes s-box for

providing efficient security level but also it increases the complexity of the system and hence as shown above in the

table 2 that it consumes 8% of LUT’s. So we have to re-design the approach in which we can eliminate the use of

substitution box since it consumes maximum amount of memory space and secondly achieving significant level of

security in small applications. Keeping in mind all the constraints we have to re-design all the components so that we

can make efficient utilization of operations and provide optimization in terms of memory space consumed, security and

complexity[5][10].

VII. COMPONENTS OF X-TEA

In this paper we will be covering all the components that will be helpful in designing the digital design. Since it is the

components which will help in achieving the optimizations in terms of memory space, complexity in terms of lines of

code and security. X-tea has feistel like routine which utilizes operations like XOR, adders, subtractors etc. First design

component is adder which will be utilized in the process of encryption. Adders are critical components since they are

responsible for faster computation there are different types of adders which are there like basic addition, by default ripple

carry adder is used but to increase the speed of computation we have to look beyond the default adder, different types of

adders that are available are large in number, it depend on the algorithm requirements we have to select the same. Some

of them are Multiplexer-based carry select adder, sequential adder, carry look ahead, binary adder and many more.

Another adder which is known for its faster computation can be utilized with the X-tea approach that is Kogge-stone

adder [9],[10].

A. KOGGE-STONE ADDER VLSI IMPLEMENTATION

Kogge-stone adder encompasses the complexity of O (log n) time and from diverse investigation it was analysed that is

called as the faster adder in terms of computation. This adder is a level-wise adder which is designed in a top-down

manner starting with the top module and ending with the leaf node, it has been designed using hardware description

language as verilog. [9].The design of 8-bit Kogge-stone adder is formulated and designed as follows

Figure 7: Kogge-stone adder RTL Schematic (.ngr file).

Figure 8: Kogge-stone technology Schematic (.ngc file)


February - 2013, pp. 18-25


B. WAVEFORM(FUNCTIONALITY)

Figure 9: Waveform for functionality of adder

C. OTHER COMPONENTS

Apart from adder other critical design is the design for encryption and decryption round. In previous work the encryption

and decryption logic is defined separately but since our criteria for optimization is memory area chip size, so we in future

we have to design in such a manner that will ensure security simultaneously utilizing the memory area chip efficiently.

The third design is the flow of data within the encryption and decryption routine which utilizes the function of xor

operation. The logical function used in the algorithm uses a predefine delta value each cycle in the routine takes up the

value, the delta value which is incorporated depends on the number of rounds and is used in key scheduling routine.

Different values of delta are used in different rounds providing the security in comparison to AES security was achieved

using substitution box. The default delta value which is used is rounded number i.e. 2654435769. This number in

hexadecimal format is 0×9E3779B9 [5][6][10].

Some functions which are used in the algorithm are defined below Sub key generation depends on the designer

which can take the key bit ranging 64 bit to 128 bit. Key partition help in deciding which sub key to be used for

encryption routine and which sub key to be used for decryption routine. This is the default value used in the initiation of

the algorithm. This value is derived from the below mathematical equation

Delta Formula (δ) = [(161÷72) -1] × 231

Function_f = [(f<<4^f>>5) + f] ^ Function_z

Function_z = δ value + sub key function.

VIII. CONCLUSION

This paper provides the on system chip design and implementation using fast encryption algorithm, advance encryption

standard. In comparison to previous algorithms i.e. DES, 3DES etc, it was found that AES is much secure since it utilizes

substitution box for security purposes and for large applications. This paper also highlights the benefits of light weight

cryptographic algorithm like X-tea, in terms of the operations used with the AES and provides that X-tea since its small

in size and it is used for mobile applications it can be integrated with other cryptographic algorithms depending upon the

requirements and design constraints, Secondly it provides the VLSI verilog design implementation of 8-bit Kogge stone

adder which is known for its faster computation and can be beneficial while implementing X-tea or any other

cryptographic algorithm

IX. RECOMMENDATIONS FOR FUTURE WORK

What we would recommend for our future work Firstly, is that to utilize this 8-bit adder as discussed above in the

implementation of x-tea. Secondly, since there are not many hardware design implementation of light weight

cryptographic algorithm such as x-tea, the designers of the same can change and revise the approach my moving to a

fully pipelined design architecture that will increase the performance secondly within the same structure encryption and

decryption design should be implemented in order to utilize the memory space. Thirdly delta function which is defined

by default and is the key component in the design of X-tea can be user defined so that delta function is kept hidden along

with the key leading to more security. Since the motivation of x-tea comes from the survey of many researchers in terms

of its size, simplicity and less complexity. Lastly, in future it can be used in providing multi-encryption approached on

FPGA’s.

REFERENCES

[1] Rashi Kohli, Divya Sharma,Manoj kr.Baliyan “S-Box Design Analysis and Parameter Variation in AES

Algorithm“International Journal of Computer Applications (0975 – 8887) Volume 60– No.2, December 2012.

[2] M. Kosaraju, varanasi murali, P.Mohanty saraju , “A high performance VLSI Architecture for Advance

Encryption Standard (AES) algorithm”, 1063-9667/06 (IEEE).


February - 2013, pp. 18-25


[3] Liberatori monica, otero Fernando, Bonadero J.C, Castineira,” AES_128 cipher, high speed, low cost FPGA

implementation” [1-4244-0606-4/07].

[4] AL-Qudah Ibrahim mohammad, DOA, “New S-box design of advance Encryption standard (AES)” Computer

Science, Ministry of High Education, Ryiahd Saudi Arabia.

[5] Steven M. Aumack, Michael D. Koontz Jr. “Hardware Implementation of XTEA”

[6] Jens-Peter Kaps Volgenau School of IT&E, George Mason University, Fairfax, VA, USA [email protected]

Chai-tea, Cryptographic Hardware Implementations of XTEA”

[7] Derek Williams, CPSC6128-Network security, Columbus State University, April 2008,”The Tiny Encryption

Algorithm (TEA).

[8] Edi Permadi, President university, electrical engineering 2005,“The implementation of Tiny encryption

algorithm (TEA) on PIC18F4550 microcontroller”

[9] Hoang Q. Dao and Vojin G. Oklobdzija Advanced Computer System Engineering Laboratory Department of

Electrical and Computer Engineering University of California, Davis, CA 95616,”Performance Comparison of

VLSI Adders Using Logical Effort”

[10] Niladree De, JaydebBhaumik , “A Modified XTEA” International Journal of Soft Computing and Engineering

(IJSCE) ISSN: 2231-2307, Volume-2, Issue-2, May 2012.

[11] GeorgeN.Selimis∗,Athanasios P. Kakarountas, Apostolos P. Fournaris, Athanasios Milidonis, and Odysseas

Koufopavlou, Department of Electrical and Computer Engineering,University of Patras, Greece, 26110”A Low

Power Design for Sbox Cryptographic Primitive of Advanced Encryption Standard for Mobile End-Users”

Journal of Low Power Electronics Vol.3, 1–10, 2007.

[12] PanuHämäläinen, TimoAlho, MarkoHännikäinenand TimoD.Hämäläinen Tampere,“Design and Implementation

of Low-area and Low-power“ University of Technology / Institute of Digital and Computer Systems P. O. Box

553, FI-33101, Tampere, Finland

Rashi Kohli [1]

is an M.Tech student in the department of Computer science & Engineering, ASET,

Amity University, Uttar Pradesh. She received her B.Tech degree in Information and Technology from

Amity University, India. Her research interests include Cryptography, network security and software

engineering domain.

Mr. Manoj Kumar [2]

, currently working as an Assistant Professor in the department of

Computer science & Engineering, ASET, Amity University, Uttar Pradesh, India He has received

degrees in M.Sc, M.Tech & PG Diploma. His research interests include Network security,

Embedded systems & Algorithm design.

optimized on system analysis using aes and...

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