optimal design of bidirectional pfc rectifiers and

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Optimal Design of Bidirectional PFC Rectifiers and Inventers Considering 2L and 3L Topologies with Si, SiC, and GaN Switches

J. Wyss, J. Biela

Power Electronic Systems Laboratory, ETH Zürich Physikstrasse 3, 8092 Zürich, Switzerland

mailto:[email protected]

IEEJ Journal of Industry ApplicationsVol.8 No.6 pp.975–983 DOI: 10.1541/ieejjia.8.975

Paper

Optimal Design of Bidirectional PFC Rectifiers and InvertersConsidering 2L and 3L Topologies with Si, SiC, and GaN Switches

Jonas Wyss∗a)Non-member, Jurgen Biela∗ Non-member

(Manuscript received July 17, 2018, revised June 12, 2019)

Power factor correction converters are widely used in industrial drive systems. Several different configurations andtopologies exist for such converters and it is difficult to choose one. Therefore, in this work, a comprehensive selectionof possible configurations are optimized and compared against each other. The analysis shows the important aspects ofconverter design and how the semiconductor technology used (Si, SiC, and GaN) affects the total converter volume. Asensitivity analysis of certain power semiconductor parameters is performed to highlight the benefit of possible futuredevelopments of components and materials. In addition, the differences between the rectifier stage, where an electro-magnetic interference filter stage is necessary, and the inverter stage, where the harmonic motor losses are influencedby the modulation scheme, are presented.

Keywords: three-phase system, modulation strategy, power factor correction, EMC/EMI

1. Introduction

In industrial drive systems, bidirectional 3-phase boostPower Factor Correction (PFC) converters are widely usedto supply electrical motors via a DC link from the mains(Fig. 1). The main goal of the converter is a power flow inboth directions (i.e. accelerating and decelerating the motor).

The PFC rectifier has to ensure a high power factor andhas to comply with harmonic regulations at low frequencies( f ≤ 700 Hz, LF) and electromagnetic interference (EMI)regulations at high frequencies (150 kHz ≤ f ≤ 30 MHz,HF) (1). Applying a suitable modulation scheme with a suf-ficiently high switching frequency ensures that the rectifiercomplies with the LF regulations. However, the HF noisehas to be attenuated by an additional EMI filter, which has aconsiderable impact on the converter volume (2).

The design of a PFC rectifier can be focused on various as-pects, for example on the EMI filter (3), the switching losses (4)

or the common mode (CM) voltage generation (5). However,if the focus is only set on one of these aspects, it could worsenother aspects and the overall system design. Therefore, acomprehensive converter optimization analyses the impact ofthe topology and the modulation scheme on the total con-verter volume (i.e. the volume of the EMI filter, boost induc-tor, heat sink and DC link capacitors), including an analysisof the benefit of using SiC semiconductors (6). Also the ben-efit of using PCB embedded semiconductors has been anal-ysed (7).

In this paper, the analysis will additionally include GaNdevices and a sensitivity analysis on several semiconductorparameters to investigate the benefit on the system level ofpossible future developments of components and materials.

a) Correspondence to: Jonas Wyss. E-mail: [email protected]∗ Laboratory for High Power Electronic Systems, ETH Zurich,

Physikstrasse 38092, Zurich, Switzerland

Fig. 1. In a drive system the DC link is supplied with arectifier from the mains, while the inverter generates thedesired motor voltage out of the DC link. The topologiesare described in Sect. 2.1

For the EMI filter, different damping topologies and CM con-figurations are analysed.

As the inverter stage use similar topologies and modula-tion schemes, the same considerations can be done, exceptfor the EMI filter which is not necessary. However, not onlythe semiconductor losses have to be considered, but also theharmonic motor losses that depend on the applied modula-tion scheme (8) and the bearing currents which are a side ef-fect of the generated CM voltage of the converter which cancause bearing failures (9). In this paper an optimization of theinverter will be proposed, regarding the aforementioned as-pects.

Section 2 describes the investigated topologies and modu-lation schemes. In Sect. 3, the EMI filter design is outlinedand Sect. 4 shows the optimization procedure. In Sect. 5, themodels are validated with an experimental boost PFC rectifierand Sect. 6 presents the optimization results.

2. Topologies and Modulation Schemes

The topology and modulation scheme are the major de-sign choices for a PFC converter. A controller sets an LFreference voltage of Vconv in the simplified differential mode(DM) equivalent circuit shown in Fig. 2 to ensure the con-trol of bidirectional power (10). The choice of topology and

c© 2019 The Institute of Electrical Engineers of Japan. 975

Optimal Design of Bidirectional PFC Rectifiers and Inverters（Jonas Wyss et al.）

Fig. 2. Differential mode equivalent circuit of a PFCconverter connected to the grid

Fig. 3. Investigated topologies: (a) 2-level, (b) 3-levelT-Type and (c) 3-level Neutral Point Clamped

modulation scheme does not affect this LF voltage and there-fore the controllability, but only the HF spectrum of the con-verter voltage, which has to be attenuated by the EMI fil-ter (Sect. 3). In Sect. 2.1, the investigated topologies are pre-sented, followed by Sect. 2.2 with an overview of the investi-gated modulation schemes.2.1 Topologies Figure 3 shows the investigated

topologies. The respective advantages and disadvantages arediscussed in the following.2.1.1 2-level The 2-level (2L) topology offers low

conduction losses and low costs as the amount of power semi-conductors is small. The disadvantage are high switchinglosses, only two voltage levels which affects the EMI filtervolume considerably and a high power loss per power semi-conductor device.2.1.2 3-level Neutral Point Clamped The 3-level

Neutral Point Clamped (3L-NPC) topology has the lowestswitching losses and a good loss distribution among thepower semiconductor devices. The three voltage levels leadto a smaller EMI filter compared to the 2-level topology. Thedisadvantage are high conduction losses as there are alwaystwo power semiconductor devices conducting the current.2.1.3 3-level T-Type The 3-level T-Type (3L-TT)

topology is a compromise between a 2-level topology anda 3-level NPC topology. The conduction losses are lowercompared to the NPC topology as sometimes only one powersemiconductor device is carrying the current, but the switch-ing losses are higher as the switches S 1/S 4 have a higher volt-age rating than in the NPC topology.2.2 Modulation Schemes Depending on the chosen

topology, different modulation schemes can be applied. Fig-ure 4 shows the space vector plane of a 2-level converter andsector I of a 3-level converter are shown. For the examplegiven in Fig. 4(a) the space vectors (pnn), (ppn), (ppp) and(nnn) would be used. As the space vectors (ppp) and (nnn)generate the same DM voltage, the distribution of the dutycycle between these two space vectors is a degree of freedom

(a) (b)

Fig. 4. (a) 2-level space vector plane, (b) sector I of the3-level space vector plane

Fig. 5. Generated peak DM voltage of the converter atthe switching frequency for different modulation schemes

for the modulation scheme. For the 3-level converter evenmore degrees of freedom are present. In the following theinvestigated modulation schemes are shortly described in thespace vector modulation (SVM) and the advantages and dis-advantages are outlined.2.2.1 2L Sinusoidal In the 2L Sinusoidal (2L-Sin)

modulation scheme, the phase voltages follow a sinusoidalreference (11). Translated into the SVM , the distribution ofthe space vectors (ppp) and (nnn) is chosen so that the aver-age CM voltage over a switching period is zero. The maindisadvantage of this modulation scheme are the high switch-ing losses.2.2.2 2L Clamping In the 2L Clamping (2L-C) mod-

ulation scheme, the phase with the highest current is clampedto either positive or negative DC link voltage during oneswitching period (11). For the example reference vector givenin Fig. 4(a) and for the assumption that phase 1 has the high-est current, space vector (nnn) would be omitted. On onehand this reduces the switching losses considerably, on theother hand the DM peak at the switching frequency is higherthan in the 2L-Sin modulation scheme (cf. Fig. 5), thereby in-creasing the EMI filter.2.2.3 3L Sinusoidal Similar to the 2L-Sin modu-

lation scheme, in the 3L Sinusoidal (3L-Sin) modulationscheme the phase voltages follow a sinusoidal reference andno CM voltage below the switching frequency is generated.However, the neutral point current inp (cf. Fig. 3) is not ac-tively balanced, why a relatively big DC link capacitor is re-quired (6).2.2.4 3L Optimal Clamping In the 3L Optimal

Clamping (3L-OC) modulation scheme, the phase with thehighest current is clamped, thereby reducing the switchinglosses (4). The disadvantage is the generation of a CM voltagebelow the switching frequency, a high DM peak at the switch-ing frequency (cf. Fig. 5) and an unbalance of the neutral

976 IEEJ Journal IA, Vol.8, No.6, 2019


point of the DC link, resulting in a big DC link capacitor (6).2.2.5 3L Clamping In the 3L Clamping (3L-C) mod-

ulation scheme, a controller for the neutral point voltage ofthe DC link decides if the phase with the highest or thesecond-highest current is clamped (12), as these two possibil-ities either charge or discharge the neutral point of the DClink. Compared to the 3L-OC modulation scheme, the DClink capacitor volume is reduced at the price of increasedswitching losses.2.2.6 3L Neutral-Point Balanced In the 3L Neutral-

Point Balanced (3L-NPB) modulation scheme, the averagecurrent to the neutral point of the DC link inp (cf. Fig. 3) iscontrolled to zero in the average of a switching period (12). Theswitching losses are higher compared to the 3L-OC and 3L-Cmodulation scheme, but due to the DC neutral point balanc-ing the DC link capacitor is smaller and the lower DM peak(cf. Fig. 5) reduces the EMI filter volume.

Based on the chosen topology and modulation scheme incombination with the EMI filter respectively the motor, thevoltage and current forms can be calculated. For the recti-fier, the EMI filter design (explained in Sect. 3) is optimizedwith respect to the total converter volume (cf. Sect. 4.1). Forthe inverter, the harmonic losses of the motor and the powersemiconductor losses are evaluated as explained in Sect. 4.2.

3. EMI Filter

At the grid connection of the rectifier stage, the current hasto be filtered in order to fulfill the EMI regulations. Section3.1 describes the standards which are considered, Sect. 3.2shows the investigated damping topologies for the DM fil-ter and in Sect. 3.3 the investigated CM filter topologies areshown.3.1 EMI Standards The EN 61000-3-12 standard is

used for the LF and total harmonic distortion limits, whilethe CISPR 11 class A standard is used for the HF limits. Inbetween, a logarithmic linear function is used as a standardin this medium frequency (MF) range could be expected inthe future (1). Figure 6 shows the applied limits.

Generally, the DM filter consists of a LCL structure as in-dicated in Fig. 7 in the equivalent circuit for one phase. Onetrade-off in the filter design is the value of the boost induc-tance Lb: The higher it is, the higher the boost inductor vol-ume becomes and the lower the other filter elements becomeand vice versa and is therefore optimized as explained inSect. 4.1. The resonance frequency

ω0 =1√LfCf

· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (1)

would lead to an unstable behaviour of the converter, there-fore a damping network is required as explained in the nextsection.3.2 Damping Topologies To avoid that the EMI fil-

ter affects the converter control, Middlebrook’s stability cri-terion (13) (14) has to be fulfilled, i.e. the filter output impedancehas to be smaller than the converter input impedance. Thecriterion has been extended to 3-phase systems (10). Figure 8shows the investigated damping topologies. These dampingtopologies have been analysed and it has been shown that thevolume of the parallel-RL damping (Fig. 8(b)) leads alwaysto a smaller volume than the serial-RL damping (Fig. 8(d)),

Fig. 6. EMI limits used as boundary in this paper

Fig. 7. General structure of the DM filter for one phase

Fig. 8. Passive damping filter topologies: (a) Serial-RC damping, (b) Parallel-RL damping, (c) Parallel-RCdamping and (d) Serial-RL damping

Fig. 9. CM equivalent schematic of a three-phase boostPFC converter. The points A and B can be connected withA1 / A2 respectively B1 / B2

while serial-RC and parallel-RC (Fig. 8(a) respectively c)lead to the same volume (15). Therefore, only the parallel-RCand the parallel-RL damping are considered in this paper.3.3 CM Filter Topologies Figure 9 shows the CM

equivalent circuit of a three-phase boost PFC converter. TheCM voltage source Vconv,CM depends on the chosen topol-ogy and modulation scheme. Cg is the equivalent capacitancefrom the two DC link poles to ground and Csc is the parasiticcapacitance from the power semiconductors to the groundedheat sink. The CM inductor LCM can either be placed on thegrid or the converter side. If it is placed on the grid side,there are no HF DM currents which would generate addi-tional losses. On the other hand if it is placed on the converterside, the CM damping is higher. The CM capacitor CCM caneither be connected with the neutral point of the DC link orwith ground. Therefore, four configurations are investigated:3.3.1 CM Filter Topology 1 LCM is placed on the

grid side (A-A2) and CCM is connected to the DC link mid-point (B-B1).



Fig. 10. Example configuration with a 3-level TT topol-ogy, a DM filter with parallel-RL damping and CM filtertopology 1

3.3.2 CM Filter Topology 2 LCM is placed on theconverter side (A-A1) and CCM is connected to the DC linkmidpoint (B-B1).3.3.3 CM Filter Topology 3 LCM is placed on the

grid side (A-A2) and CCM is connected to ground (B-B2).3.3.4 CM Filter Topology 4 LCM is placed on the

converter side (A-A1) and CCM is connected to ground (B-B2).3.4 Example Configuration Figure 10 shows the 3-

phase equivalent circuit of the experimental setup in Sect. 5.It consists of a 3-level TT topology, a DM filter with parallel-RL damping and CM filter topology 1.

4. Optimization Procedure

Based on the chosen topology and power semiconductordevices, modulation scheme, damping topology and CM fil-ter topology, the design parameters of the converter are op-timized for maximal power density in order to derive thedependency of the converter volume on the switching fre-quency. Section 4.1 describes the optimization routine for therectifier stage and Sect. 4.2 for the inverter stage. In Sect. 4.3the volume estimation for the different converter componentsis explained.4.1 Rectifier Optimization Procedure The consid-

ered optimization procedure shown in Fig. 11 has been pre-sented in a previous work (15) and is used to identify theswitching frequency and CM and DM filter design param-eters which lead to the lowest converter volume. The input ofthe optimization is the system specification which includesthe AC and DC voltage, the output power, the inductor andcapacitor materials and the topology including semiconduc-tor devices and modulation scheme. For reducing the com-puting time, the optimization routine is implemented in a cas-caded structure. The following DM filter design parametersare optimized:

( 1 ) The boost inductance value Lb (trade-off betweenboost inductor volume and filter volume).

( 2 ) The filter resonance frequency ω0 (trade-off be-tween filter volume and attenuation).

( 3 ) The frequency location of the maximum filter out-put impedance ωm (trade-off between damping capa-bility and volume of the damping element).

( 4 ) The maximum value of the filter output impedanceZm (trade-off between inductor and capacitor volumeof the DM filter).

In addition, the following CM filter design parameters areoptimized:

( 1 ) The CM filter resonance frequency ωcm (trade-offbetween filter volume and attenuation).

Fig. 11. Flowchart of the cascaded procedure to opti-mize the boost PFC rectifier for minimal volume (6)

( 2 ) The maximum value of the CM filter outputimpedance Zcm (trade-off between inductor and capac-itor volume of the CM filter).

Besides the EMI filter parameters, also the switching fre-quency fs is varied (trade-off between volume of the passivecomponents, i.e. EMI filter and DC link capacitor, and heatsink volume).4.2 Inverter Optimization Procedure The opti-

mization for the inverter which is based on the procedure forthe rectifier is shown in Fig. 12. In contrast to the rectifier op-timization, no EMI filter has to be optimized. However, theharmonic motor losses are estimated as they are affected bythe applied modulation scheme. They can be estimated via apower loss curve, defined by

Pmotor,harmonic =∑

V2n ·⎛⎜⎜⎜⎜⎝

Af αn+

B

f βn

⎞⎟⎟⎟⎟⎠ · · · · · · · · · · · · · · · (2)



Fig. 12. Flowchart of the procedure to optimize the mo-tor inverter for minimal volume

where the high-frequency iron and copper losses are esti-mated via the experimentally derived parameters A, B, α andβ (16).4.3 Volume Estimation If a converter design com-

plies with the EMI standards, the volumes of the various com-ponents are estimated (step 6 of Fig. 11). The capacitor vol-ume is estimated with (15)

VC = k1 ·CV2 + k2(V). · · · · · · · · · · · · · · · · · · · · · · · · · · (3)

The parameters k1 and k2 differ for the different capacitortypes (DC link, DM filter, CM filter capacitor) and are shownin Appendix 1. The inductor volume is estimated with (15)

VL = k1 ·(LI2) 3

4+ k2 · LI2. · · · · · · · · · · · · · · · · · · · · · · · (4)

The parameters k1 and k2 are based on an inductor optimiza-tion (15) and are shown in Appendix 1 for the different inductortypes (boost, DM filter and CM filter inductor).

The conduction and switching losses of the power semi-conductors are calculated based on datasheet values. For the3L-TT topology (cf. Fig. 3(b)) the switching losses have beenscaled to the lower operating voltage. In addition, the switch-ing losses differ from the data sheet as a diode with a lowervoltage rating is used for the transition of the current. Thedatasheet curves have been adjusted linearly based on mea-sured switching losses (17). The maximum allowed heat sinktemperature is

Ths = min(Tsc − Pchip,i · Rth,i), i = 1...N, · · · · · · · · · · · (5)

where Tsc defines the maximal allowed junction temperature.Pchip,i is the power loss of a single chip, Rth,i its correspond-ing thermal resistance from junction to heat sink (includingan insulation foil between semiconductor case and heat sink)and N defines the number of semiconductors mounted on theheat sink. The heat sink is assumed to have a Cooling Sys-tem Performance Index (18) CSPI = 10 W K−1 dm−1 (forced aircooling) and therefore the volume can be calculated with

Vhs =

∑Pchip

CSPI · (Ths − Tamb). · · · · · · · · · · · · · · · · · · · · · · · (6)

Fig. 13. Prototype of a bidirectional 30 kW boost PFCrectifier with an input of 3 x 230 V AC, an output of 800 VDC and a volume of 13.8 dm3

Fig. 14. Measurement results of the prototype shown inFig. 13 with Vac = 230 V, Vdc = 750 V and P = 15 kW

5. Experimental Setup

To verify the models used to calculate the currents and volt-ages of the rectifier system and the maximum estimation ofan EMI test receiver, a 30 kW prototype as shown in Fig. 13has been built. Figure 14 shows the input voltages and cur-rents as well as the output voltage and current with a 15 kWload. Note that there is a 5th and 7th harmonic in the volt-age input waveforms. This causes a 5th and 7th harmonic inthe grid current of the converter but still meets the grid reg-ulations. The critical frequency range is shown in Fig. 15,where the EMI measurements are compared to the model.The model predicts the maximum estimation of the test re-ceiver with a good accuracy and the MF limits are met. In theMHz-range, the HF limits are violated, which could be cor-rected by a proper HF design of the converter components,which is not the scope of this work.

6. Comparative Evaluation

The optimization procedures described in Sect. 4 havebeen applied to a wide variation of topologies, modulationschemes, DM and CM topologies. The optimizations areperformed for the rectifier stage (Sect. 6.1) as well as for theinverter stage (Sect. 6.2). Furthermore, a sensitivity analy-sis of the volume on the power semiconductor parameters is



Fig. 15. Measurement of the EMI test receiver ESIB7compared to the model. Vac = 230 V with a LISN NNB-4/200 inserted, Vdc = 750 V without a load

Table 1. Assumptions and constraints for the optimiza-tion procedure

Ambient temperature Tamb 55 ◦C

Maximal junction temperature Tsc 125 ◦C

Heat sink CSPI 10 W K−1dm−1

Maximal inductor surface temperature Tind 80 ◦C

Grid voltage Vac 230 V

Grid frequency fn 50 Hz

Rectifier power Prect 30 kW

DC link voltage Vdc 800 V

Motor voltage VM 170 V

Motor stator inductance Ls 3.05 mH

Motor stator restistance Rs 104 mΩ

Motor power PM 22.5 kW

performed in Sect. 6.3. Table 1 shows the assumptions andconstraints of the optimization procedure. Note that chang-ing these parameters would change the results. However, theoptimization can be used for various parameters and the ex-ample provided in this paper gives a guideline which config-urations of the converter are the most promising ones.

With this volume estimation equations the total volume ofthe converter can be optimized. The corresponding resultsare shown in Sect. 6.6.1 Rectifier Optimization The results for the rec-

tifier stage are divided in different categories: In Sect. 6.1.1,the focus is put on the investigated modulation schemes. Sec-tion 6.1.2 analyses the impact of the chosen DM dampingtopology while Sect. 6.1.3 focuses on the CM topologies. Fi-nally, in Sect. 6.1.4 the total rectifier volume for the differentsemiconductor technologies is analysed.6.1.1 Modulation Scheme Comparison Figure 16

shows the heat sink, DC link capacitor and EMI filter vol-ume as a function of the switching frequency for the inves-tigated modulation schemes. For this comparison, Si IGBTsare assumed and for 3L only the NPC topology is consid-ered. The heat sink volume explains why with 2L topolo-gies only a moderate switching frequency can be achieved.The DC link capacitor volume reveals the disadvantage ofthe 3L-OC modulation scheme: The volume is relatively big

Fig. 16. Heat sink, DC link capacitor and EMI filter vol-ume depending on the switching frequency for differentmodulation schemes (cf. Sect. 2.2). Si IGBTs are as-sumed and for 3L the NPC topology is considered. TheDM filter is built with a parallel-RL damping topologyand CM filter topology 1

Fig. 17. EMI filter volume depending on the switch-ing frequency for different DM damping topologies (cf.Sect. 3.2) and modulation schemes (cf. Sect. 2.2). For 3Lthe TT topology is considered and the CM filter is builtwith topology 1

and does not decrease with a higher switching frequency, asthe average neutral point current over a switching period isnon-zero. The EMI filter volume shows that for the sameswitching frequency, the EMI filter volume of the 3L-NPBmodulation scheme is lower than the one for other modula-tion schemes, as was predicted by the DM peak voltage (cf.Fig. 5).

To summarize, the 3L-NPB modulation scheme results inthe smallest volume, due to the advantage of both a small DClink capacitor and a low EMI filter volume, which compen-sate for the higher switching losses compared to the clampingmodulation schemes.6.1.2 Damping Topology Comparison Figure 17

shows the EMI filter volume for different damping topolo-gies (cf. Sect. 3.2) and modulation schemes depending on theswitching frequency. Si IGBTs, SiC Power MOSFETs andGaN transistors are considered for all modulation schemesand combined together to get a wide switching frequencyrange. The results show that the preferred damping topology



Fig. 18. EMI filter volume depending on the switchingfrequency for different CM topologies (cf. Sect. 3.3). The3L-NPB modulation scheme is applied for a 3L TT topol-ogy using GaN transistors. For the DM filter a parallel-RL damping topology is used

Fig. 19. Total converter volume depending on theswitching frequency for different semiconductor tech-nologies. For the 3L topologies the 3L-NPB modulationscheme is applied while for the 2L topology the 2L-OCmodulation scheme is applied. A parallel-RC dampingtopology for the DM filter and CM filter topology 1 isused

depends on the modulation scheme and switching frequency.The lowest EMI filter volume can be achieved with the 3L-NPB modulation scheme and a parallel-RC damping topol-ogy.6.1.3 Common Mode Topology ComparisonFigure 18 shows the EMI filter volume depending on the

switching frequency for different CM filter topologies (cf.Sect. 3.3). It can be seen that it is advantageous to place theCM inductor at the grid side (topology 1 and 3) as otherwisethe HF harmonics of the DM current cause additional lossesin the windings of the CM inductor and therefore would in-crease its volume. It is also advantageous to connect the CMcapacitor to the DC link neutral point (topology 1 and 2),which has the additional benefit to reduce the currents to pro-tective earth.6.1.4 Semiconductor Technology Comparison In

Fig. 19, the total rectifier volume is shown for different semi-conductor technologies and topologies. For the 2L topology,

Table 2. Optimal rectifier design with correspondingcomponent volumes

Converter Topology 3-Level NPC

Modulation Scheme 3L-NPB

Switching Frequency fs 60.9 kHz

Switches VisIC V22N65A

NPC Diodes Infineon IDW30G65C5

Heat Sink 1.1 dm3

DC Link Capacitor Cdc 2 x 14 µF 2 x 17 cm3

Boost Inductor Lb 3 x 412.5 µH 3 x 373 cm3

Filter Inductor Lf 3 x 30.9 µH 3 x 41 cm3

Filter Capacitor Cf 3 x 9.3 µF 3 x 36 cm3

Damping Capacitor Cd 3 x 14.1 µF 3 x 54 cm3

Damping Resistor Rd 3 x 3.2 Ω

CM Inductor LCM 304.3 µH 60 cm3

CM Capacitor CCM 6.2 µF 56 cm3

Total Volume 2.8 dm3

Fig. 20. Volume distribution of the optimal rectifier de-sign

the 2L-OC modulation scheme is applied and for the 3Ltopology the 3L-NPB modulation scheme, according to theresults in Sect. 6.1.1. For the damping topology, a parallel-RC topology is chosen (cf. Sect. 6.1.2) and the CM filter isbuilt with CM topology 1 (cf. Sect. 6.1.3). The 2L topologywith Si IGBTs could not be seen on the graph as the volumeis very high - around 9 dm3. Either a change to new semicon-ductor technologies or a change to a 3L topology reduces therectifier volume significantly. If both measures are combined,the rectifier volume is reduced further. The 3L NPC topologyleads to the smallest volume. GaN semiconductor devicesprove to be the best choice, as the switching frequency canbe raised considerably, thereby reducing the volume of theEMI filter.

Keep in mind that the difference between the TT and NPCtopology heavily depends on the used semiconductor devices(cf. Appendix 1).6.1.5 Optimal Rectifier Design Table 2 shows the

components and their volume for the optimal rectifier design,which has a total volume of 2.8 dm3. Figure 20 shows thevolume distribution of the converter. It can be seen that theheat sink and the boost inductors have the biggest share of thetotal rectifier volume. The EMI filter share (without the boostinductor) is approximately 20% of the total rectifier volume.6.2 Inverter Optimization The results for the



Fig. 21. Total inverter volume depending on the switch-ing frequency for different topologies, modulationschemes and semiconductor technologies

Fig. 22. Harmonic motor losses (2) depending on theinverter volume for different modulation schemes. SiCMOSFETs are considered. The parameters for the har-monic motor losses are A = 0.019, B = 0.0045, α = 1.5and β = 0.35

inverter optimization are shown in Fig. 21 and 22. In con-trast to the rectifier stage, there are less passive componentswhich would benefit from a high switching frequency and alow DM voltage peak. This leads to three observations:

( 1 ) The 3L TT topology is preferred to the 3L NPCtopology as the conduction losses are lower.

( 2 ) The 3L-C modulation scheme is preferred to the 3L-NPB modulation scheme as the lower switching lossesoutvalue the disadvantage of a higher DM peak volt-age, as there is no EMI filter.

( 3 ) The considered SiC MOSFETs perform better thanthe GaN transistors as they result in lower conductionlosses.

An additional benefit of the 3L topologies can be seen inFig. 22: Due to the smoother output voltage, the harmoniclosses of the motor can be considerably reduced. Further-more, as the voltage steps of the winding voltages are re-duced, the voltage stress on the insulation is reduced and theCM currents (which result in bearing currents) are reduced.6.2.1 Optimal Inverter Design Table 3 shows the

components and their volume for the optimal inverter design,

Table 3. Optimal inverter design with correspondingcomponent volumes

Converter Topology 3-Level TT

Modulation Scheme 3L-C

Switching Frequency fs 9 kHz

Switches 1200 V Cree C2M0025120D

Switches 600 V Microsemi APT130SM70B

Heat Sink 678 cm3

DC Link Capacitor Cdc 2 x 74.9 µF 2 x 70 cm3

Total Volume 818 cm3

Fig. 23. Volume reduction for different semiconduc-tor improvements: reduced thermal impedance, reducedconduction losses or reduced switching losses

which has a total volume of 818 cm3. The ratio of heat sinkto DC link capacitors is 83:17.6.3 Sensitivity Analysis For all semiconductor tech-

nologies, different characteristics have been varied to ana-lyze their impact on the total converter volume of the rec-tifier stage. A 3L NPC topology is considered and a 3L-NPBmodulation scheme is applied. For the DM filter, a parallel-RC damping topology is considered and the CM filter is builtwith CM topology 1. Either the thermal impedance, the con-duction losses or the switching losses have been reduced by50%. The resulting volumes are shown in Fig. 23. As canbe seen the biggest impact on the total converter volume iscaused by reduced conduction losses, as these are the domi-nant semiconductor losses.

7. Conclusion

In this paper, various modulation schemes, topologies andEMI filter designs are analysed and compared against eachother for bidirectional boost PFC rectifiers as well as invert-ers in terms of the volume. The 3L NPC topology has beenshown to be the best topology for the rectifier stage, whilefor the inverter stage, the TT topology is to be the preferredone as the conduction losses are dominant there. For thesame reason, GaN transistors are preferred for the rectifierstage, while SiC MOSFETs are advantageous for the inverterstage. In future research, the optimization of the rectifier andinverter stage could be combined to optimize the completedrive system.

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Appendix

1. Material ParametersThe used semiconductor devices are shown in Table 1.

They have been chosen to have similar conduction losses toallow a fair comparison. Note that the current rating given by

app. Table 1. Semiconductors considered in theoptimization

Type Name

Si 1200 V 25 A IGBT Infineon IKW25N120T2

Si 600 V 30 A IGBT Infineon IKW30N65ES5

Si 600 V 30 A NPC Diode Infineon IDW30E65D1

SiC 1200 V 90 A MOSFET Cree C2M0025120D

SiC 600 V 110 A MOSFET Microsemi APT130SM70B

SiC 600 V 30 A NPC Diode Infineon IDW30G65C5

GaN 1200 V 50 A Transistor VisIC VM40HB120D

GaN 600 V 80 A Transistor VisIC V22N65A

app. Table 2. Parameters for estimating the volume ofthe inductors

Component Core Material k1 k2

Lb METGLAS 2605SA1 266 cm3(H−1A−2

) 43 0 cm3H−1A−2

Lf METGLAS 2605SA1 169 cm3(H−1A−2

) 43 64 cm3H−1A−2

LCM Vitroperm 500F 39 cm3(H−1A−2

) 43 15 cm3H−1A−2

app. Table 3. Parameters for estimating the volume ofthe capacitors

Component Series k1 k2

Cf EPCOS B3292x 22.96 cm3F−1V−2 2.24 cm3

CCM EPCOS B3265x 55.54 cm3F−1V−2 0.84 cm3

CDC EPCOS B3277x 4.95 cm3F−1V−2 4.24 cm3

the manufacturers are considerably different despite similarconduction losses. The parameters for estimating the induc-tor and capacitor volumes are shown in Tables 2 and 3.

Jonas Wyss (Non-member) was born in Chur, Switzerland in 1987.He has studied Electrical Engineering at the FederalInstitute of Technology in Zurich, Switzerland (ETHZurich), focusing on drive systems and power elec-tronics. In 2013, he received the master degree. Hismaster thesis dealt with developing a multi-outputrectifier. In April 2013 he joined the High PowerElectronics Laboratory as a PhD student focusing onrectifier systems for drive systems.

Jurgen Biela (Non-member) received the Diploma (Hons.) degreefrom Friedrich-Alexander-Universitaet, Erlangen-Nuernberg, Nuremberg, Germany, and the Ph.D. de-gree from the Swiss Federal Institute of Technol-ogy (ETH) Zurich, Zurich, Switzerland, in 1999 and2006, respectively. He dealt, in particular, with res-onant dc-link inverters with the University of Strath-clyde, Glasgow, U.K., and the active control of series-connected IGCTs with the Technical University ofMunich, Munich, Germany, during his studies. In

2000, he joined the Research Department, Siemens Automation and Drives,Erlangen, Germany, where he was involved in inverters with very highswitching frequencies, SiC components, and EMC. In 2002, he joined thePower Electronic Systems Laboratory (PES), ETH Zurich, for working to-ward the Ph.D. degree, focusing on optimized electromagnetically integratedresonant converters. From 2006 to 2007, he was a Post-Doctoral Fellow withPES and a Guest Researcher with the Tokyo Institute of Technology, Tokyo,Japan. From 2007 to 2010, he was a Senior Research Associate with PES.Since 2010, he has been an Associate Professor in high-power electronicsystems with ETH Zurich. His current research interests include the design,modeling, and optimization of PFC, dcdc and multilevel converters with em-phasis on passive components, and the design of pulsed-power systems andpower electronic systems for future energy distribution.


optimal design of bidirectional pfc rectifiers and

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