openpiton+arianein action - princeton...

OpenPiton+Ariane in Action

Princeton University and ETH Zürich

http://openpiton.orghttp://pulp-platform.org

http://openpiton.org/

http://pulp-platform.org/

FPGA Prototyping

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Comparison of Supported BoardsDevelopment Board,

FPGA name,Part

Core Clock(1 core)

Max# of Cores(with FPU)

DDR Type,Size,

Data Width

Price (nonacademic/

academic)

Xilinx VC707Virtex-7

XC7VX485T-2FFG1761C60 MHz 3

DDR31 GB

64 bits$3,495

Digilent Genesys2Kintex-7

XC7K325T-2FFG900C67 MHz 2

DDR31GB

32 bits

$999/$600

Digilent NexysVideoArtix-7

XC7A200T-1SBG484C30 MHz 1

DDR3512MB16 bits

$490/$250

Digilent Nexys 4 DDRArtix-7

XC7A100T-ACSG324C30 MHz 1^

DDR2128MiB16 bits

$320/$160

Xilinx VCU118 *Virtex UltraScale+

XCVU9P-L2FLGA2104E100MHz 8

DDR42GB

64bits$6,995

4* experimental ^ no FPU, peripheral IP (test runs from BRAM)

Prototype Architecture

Ariane Core

DRAMSDHCUART

Switches, LEDs

Ethernet

Digilent Genesys2

5

Wishbone SD Master*:• Up to 32GB SD/SDHC cards• Storage for OS/tests

UART:• Terminal I/O• Loading of assembly test(DMW - Direct Memory Write from a host)

DDR controller*:• Xilinx’s MIG IP core• Configurable data width• Used as main memory

*optional

Ethernet controller*:• Xilinx’s Ethernet Lite MAC IP Core• Driver from Linux kernel• 100 Mb/s

JTAG P-M

esh

Cros

sbar

Setup for Hands-on with FPGA

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Setting up Your FPGA Board

GO!14

Suggested ConfigurationsBRAM_TEST SD with OS

+ EthUART DMW

to DDRBRAM with hardwired

test

DRAM memory controller

SD card controller

UART 16550

Ethernet Lite MAC

UART support fortest streaming

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Tools• protosynAll encompassing tool for creation of FPGA project and generating programming file

• pitonstreamTool for running assembly tests on FPGA

Sources are located at piton/tools/src/proto/

pitonstreamboard type, asm test list .ustr

protosynboard type, design, config opt.xpr

.bit

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protosyn Flow

bram test?

*.v.pyv -> *tmp.v

sims build

sims run

RTL

mapping test to BRAM

create project?

mem.imagesims.log

test_proto.coe

project creation .xpr

synthesis

mapping, placing, routing, bitstream generation, STA

NO

YES

implement?

YES

NO

IP cfg (.xci),constraints (.xdc),defines

YES

NO

.xpr

.bit,

.ltx

LegendControl FlowData Flowpyv preprocessorSims scriptVivadoinput/output filesflow step conditions

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Running protosyn

…more options are in FPGA manual

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Example protosyn run

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FPGA Flow Runtimes

• System including DDR controller

– ~1 hour including IP generation

– ~40 mins excluding IP generation

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FPGA Flow Outputs

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FPGA Flow Outputs

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FPGA Flow Outputs

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Hands-on with FPGA

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Booting Linux on OpenPiton+Ariane

• ls /dev/ttyUSB*

• screen /dev/ttyUSB0 115200

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Network Setup

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Use the MAC from your board

Network Setup

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Network Setup

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Running Tetris on OpenPiton+Ariane

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Browse pulp-platform.org and openpiton.orgon OpenPiton+Ariane

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Challenge Each Other!

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• Vitetris Netplay (credits @Victor Nilsson)

• First player needs to wait for connection- ./tetris –listen <port>

• Second player has to connect to specific IP of opponent- ./tetris- Select Netplay- Enter <hostname or IP : port>

• Play!

openpiton+arianein action - princeton...

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