open voltage regulator speci˝cation -...
TRANSCRIPT
OpenVRegOpen Voltage Regulator Specification
Type 2Revision 1.0
November 30, 2011
Contents
1 Introduction 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 OpenVReg Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Electrical Specifications 32.1 Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.4 Required Function Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.5 Optional Function Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 PWM-VID Dynamic Voltage Control - Analog Method 123.1 Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2 Integrating the Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.4 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.5 Voltage Waveform and Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . 183.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Mechanical Specifications 204.1 QFN24 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2 QFN24 PCB Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Environmental Compliance 22
Applicable Documents 23
ii
List of Figures
1.1 OpenVReg Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 OpenVReg Type 2 Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . 42.2 OpenVReg Type 2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.3 Power Saving Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.4 Thermal Alert and Temperature Sensing Circuit Diagram . . . . . . . . . . . . . . . 92.5 Over Voltage and Under Voltage Protection . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Dynamic Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2 PWM-VID Analog Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3 Integrated Buffer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.4 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.5 Illustration for Standby Mode and Adjustable Vboot Setting . . . . . . . . . . . . . . 173.6 Illustration of Voltage Waveform and Propagation Delay . . . . . . . . . . . . . . . . 18
4.1 QFN24 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2 QFN24 PCB Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
iii
List of Tables
1.1 OpenVReg Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Type 2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.2 Description of Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.3 Power Saving Interface Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 82.4 Type 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Dynamic Voltage Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.2 Buffer Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.3 Recommended Component Options . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 QFN24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
iv
Chapter 1
Introduction
OpenVReg is a standard for power management devices targeted primarily at the computing market.This document describes the basic operation, theminimum set of features, the electrical interface and themechanical requirements necessary to implement OpenVReg compliant devices. The current versionof the specification focuses exclusively on DC-DC regulators and controllers. Future version of thespecification may add definition for other types of devices.
1.1 Motivation
To enable package and pinout compatibility acrossmultiple sources of similar devices, OpenVReg definesa single PCB footprint and layout that will be compatible with devices from multiple manufacturers,reducing the risk of a shortage from any one supplier. It also creates an opportunity for all participatingmanufacturers to access sales beyond the initial design phase, which historically locked a project to aspecific manufacturer’s device.
1.2 Overview
OpenVReg addresses different voltage and current requirements by defining several types. Withineach type, one or more subtypes may be necessary to address different usage models (i.e. desktop vs.notebook). Figure 1.1 shows an overview of the devices defined in the current OpenVReg specification.Each type is defined in a separate document as described in Section 1.3.
Compliant devices of the same type and subtype shall have:
q The minimum feature set defined for the specific subtype: devices shall support all the basefeature set.
q Non-conflicting pinout definitions: additional features are allowed but shall not conflict with thebase feature set.
q Circuit compatibility: devices shall function within the predefined reference circuit.
q Common PCB layout: devices shall be compatible with the recommended footprint.
q Mechanically compatible packages: devices shall not exceed the volume defined in the mechanicalspecification.
Note: Device compatibility within the same type and subtype is limited to netlist topology only. Everydevice may have its own Bill of Materials (BOM).
1
Open Voltage Regulator Specification (Type 2 Revision 1.0)
OpenVReg
Specification
Type 0−LV (Vin=3.3−5V)
Type 0−DT (Vin=12V)
Type 2−DT (Vin=12V)
Type 0
(Integrated)
Type 2
(2−phase)
Type 2−BT (Vin=7−20V)
Type 0−BT (Vin=7−20V)
Figure 1.1: OpenVReg Overview
1.3 OpenVReg Devices
The current OpenVReg specification defines two regulator types: Type 0 and Type 2. Table 1.1 showsthe defined devices and their primary application. Future specifications will add additional types toaddress different current ratings. This specification will focus on Type 2.
Table 1.1: OpenVReg DevicesDocument Device Description Primary Application Vin[V]Type 0 0-LV 3A DC-DC converter with integrated mosfets Desktop/Notebook 3.3-5
Type 0 0-DT 3A DC-DC converter with integrated mosfets Desktop 12
Type 0 0-BT 3A DC-DC converter with integrated mosfets Notebook 7-20, Battery
Type 2 2-DT 2-phase DC-DC controller with integrated gate drivers Desktop 12
Type 2 2-BT 2-phase DC-DC controller with integrated gate drivers Notebook 7-20, Battery
2
Chapter 2
Electrical Specifications
OpenVReg Type 2 is a dual phase DC/DC controller. Devices use a mass manufacturing friendly andspace saving 24-pin 0.5mm pitch 4x4mm QFN package. Refer to Section 4.1 for the full mechanicalspecification. Type 2 defines two subtypes targeting different applications:
Type 2-DT
q Standard voltage, fixed input (12V)
q Generic desktop and consumer electronics
Type 2-BT
q Battery voltage, dynamic input( 7-20V)
q Battery operated devices with 3 or more cells battery packs
3
Open Voltage Regulator Specification (Type 2 Revision 1.0)
2.1 Reference Circuit
Figure 2.1 shows a typical application circuit for OpenVReg Type 2.
Opamp Compensation
Driver Supply Voltage
Frequency Selection
Optional
External
Strap 1
Supply Voltage
Thermister GM Amplifier
Strap 2Optional
Compensation
17
18
19
20
10
12
22
2513
14
6
5
4
23
24
1
29
2115
R_HG1
C_BT2
R_TM
2
D
GS
D
GS
D
GS
D
GS
TSNS
COMP
GND
THERM/GND
VSNS
BOOT2
GNDSNS
PGOOD
TALERT#
HGATE2
FS
PVCCVCC
HGATE1
BOOT1
PHASE1
LGATE1
PHASE2
LGATE2
PSI
EN
VREF
REFADJ
VID
REFIN
R_FS2
R_PSI
3V3
VREF
1
3V3
VIN
PVCC
VIN
VIN
L2
R_VGND
R_EN
R2
C5 R3
3
12
Q21
Q33
Q43
12
R_TM
R_VCC
C1
R1 C4
8
R_LG1
11
R_LG2
2R_HG2R_PSI2
R_PG
3
7
R_PVCC
Q1
Type2
R_FS
16
C_PVCC
R_VREF2
R_TA
LERT
R_VREF1
C_VREF
VCC
C_VCC
R_REFADJ
C_REFIN
2
C_BT13
L1
R_VOUT
C3
VGND_SNS
VOUT_SNS
C2
C_VIN1
VOUT
C_VIN2 C_OUT
IN
IN
OUT
OUT
SG
D
SG
D
SG
D
SG
D
IN
OpenVReg
REFIN
VID
REFADJ
VREF
EN
PSI
LGATE2
PHASE2
LGATE1
PHASE1
BOOT1
HGATE1
VCC PVCC
FS
HGATE2
TALERT#
PGOOD
GNDSNS
BOOT2
VSNS
THERM/GND
GND
COMP
TSNS
5
4
3
2
1
A B C D E F G
Figure 2.1: OpenVReg Type 2 Typical Application Circuit
Note 1: Devices in the blue dashed lines are optional and can be unstuffed when not needed.Note 2: Soft start is adjusted by the REFIN capacitor.
4
Open Voltage Regulator Specification (Type 2 Revision 1.0)
2.2 Pinout
1 2 3 4 5 6
7
8
9
10
11
12
141518
19
20
21
22
23
24
17 16 13
25
/GND
THERM
HG
AT
E1
LGATE1
PHASE1
BO
OT
1
EN
LGATE2
PHASE2
BO
OT
2
HG
AT
E2
PG
OO
D
VC
C
COMP
VSNS
GNDSNS
FS
VREF
REFIN
RE
FA
DJ
VID
PS
I
PVCC
GND
TS
NS
TA
LE
RT
#
Figure 2.2: OpenVReg Type 2 Pinout
5
Open Voltage Regulator Specification (Type 2 Revision 1.0)
2.3 Pin Descriptions
Table 2.1 describes the pin list and function for OpenVReg Type 2.
Table 2.1: Type 2 Pin DescriptionsPin Number Pin Name I/O Description
1 BOOT1 I High side gate driver supply of phase 1.
2 HGATE1 O High side gate driver output of phase 1.
3 EN I Enable input.
4 PSI I Power Saving Interface.
5 VID I Voltage ID input. Refer to PWM-VID Dynamic VoltageControl - Analog Method in Chapter 3 and PWM-VIDSpecification for details.
6 REFADJ O Reference adjustment output. Refer to PWM-VID DynamicVoltage Control - Analog Method in Chapter 3 andPWM-VID Specification for details.
7 REFIN I External Reference Input.
8 VREF O Output Reference Voltage. This is a high precision voltagereference.
9 FS I Frequency Selection. Connect a resistor from this pin toGND to select the switching frequency. Connected aresistor from this pin to VIN to select the on time Ton.
10 GNDSNS I GND Sense. Negative node of the remote voltage sense.
11 VSNS I Vout Sense. Positive node of the remote differentialvoltage sense.
12 COMP O Compensation. Use this pin in combination with VSNS tocompensate the feedback loop of the converter.
13 TSNS I Temperature sensing input.
14 TALERT# O Thermal alert. Active low open drain output.
15 VCC I/O Supply Voltage.
16 PGOOD O Open drain power good output.
17 HGATE2 O High side gate driver output of phase 2.
18 BOOT2 I High side gate driver supply of phase 2.
19 PHASE2 I Switch node of phase 2.
20 LGATE2 O Low side gate driver output of phase 2.
21 PVCC I/O Driver Supply Voltage.
22 GND - Ground. Must be connected to GND on PCB. Can be GNDor NC on the regulator.
23 LGATE1 O Low side gate driver output of phase 1.
24 PHASE1 I Switch node of phase 1.
25 THERM/GND - Thermal connection to the PCB. Must be connected toGND on PCB. Can be GND or NC on the regulator.
6
Open Voltage Regulator Specification (Type 2 Revision 1.0)
2.4 Required Function Descriptions
Dynamic Voltage Control Device shall support dynamic voltage adjustment. Refer to PWM-VID Dynamic Voltage Control - Analog Method in Chapter 3 and PWM-VID Specification fordetails to implement this feature.
Protection Device shall shut down and latch when protection is detected. Device shall be protectedfrom shutdown during voltage transitions at REFIN.
Power Good PGOOD output shall ONLY be deasserted low when controller shut down.
Standby Voltage Device shall support an ultra-low output voltage Voutmin.Enable Function A pull up on this pin is necessary to enable the regulator. Forcing this pin below
Enable Low Threshold shuts down the device.Frequency Selection The FS pin is used to determine the switching frequency or on time.
External Compensation External compensation is required. Regulators must be stable with totaloutput capacitor equivalent series resistance (ESR) as low as 1 milliOhm.
Short Circuit Protection (SCP) Device shall be shut down and protected from damage due to ashort across the output. However, a sudden change in load shall not trigger SCP. Manufacturersmay implement this function by Under Voltage Protection (UVP) or other methods.
Power Saving Interface (PSI) This is an multilevel input to support Power Saving features. SeeTable 2.2 for mode descriptions. Devices shall support dual phase with FCCM and single phasewith DCM. . Single phase with FCCM or USM is optional. Controller shall support boot-up tosingle phase mode or dual phase mode by strapping PSI voltage.
Table 2.2: Description of Operating ModesMode DescriptionsDCM Discontinuous Conduction Mode decreases the switching frequency to improve the
efficiency at light load.
USM Ultra-Sonic Mode limits the switching frequency above audible frequency range to avoidthe noise in DCM mode.
FCCM Forced Continuous Conduction Mode does not change the switching frequency when theinductor current goes to negative at light load. This mode is used to disable Power Savingfeatures.
As shown in Table 2.3, an input high will set controller to dual phase with FCCM; an input low will setcontroller to single phase with DCM; an input to intermediate level(s) will set the controller to singlephase with FCCM or USM. Intermediate level(s) are manufacturer specific. Refer to Table 2.4 for PSIthreshold voltages.
7
Open Voltage Regulator Specification (Type 2 Revision 1.0)
Table 2.3: Power Saving Interface ConfigurationsPSI Level Phase Configuration NoteHigh Dual Phase with FCCM Required
Intermediate Single Phase with FCCM Optional
Intermediate Single Phase with USM Optional
Low Single Phase with DCM Required
Note: When operated at single phase mode, controller shall be set to phase 1.
Figure 2.3 illustrates the typical usage of PSI. Different combinations of resistors R_PSI and R_PSI2will set the input levels to the PSI pin.
Controller
PSI
3V3
R_PSI
R_PSI2IN
4
3
2
1
A B C D E F G
Figure 2.3: Power Saving Circuit Diagram
Thermal Shutdown When the device temperature exceeds the junction temperature (Tj), internalthermal shutdown circuitry shall turn off the device.
Thermal Alert (TALERT#) This is an active low open drain output warning signal to indicatewhen either the controller has reached 80% percent of Tjmax or MOSFET has reached itsthreshold via the external thermistor. Refer to Figure 2.4 for logic diagram details. Manufacturersshall provide a method to bypass the internal temperature sensing circuit when the internaltemperature accuracy is insufficient.
Temperature Sensing (TSNS) This is the external thermistor temperature sensing input.
8
Open Voltage Regulator Specification (Type 2 Revision 1.0)
TALERT#
External
Sensing
Temperature
TSNSComparator
Sensor
Temperature
Internal DieOpen Drain Output
Controller
VREF
3V3
<edit here to insert page detail>BASE LEVEL GENERIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
R_TM2
GND
R_TM
R_TALERT
2701 SAN TOMAS EXPRESSWAY
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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
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G
BOM REVPCB REV
SANTA CLARA, CA 95050, USA
Figure 2.4: Thermal Alert and Temperature Sensing Circuit Diagram
9
Open Voltage Regulator Specification (Type 2 Revision 1.0)
2.5 Optional Function Descriptions
Power Supply Pin The pinout provides the option of two power supply pins (PVCC, VCC).Manufacturers can choose to use either or both of them for power supply purpose. If only onepin is used for power supply , the other pin can be NC or can be used for decoupling.
Current Balance Adjustment Current balance or current share adjustment is optional.
Over Current Protection (OCP) OCP is optional. When implemented, manufacturer shall sup-port adjustable OCP or provide a way to disable OCP.
Over Voltage Protection (OVP) OVP is optional. When implemented, manufacturer shall referto Table 2.4 for minimum OVP threshold voltage or provide a way to disable OVP.
Under Voltage Protection Under voltage protection is optional.
Input Undervoltage Lockout (UVLO) Input undervoltage lockout is optional.
Figure 2.5: Over Voltage and Under Voltage Protection
Note 1: The above optional features may be implemented with the reserved optional low gate strapsdefined by the Reference Circuit in Figure 2.1.
Note 2: It is required to temporarily disable the protection mechanisms (UVLO, OCP, OVP if imple-mented) during dynamic voltage change.
10
Open Voltage Regulator Specification (Type 2 Revision 1.0)
2.6 Electrical Characteristics
Table 2.4 describes the required electrical characteristics for Type 2. For all parameters, manufacturersmay, at their discretion, support wider ranges compared to the ones defined in the table
Table 2.4: Type 2 Electrical CharacteristicsParameter Sym Min Typ Max Units Notes
Supply Voltage VCC 13.2 V Type 2-DTVCC 5.5 V Type 2-BT
Gate Driver Voltage PVCC 4.5 12 13.2 V Type 2-DTPVCC 4.5 5 5.5 V Type 2-BT
Maximum Duty Cycle 70 %
Minimum Duty Cycle 0 %
Minimum Switching frequency Fswmin 250 KHz *See note below
Enable High Threshold Venih 1.6 V
Enable Low Threshold Venil 0.8 V
Power Saving Interface HighThreshold
Vpsiih 2.4 V Enables DualPhase With FCCM
Power Saving Interface LowThreshold
Vpsiil 0.8 V Enables SinglePhase With DCM
Power Saving InterfaceIntermediate Threshold Range
0.8 2.4 V Multi-level Range(optional)
Minimum Junction Temperature Tjmin 0 ºC
Maximum Junction Temperature Tjmax 150 ºC
Maximum Internal Power GoodPull Low Resistance
150 Ohm Tjmin<Tj<Tjmax
Minimum Output Over VoltageProtection Threshold
Vovp 1.4*Vout V Tjmin<Tj<Tjmax(optional)
Maximum Output UndervoltageProtection Threshold
Vuvp 0.5*Vout V Tjmin<Tj<Tjmax
Thermal Shutdown Threshold Tsd Tjmax -10 Tjmax ºC
Minimum Thermal AlertThreshold
TALERT# 0.8*Tjmax ºC
Temperature Sense Threshold Vtsns 1.00 V External ThermalSense
Minimum Output Voltage Voutmin 0.3 V Standby Mode
Reference Voltage VREF 2.0 V
Reference Accuracy 1.0 % Ta=25ºC1.50 % Tjmin<Tj<Tjmax20 % Standby Mode
Note: The minimum switching frequency(Fswmin) shall be less than or equal to 250 KHz.
11
Chapter 3
PWM-VID Dynamic Voltage Control -Analog Method
PWM-VID is a single-wire dynamic voltage control circuit driven by the pulse widthmodulationmethod.This circuit reduces the device pin count and enables a wide dynamic voltage range.
The VID PWM duty cycle determines the variable output voltage at REFIN, as shown in Figure 3.1.Vmin is the zero percent duty cycle voltage value. Vmax is the one hundred percent duty cycle voltagevalue. The resolution of each voltage step (Vstep) is determined by the number of available steps(Nmax) and the selection of the dynamic voltage range (Vmax-Vmin). N is the number of steps at aspecific Vout. N/Nmax ratio is equal to the duty cycle. The dynamic voltage VID frequency (Fswvid)is determined by the unit pulse width (Tu) and the available step number Nmax (Tvid = Tu * Nmax,Fvid= 1/Tvid). Tu is programmable.
Vou
t (V)
Vmax
Vout = Vmin + N *Vstep
0 0.2 0.4 0.6 0.8 1 1.2
Vou
t (V)
PWM DUTY
Vmax
Vmin
Vout = Vmin + N *Vstep
Figure 3.1: Dynamic Output
Vstep, Nmax, Vmin, and Vmax are variables that determine Vout. Nmax is limited by the unit pulsewidth and the minimum VID frequency.
12
Open Voltage Regulator Specification (Type 2 Revision 1.0)
The dynamic voltage output could be implemented by the analog method with a switching device anda resistor network. A buffer is used as the switching device to create dynamic output. Resistor networksets the minimum offset voltage.
3.1 Circuit Diagram
Figure 3.2 shows the analog circuit diagram for the PWM-VID dynamic voltage control. The bufferrequires a stable, high precision voltage reference (VREF) for the linear output. The dynamic rangeof the circuit is determined by the resistor selection. Resistor R_REFADJ and capacitor C_REFINfunction as a filter for the PWM signal, and will affect the ripple voltage and the slew rate at the output(REFIN) during voltage transitions. Refer to 3.1 for equations to calculation details.
PWM
R_VREF2C_REFIN
O
GND
VCC
ANC
OEBuffer
REFIN
VREF
GNDGND GND
R_VREF1
R_REFADJOE
NCA
VCC
GND
OIN
4
3
2
1
A B C D E F G
Figure 3.2: PWM-VID Analog Circuit Diagram
13
Open Voltage Regulator Specification (Type 2 Revision 1.0)
Table 3.1: Dynamic Voltage Equations
Output Voltage Equation Description
NmaxTotal available voltage stepnumbers.
N
The step number at the specificVout. N/Nmax ratio equals dutycycle.
Vmax VREF ∗ R_VREF2R_VREF2 + (R_VREF1||R_REFADJ)
The output voltage of REFIN at onehundred percent duty cycle.
Vmin VREF ∗ R_VREF2||R_REFADJR_VREF1 + (R_VREF2||R_REFADJ)
The output voltage of REFIN at zeropercent duty cycle.
VstepVmax− Vmin
NmaxThe resolution of the voltage step.
Vout Vmin + N∗Vstep The output voltage at REFIN.
Fswvid1
Tu ∗ NmaxThe dynamic voltage VID frequency
There will be some ripple voltage at REFIN due to the nature of the PWM and filter. The error amplifierat REFIN shall be able to tolerate a reasonable amount of Ripple Voltage.
Note: For design consistency, a tri-state buffer is required as the switching device.
14
Open Voltage Regulator Specification (Type 2 Revision 1.0)
3.2 Integrating the Buffer
Figure 3.3 shows a dynamic voltage control circuit with the integrated buffer. This defines the imple-mentation of the VID and REFADJ functions.
Controller
PWM
External
Block
Control
Vstandby
VID
GND
2
3Q5
GND
R15
1
VREF
REFADJ
REFIN
GNDGND
Buffer
R_VREF1
GND
Rstandby
R_VR
EF2
C_REFIN
SG
D
OE
NCA
VCC
GND
OR_REFADJ OE
NCA
VCC
GND
O
IN SG
D
IN
4
3
2
1
A B C D E F G
Figure 3.3: Integrated Buffer Circuit
15
Open Voltage Regulator Specification (Type 2 Revision 1.0)
3.3 Timing Diagram
Figure 3.4 contains the details of the timing diagram. After VCC powers up, the controller generatesthe VREF. REFIN settles at Vboot before the GPU drives the VID pin. After the GPU powers up,Vboot control will be pulled low by software. At the same time the VID is driven by a PWM signal,moving REFIN into the normal operating mode. When the GPU is going to standby, software willtri-state VID and Vboot control, and an External Control will enable Rstandby.
VCC
EN
VREF
External Control (GPU Standby mode)
VID (PWM)
REFIN
Vout
Vboot
Vstandby
GPU Standby
Vboot
Figure 3.4: Timing Diagram
16
Open Voltage Regulator Specification (Type 2 Revision 1.0)
3.4 Standby Mode
Standby mode keeps the GPU in a low voltage state (in the range of 0.3V) for the quick recovery. As theGPU steps into the standby mode, the resistor Rstandby and the switch Q6 (parallel to the R_VREF2and Rboot) set the standby voltage. The accuracy of the reference voltage in the standby mode couldbe reduced from the normal operating mode. Refer to Figure 3.5 for the illustration of standby voltage.
Vou
t (V)
PWM‐VID OUTPUT
Standby Mode
Vboot
0 0.2 0.4 0.6 0.8 1
Vou
t (V)
Duty Cycle
PWM‐VID OUTPUT
Standby Mode
Vboot
Figure 3.5: Illustration for Standby Mode and Adjustable Vboot Setting
17
Open Voltage Regulator Specification (Type 2 Revision 1.0)
3.5 Voltage Waveform and Propagation Delay
Figure 3.6 describes the behavior of the buffer.
GND
3V3
INPUT
TfTr
Vm
TPLH
OUTPUT
Tu
TPHL
VREF
Vol
Vm
Figure 3.6: Illustration of Voltage Waveform and Propagation Delay
3.6 Electrical Characteristics
Table 3.2: Buffer Electrical CharacteristicsParameter Sym Min Typ Max Units Notes
Buffer Supply Voltage VREF V
Unit Pulse Width Tu 27 ns Configurable
Buffer Output Rise Time Tr 5 ns
Buffer Output Fall Time Tf 5 ns
Rising and Falling Edge Delay ∆T 0.5 ns ∆T = | Tr - Tf |
Propagation Delay Tpd 10 ns Tpd = TPHL =TPLH
Propagation Delay Error ∆Tpd 0.5 ns ∆Tpd = TPHL - TPLHH
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Open Voltage Regulator Specification (Type 2 Revision 1.0)
Table 3.3: Recommended Component OptionsParameter Sym Min Typ Max Units Notes
Upper Resistor R_VREF1 4.75 kOhm
Lower Resistor R_VREF2 4.22 kOhm
Filter Resistor R_REFADJ 6.34 kOhm
Boot Mode Resistor Rboot kOhm Project Specific
Standby Mode Resistor Rstandby 1.07 kOhm
Filter Capacitor C_REFIN 0.01 µF
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Chapter 4
Mechanical Specifications
4.1 QFN24 Package Outline Drawing
OpenVReg Type 2 and subtypes could use 24 lead QFN 4mmX4mm package. (Refer to Figure 4.1 fordetails).
Figure 4.1: QFN24 Package Outline Drawing
Table 4.1: QFN24 Package Dimensions
Min Typ Max UnitsA 3.9 4.0 4.1 mm
B 2.30 2.90 mm
C 2.30 2.90 mm
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Open Voltage Regulator Specification (Type 2 Revision 1.0)
4.2 QFN24 PCB Footprint
Figure 4.2: QFN24 PCB Footprint
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Chapter 5
Environmental Compliance
All the components are subject to the Industry Environmental Compliance laws, regulations andstandards. In addition, RoHS Annex Exemptions are not allowed. Due to the constant changes andadditions to laws and regulations, manufacturers shall check with customers for up-to-date requirements.
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Applicable Documents
The following documents contain provisions which through reference in this text, constitute provisionsof this standard. At the time of publication, the editions indicated were valid. However, users of thisstandard are advised to ensure they have the latest versions of referenced standards and documents.
q PWM-VID Specification Revision 1.0.
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Open Voltage Regulator Specification (Type 2 Revision 1.0)
Contact
If you have questions or comments, please send email to [email protected].
Notice
ALL DESIGN SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOS-TICS, LISTS, AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY, “MATERIALS”)ARE BEING PROVIDED “AS IS.” NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY,OROTHERWISEWITH RESPECT TOTHEMATERIALS, ANDEXPRESSLYDISCLAIMS ALLIMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESSFOR A PARTICULAR PURPOSE.
Information furnished is believed to be accurate and reliable. However, NVIDIA Corporation assumesno responsibility for the consequences of use of such information or for any infringement of patentsor other rights of third parties that may result from its use. No license is granted by implication ofotherwise under any patent rights of NVIDIACorporation. Specifications mentioned in this publicationare subject to change without notice. This publication supersedes and replaces all other informationpreviously supplied. NVIDIA Corporation products, designs, and/or specifications are not authorizedas critical components in life support devices or systems without express written approval of NVIDIACorporation.
Trademarks
© 2011 NVIDIA Corporation. All rights reserved. NVIDIA, the NVIDIA logo, and OpenVRegare trademarks and/or registered trademarks of NVIDIA Corporation in the U.S. and other countries.Other company and product names may be trademarks of the respective companies with which theyare associated.
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