on thermal activation of interface-generated currents in high-resistivity silicon devices

Nuclear Instruments and Methods in Physics Research A 512 (2003) 8–20

On thermal activation of interface-generated currents inhigh-resistivity silicon devices

Arie Ruzin*

Department of Physical Electronics, Faculty of Engineering, Tel Aviv University, 69978 Tel Aviv, Israel

Abstract

In this study Si/SiO2 interface properties of high-resistivity, detector-grade silicon are characterized, analyzed and

compared. Wafers cut from the same ingots were processed by various technologies with the same mask set to

emphasize the comparative nature of the study. Samples with resistivity in the range of 2–15 kO cm and orientations

/1 1 1S and /1 0 0S were used. It is shown that the thermal activation energies of the surface-generated currents are

similar in all the process technologies and wafer orientations. The concentration of the generation centers is shown to be

process and orientation dependent. Current–voltage curves are shown to be somewhat different compared to the

‘‘textbook’’ case and computer simulation results are used to explain the difference.

r 2003 Elsevier B.V. All rights reserved.

PACS: 85.60.Gz; 87.66.Pm; 85.30.De

Keywords: Si/So2 interface; Gated bodies; Interface ganeration; Activation energy

1. Introduction

Surface and interface generation–recombination(G–R) centers may affect significantly the overallperformance of semiconductor devices. Mostsusceptive are devices operated at low leakagecurrents, and devices used in applications wherelow electronic noise is required. Radiation detec-tors fall into both categories. The leakage currentin reversed bias p–n junctions is often determinedby the free-carrier generation in the bulk and at theinterface. In addition, the interface G–R centersmay trap and detrap free carriers introducingfluctuations to the free-carrier concentration, thus

creating an electronic noise, as in the MOSFETchannels.

The gated diode structure has been introducedin the 1960s and since then serves as an efficienttool for interface studies [1]. The ‘‘textbook’’structure of the gated diode and the expectedcurrent–voltage (I2V ) curve for pþn case, asdescribed in Ref. [1], are shown in Figs. 1(a) and(b), respectively. For convenience purposes theillustration is altered from Ref. [1] to p+n diode.The diode is kept in the reverse bias regime. Whenpositive voltage is applied to the gate, the siliconunderneath the oxide is in accumulation and nonet carrier generation takes place (region ‘Acc.’ inFig. 1(b)). At a low negative gate bias the surfacepotential crosses the flat band level and the surfacebecomes depleted. Under these conditions net

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*Tel.: +972-3-640-5214; fax: +972-3-642-3508.

E-mail address: [email protected] (A. Ruzin).

0168-9002/03/$ - see front matter r 2003 Elsevier B.V. All rights reserved.

doi:10.1016/S0168-9002(03)01872-2

surface generation takes place with the holesdrifting to the pþ region contributing to theleakage current. As the negative bias is intensifiedthe depletion region underneath the oxide growsproducing further current increase due to the bulkgeneration current from the depleted region(region ‘Depl.’ in Fig. 1(b)). Once inversionconditions are reached and carrier concentrationat the interface increases, the interface generationis reduced and so is its contribution to the totaldiode current (region ‘Inv.’ in Fig. 1(b)).

Quantitative treatment of interface generation isvery similar to the treatment of bulk generation.Generally, SRH mechanism is used:

Us ¼nsps � n2

i

ðps þ nie�Et=kT Þ=sn þ ðns þ nieEt=kT Þ=spð1Þ

where ns and ps are the concentrations of the freeelectrons and holes at the interface, ni is theintrinsic carrier concentration, se and sp are the

surface recombination velocities of electrons andholes, respectively; Et is the energy level of thegeneration recombination centers with respect tothe intrinsic Fermi level.

Numerous studies were published on the subjectof surface recombination, mainly in low-resistivity,VLSI-grade silicon. Some studies concluded thatthe concentration of interface G–R centersstrongly depends on doping concentrationin the silicon bulk [2–4], while others showed nosignificant doping effect [5]. This study concen-trates on the characterization of interface G–Rcenters in high-resistivity silicon as a function oftemperature.

2. Experimental

In order to conduct a strictly comparative studyand identify the impact of process, wafer quality,wafer resistivity, and wafer orientation, the vari-able experiment parameters have to be fullycontrolled. Wafers of several resistivities andorientations were purchased directly from a wafermanufacturer1 in groups, each group cut from asingle ingot. Each wafer group was polished by thesame company2 (see footnote 1 also) to avoiddifferences in surface quality prior to the process.Each detector manufacturing facility often followsdifferent (and confidential) design rules, includingmetal/oxide overlapping policy, etc. In order toavoid geometric uncertainties the masks weredesigned and fabricated externally. The wafersand the masks were then distributed to threedetector manufacturers: Micron,3 ITE,4 andSintef.5

Fabricating the gated diode shown Fig. 1(a)requires an additional oxidation step after pþ

implant. The extra oxidation step adds to the

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(a)

-15 -10 - 5 0 5-5

-4

-3

-2

-1

0

Cur

rent

[Arb

. uni

ts]

(b)

Gate Diode

p+SiO2

n-Si

Gate Bias [V]

Fig. 1. The ‘‘textbook’’ structure of a gated diode pþn case, as

described in Ref. [1]: (a) geometry and doping profiles and (b)

expected I–V curve for a positive oxide charge.

1Topsil Semiconductor Materials, P.O. Box 93, Linderupvej

4, DK-3600 Frederikssund, Denmark.2 Institute of Electronic Materials Technology (ITME), 133

W !olczynska str, 01-919 Warsaw, Poland.3Micron Semiconductor Limited, 1 Royal Buildings, Church-

ill Industrial Estate, Lancing Sussex, UK.4 Institute of Electron Technology (ITE)Al. Lotnikow 32/46,

PI 02-668 Warsaw, Poland.5Sintef, P.O. Box 104, Blindern, N-0314 Oslo, Norway.

A. Ruzin / Nuclear Instruments and Methods in Physics Research A 512 (2003) 8–20 9

thermal budget, and it is unneeded in a standardPIN detector fabrication process.

A cylindrical, multi-gate structure was usedfollowing the GM design of the ROSE (RD-48)collaboration [6], as shown in Fig. 2. The structureis fully compatible with the standard, one-side PINdetector fabrication technology. The MOS ringsare 50 mm thick with 5 mm distances between eachother and between the innermost (first) ring andthe diode.

The I–V measurements were conducted usingKeithley M90 system. The first gate ring was sweptfrom positive (or zero) to negative voltage, whilethe diode reverse bias was stepped. In order tolimit the expansion of the lateral depletion fromthe first gate to the next gates, the second gate ringwas biased with a positive voltage to formaccumulation conditions. The measurements werecarried out in a Janis ST-100 cryostat6 as afunction of temperature.

3. Computer simulation

The experimentally observed I–V curves werequalitatively different from the curve describedin Fig. 1(b). Contrary to the ‘‘textbook’’ curve, insome cases the diode current was higher inaccumulation than in inversion (under the gate),IinvoIaccum: In addition the slope of the I–V curvein the depletion region is process/sample depen-

dent. In order to understand the differencescomputer simulation was performed on thestructures shown in Figs. 1(a) and 2, using thecommercial ISE-TCAD simulation software [3].The commonly used analytic treatment of thedevice requires certain approximations. One of theassumptions is that the surface potential under-neath the whole gate area is uniform, therefore thewhole gate area switches from accumulation todepletion and then to inversion simultaneously,whereas in reality it does not have to be the case,particularly under the depletion–inversion condi-tions. In addition, the overlapping area and edgeof the pþ area under oxide should be examined inmore detail. Two gated diode structures weresimulated, one with 5 mm overlapping between thegate contact and the diode implant, GD49, and theother identical to the experimental structure (with5 mm gate to diode spacing), GD50. Both struc-tures are cylindrical with +1mm diodes, ‘‘fabri-cated’’ by B0.6 mm deep boron implant on n-type,silicon substrates. The bulk is 200 mm thick withB2 kO cm resistivity and B1 mm nþ (phosphor)layer on the backside. Gate material is aluminumand oxide charge is set at 1010 cm�2. On theimplanted areas of the backside and the diode,ideal ‘‘Ohmic’’ contacts are defined. The potentialof the backside is set to 0 and the potential of thediode is set to –10V, providing reverse bias withdepletion layer of B80 mm under the center of thediode implant.

3.1. ‘‘Textbook’’ gated diode with diode–gate

overlap

In the structure shown in Fig. 1(a) the metallur-gic junction edge is located under the MOS gate,therefore the approximation that the interfacepotential equals the pþ potential under theinversion conditions should be accurate. However,with the gate biased positively for achievingsurface accumulation, the pþ overlapping regionmay be depleted near the interface, thus yieldinginterface-generated current. One should keep inmind that under such bias conditions the ‘‘classic’’solution does not take into account any interface-generated current contribution. Furthermore,some results indicate that the concentration of

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Fig. 2. Side view of the multi-gate, cylindrical, GM structure,

cut through the center.

6 Janis Research Company, 2 Jewel Drive, Wilmington, MA

01887-0696 USA.

A. Ruzin / Nuclear Instruments and Methods in Physics Research A 512 (2003) 8–2010

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Fig. 3. Distribution of electrostatic potential inside gated diode, GD49, with surface recombination, s ¼ 10 cm/s, and bulk generation

tow=10ms, focusing on the interface area near the gate–diode border.

Fig. 4. Profile of [holes–electrons] concentration inside GD49 device. Bright color denotes holes, dark color electrons.


interface G–R centers is proportional to thedoping concentration [2–4] according to

s ¼ s0 1þ SRefN

NRef

� �g� �ð2Þ

in which case the generation in this region could bedominant. In Eq. (2) N is the doping concentra-tion near the interface, and the parameters s0, SRef ,

NRef , g are empirically determined. These para-meters represent the minimal recombination velo-city (s0), the ‘‘threshold’’ doping concentration atwhich the effect becomes significant (NRef ), andthe effect intensity (SRef , g)U It should also benoted that in the GD49 structure, neither in Ref.[1], nor in the presented simulation program, thedevice behavior near the external edge of the gateis not taken into account. The electrostaticpotential distribution in gated diode, GD49, atfour different gate voltages is shown in Fig. 3.As expected, in the accumulation regime(Vg ¼ þ15V) the lateral depletion layer is negli-gible and the interface potential is slightly positive

(indicated by nearly white, monotonic color underthe gate). At lower gate voltages the interfacepotential is lowered, and at Vg ¼ �3V a depletionlayer is formed. However, unlike in the regularMOS structures, where there is no splitting of theFermi level, in the gated diodes a stronger bandbending is required to place the hole quasi-Fermilevel in the inversion position. Once the inversionconditions are reached the potential profiles underthe gate and the pþ region are very similar. Thedifference in the concentration of the free holesand electrons at these conditions is shown inFig. 4. The ‘tow’ and ‘s’ indicated in Fig. 3 captionrefer to the bulk SRH (Shockley–Read–Hall)lifetime and surface recombination velocity,respectively.

High [h]–[e] concentration is denoted by darkcolor, and high [e]–[h] concentration by brightcolor. The ‘extension’ of the pþ region to the gatearea under inversion conditions is clearly seen atVg ¼ �9:5 and –30V. It is important to note thatin the frame ‘‘Vg ¼ þ15V’’ of Fig. 4, a depleted

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Fig. 5. Profile of the total generation of free carriers, including bulk and interface SRH generation in the GD49 structure.


region is present in the silicon under the oxide inthe region of gate–implant overlapping. In thisregion the MOS substrate is given by the p+

implant of the diode, which is biased at –10V,therefore the gate bias of +15V creates adepletion region. The practical implication of thisdepletion region can be seen in Fig. 5, frame‘‘Vg ¼ þ15 V ’’. In the overlapping area there is abright colored region, indicating net free carriergeneration at the interface. In addition, there is alocal impact ionization (in the order of 1011 cm�3)due to the high electric field in the edge region.With decreasing gate bias the electric field in theedge area decreases, so when the inversion condi-tions are reached, neither the interface generationnor the impact ionization is observed.

In the accumulation regime there is no netcarrier generation at the n-Si/SiO2 interface, or inthe bulk underneath. At a gate voltage of –3Vinterface generation at the n-Si/SiO2 interfacetakes place, yet the generation at the p-Si/SiO2

stops due to accumulation conditions. In inversionpractically no interface generation takes place, andthe device current is dominated by the bulkgeneration.

3.2. Multi-gate structure without overlapping

In the GD50 virtual device the bias voltage ofGate 1 was scanned in the same range as the gatevoltage of GD49, while Gate 2 was kept at +30Vto ensure accumulation conditions around Gate 1and limit the active volume of the device. As canbe seen in Fig. 6 the electrostatic potential profilesof GD50 are rather similar to those of GD49,except a certain voltage drop across the lateral5 mm gap between the p+ region and the gate.Thus, the interface potential under the gate ininversion is higher than in the p+ region and thedepletion width is smaller. The difference betweenthe free hole and electron concentrations shown inFig. 7 shows clearly that the inversion layer

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Fig. 6. Distribution of electrostatic potential inside gated diode, GD50; focusing on the interface area near the gate–diode border.


formed under Gate 1 at negative Vg bias does notextend laterally to ‘short-circuit’ to the pþ implant,as in the case of GD49 device. The positive biasedGate 2 and the positive oxide charge provideelectron-rich layer at the interface extending to thedevice edge.

The free-carrier concentrations at the Si/SiO2

interface under the 5 mm gaps between the diode,Gate 1, and Gate 2 areas appear to be verydifferent than under either gate. In fact, it is shownin Fig. 8 that the interface generation in the gapsbetween the gates and between the first gate andthe diode implant does not stop entirely even fordeep inversion conditions under Gate 1. Theinterface generation is indicated by the smallbright areas at the Si/SiO2 interface under thegate gaps on frame ‘‘Vg ¼ �30’’ of Fig. 8.

3.3. Current–voltage simulation

Qualitatively it is clear that the classic inter-pretation of the current curve in Fig. 1(b), stating

that the current in the accumulation bias range isbulk generated (in the diode depletion width)could be inaccurate. In fact, even the currentincrease shown in the inversion compared to theaccumulation zones is not evident because of thecontinuous interface generation. To gain a quanti-tative insight on this effect both devices weresimulated for various combinations of bulk andinterface generation rates.

Device geometry GD49 was simulated for thefollowing combinations of bulk–interface genera-tion: {s ¼ 0 cm/s, tSRH ¼ 10ms}, {s ¼ 10 cm/s,tSRH ¼ 10ms}, and {s ¼ 10 cm/s, tSRH ¼ 1000 s}with s ¼ sp ¼ sn and no doping dependence of s:The results are summarized in Fig. 9. The firstcombination, corresponding to zero interfacegeneration, yields a small increase in the diodecurrent when a depletion region forms under thegate.

The third combination implies negligible bulkgeneration, and the second case combines thecontributions of the bulk and the interface

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Fig. 7. Profile of [holes–electrons] concentration inside GD50 device. Bright color denotes holes, dark color electrons.


generation. It can be seen that for the thirdcombination the total diode current in accumula-tion is higher than in depletion in spite of theincreased contribution of the depleted volume.

Simulated current–voltage curves for the dopingdependent and independent interface generationare shown in Fig. 10. The dependence is assumedto follow Eq. (2) with the following parameters:

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Fig. 8. Profile of the total generation of free carriers, including bulk and interface SRH generation in the GD50 structure.

-30 -20 -10 0 10 20

-30

-25

-20

-15

-10

-5

0

BG SG BG+SG

Cur

rent

[pA

]

Gate Bias [V]

Fig. 9. Computer simulations of current–voltage dependence in

GD49 device for the cases of: bulk tSRH ¼ 10ms, s ¼ 0 (BG

curve); bulk tSRH ¼ 1000 s, s ¼ 10 cm/s (SG curve); bulk

tSRH ¼ 10ms, s ¼ 10 cm/s (BG&SG curve).

-30 -20 -10 0 10 20

-25

-20

-15

-10

-5

SRef

=10

SRef

=0

Cur

rent

[pA

]

Gate Bias [V]

Fig. 10. Computer simulations of current–voltage dependence

in GD49 device for the cases of doping-dependent and

-independent interface generation, s; SRef ¼ 10 and 0, respec-

tively. Bulk tSRH ¼ 10ms and s0 ¼ 10 cm/s for both curves.


minimal generation rate, for an ‘intrinsic’ interfaceis taken similar to the results of Sintef (seefootnote 5), s0 ¼ 10 cm/s; parameters g ¼ 1 andNRef ¼ 1016 cm�3 are similar to the results of Ref.[2]; and values of 0 and 10 were used for SRef toobtain constant and doping-dependent rates,respectively.

The current curve for the doping-dependentsðSref ¼ 10Þ coincides with the curve for doping-independent sðSref ¼ 0Þ under inversion and deple-tion conditions, yet in accumulation the curveshave a totally different shape. For higher values ofSref ð> 50Þ the curves part even under the depletionconditions.

The general shape of the I2V curves of themulti-gate device, GD50, has some distinctionsfrom these of GD49. It can be seen in Fig. 11 thatthe current in inversion in this case is higher thanin accumulation for the same s values, and thecurrents are influenced by the interface generationeven under deep inversion conditions (thereforethe BG and the BG&SG curves do not coincide ininversion).

The simulation was performed assuming G–Rcenters are in the middle of the gap, with s ¼ sn ¼sp; when

IInterface ¼ 12

qsAni ð3Þ

is valid. The simulated current steps in GD49 andGD50 are B17 and 19.5 pA, respectively. To

check the simulation results we deduce the inter-face recombination velocity from the current step:9 cm/s for GD49 and 10.3 cm/s for GD50. Itshould be noted that the simulations were per-formed on ‘half devices’, so the current stepsshould be doubled. The difference in the currentsteps could be attributed to the reduced net area ofthe gate in the GD49 device due to the over-lapping.

4. Experimental results and analysis

Two sets of typical I–V curves measured atroom temperature (RT) with gated diodesprocessed by ITE on B2 kO cm /1 1 1S- and/1 0 0S-oriented wafers (TO66-I and TO141-I) areshown in Figs. 12(a) and (b), respectively. Thedevices fabricated on the 2 kO cm /1 1 1S-orientedwafers typically exhibit B30 pA step upon thedepletion–inversion transition. Devices fabricatedon the /1 0 0S-oriented wafers typically haveB10 pA current steps. The current in inversion isnearly constant and is higher than the current inaccumulation. This is fully consistent with the caseof a dominating bulk generation. Using themeasured current steps and the relation

IInterface ¼ AUsq ð4Þ

we deduce the generation rates, Us; at roomtemperature to be 5.8� 1010 and 1.9�1010 cm�2 s�1 for /1 1 1S and /1 0 0S orienta-tions, respectively. Expression (4) is more generalthan Eq. (3) because it does not assume midgaptrap level, nor equal recombination cross-sectionsfor holes and electrons.

It should be noted that the accumulation–depletion transition occurs at lower gate voltagesin the /1 1 1S-oriented samples. The effect can beexplained by a higher oxide charge in the /1 1 1S-oriented samples.

The results shown in Fig. 13 were measured withsamples processed by Micron Semiconductors onB2 kO cm /1 1 1S- and /1 0 0S-oriented wafers.These wafers are similar (cut from the same ingot)to the wafers TO66-I and TO141-I shown inFig. 12. The devices fabricated on the /1 1 1S-oriented wafers typically exhibit B850 pA step

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-30 -20 -10 0 10 20-40

-35

-30

-25

-20

-15

-10

-5

0

BG

SG

BG+SG

Curr

ent

[pA

]

Gate Bias [V]

Fig. 11. Computer simulations of current–voltage dependence

in GD50 device for the cases of: bulk tSRH ¼ 10ms, s ¼ 0 (BG

curve); bulk tSRH ¼ 1000 s, s ¼ 10 cm/s (SG curve); bulk

tSRH ¼ 10ms, s ¼ 10 cm/s (BG&SG curve).


during the depletion–inversion transition. Devicesfabricated on the /1 0 0S-oriented wafers typicallyhave B470 pA current step. The current under theinversion conditions levels off at nearly the samevalue as under the accumulation. The step size onthe other hand is B8 times larger than the currentin inversion.

This is fully consistent with the case ofdominating interface generation. The I–V char-acteristics differ qualitatively from the curves inFig. 12 in the current slope during depletion.While the bulk-generated component of thecurrent increases due to the growth of the

depletion layer, the interface-generated componentdecreases, as shown in the simulation results forthis geometry.

The generation rates, Us; at room temperature,calculated according to Eq. (4), are 1.64� 1012 and9.1� 1011 cm�2 s�1 for /1 1 1S and /1 0 0S or-ientations, respectively. In these samples, as in theones processed by ITE, the transient fromaccumulation to depletion occurs at lower Gate 1voltage in the /1 1 1S-orientated samples. Themeasurements of samples processed by Sintefare shown in Fig. 14. The wafer sets, TO72-Sand TO145-S, are similar to the sets described

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-50 -40 -30 -20 -10 0-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2 Vd=-8V Vd=-15V Vd=-22V

Cur

rent

[nA

]

Gate Bias [V]

-50 -40 -30 -20 -10 0-0.8

-0.6

-0.4

-0.2

0.0

Vd=-7V Vd=-13V Vd=-19V

Cur

rent

[nA

]

Gate Bias [V](a) (b)

Fig. 13. Current–voltage characteristics of gated diodes processed by Micron Semiconductors on B2 kO cm silicon for three different

bias voltages on the diodes: (a) sample on TO69-M wafer with /1 1 1S orientation and (b) sample on TO139-M wafer with /1 0 0Sorientation.

-50 -40 -30 -20 -10 0

-0.40

-0.35

-0.30

-0.25

-0.20

-0.15 Vd=-7V Vd=-13V Vd=-19V

Cur

rent

[nA

]

Gate Bias [V]

-50 -40 -30 -20 -10 0 10

-0.14

-0.13

-0.12

-0.11

-0.10

-0.09

-0.08

-0.07

-0.06 Vd=-7V Vd=-13V Vd=-19V

Cur

rent

[nA

]

Gate Bias [V](a) (b)

Fig. 12. Current–voltage characteristics of gated diodes processed by ITE on B2 kO cm silicon for three different bias voltages on the

diodes: (a) sample on TO66-I wafer with /1 1 1S orientation and (b) sample on TO141-I wafer with /1 0 0S orientation.


in Figs. 12 and 13. The devices fabricated on the/1 1 1S-oriented wafers typically exhibit B21 pAstep. Device fabricated on the /1 0 0S-orientedwafers typically have B15 pA current step. Thegeneration rates, Us; at room temperature, calcu-lated according to Eq. (4), are 4� 1010 and3� 1010 cm�2 s�1 for /1 1 1S and /1 0 0S orienta-tions, respectively. As in all the other sets, thetransient from accumulation to depletion occurs atlower Gate 1 voltage in the /1 1 1S-orientatedsamples. The room temperature I–V curves differqualitatively and quantitatively for each process.

The current step magnitudes were measured forvarious temperatures and the results fit to the‘‘modified’’ Arrhenius equation

Rate ¼ AT2e�Ea=kT : ð5Þ

In the original Arrhenius equation the pre-exponential factor is assumed to be independent(or weakly dependent) of the temperature. In thecase of G–R mechanisms the factor is a function ofthe thermal velocity and the effective densities ofstates, NV; NC: This dependence accounts for theT2 factor.

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-50 -40 -30 -20 -10 0 10-60

-50

-40

-30

-20


Cur

rent

[p

A]

-60

-50

-40

-30

-20

Cur

rent

[p

A]

Gate Bias [V]

-50 -40 -30 -20 -10 0 10

Gate Bias [V]


(a) (b)

Fig. 14. Current–voltage characteristics of gated diodes processed by Sintef on B2 kO cm silicon for three different bias voltages on

the diodes: (a) sample on TO72-S wafer with /1 1 1S orientation and (b) Sample on TO145-S wafer with /1 0 0S orientation.

3.2 3.4 3.6 3.8 4.0 4.2 4.4

10-17

10-16

10-15

10-14

10-13

TO69-M TO66-I TO72-S

Cur

rent

/T2 [A

/K2 ]

1000/T [1/K]

3.2 3.4 3.6 3.8 4.0 4.2 4.410-17

10-16

10-15

10-14

10-13

TO139-M TO141-I TO145-S

Cur

rent

/T2 [A

/K2 ]

1000/T [1/K](a) (b)

Fig. 15. Arrhenius plots of the interface currents of the B2 kO cm, samples processed by: M—Micron; I—ITE; S—Sintef. (a) Silicon

/1 1 1S and (b) silicon /1 0 0S.


The fits for the 2 kO cm /1 1 1S and /1 0 0Ssamples are shown in Figs. 15(a) and (b),respectively. The fitting quality parameter, R2; isabove 0.99 in all the reported fits.

Typically, at lower temperatures the curvesmeasured with all the samples maintain the generalshape while changing the levels, as shown inFig. 16. The temperature range of the fits is usuallylimited by the measurement system considerations.The results are summarized in Table 1. SamplesTO149 and TO141 had to be measured with animprovised guard ring due to a significant currentcontribution from the device’s sawed edges. In thesesamples because of the high resistivity the lateralelectric field collects charge from the device edges.

5. Conclusions

The activation energy of the interface generationcurrent is in the range of 0.554–0.607 eV in all thesamples. The average activation energy is 0.58 eVwith a standard deviation of B14mV. In additionto the controlled sets some random samples weremeasured. For example, sample Wx336 in Table 1was manufactured by ST Thomson on a /1 1 1S-oriented wafer, grown by Wacker. The activationenergy of this sample is consistent with the othersamples. The fluctuations in the activation energydo not show correlation to process, resistivity, orwafer orientation. The absolute value of theinterface-related currents is process and orienta-tion dependent. The samples with /1 1 1S orienta-tion generate more current for all processes andresistivities than /1 0 0S samples. Micron processseems to yield the highest interface generation rate.The results seem to indicate in the reported casessome doping dependence in the /1 1 1S samplesprocessed by Micron and Sintef, but largerstatistics is required to establish this.

Acknowledgements

The research was conducted with a financialsupport of the Israeli Ministry of Industry andCommerce and Jordan Valley Applied Radiation,Inc. We also express our gratitude to Micron

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Table 1

Summery of the fitting parameters

Sample Resistivity (kO cm) Orientation Process DI (pA) (300K) A Ea (eV) T range (K)

TO69 2 /1 1 1S Micron 850 34 0.63 240–320

TO66 2 /1 1 1S ITE 32 1.5 0.63 260–320

TO72 2 /1 1 1S Sintef 21 0.68 0.627 260–320

TO139 2 /1 0 0S Micron 470 17.8 0.63 240–320

TO141 2 /1 0 0S ITE 11 0.58 0.604 270–320

TO145 2 /1 0 0S Sintef 15 0.62 0.63 270–320

TO30 11 /1 1 1S Micron 730 19.3 0.62 240–320

TO28 11 /1 1 1S Sintef 18 0.28 0.61 280–320

TO149 B22 /1 0 0S Micron 1000 102 0.65 240–320

TO151 B22 /1 0 0S ITE 32 1.85 0.64 270–320

TO114 B16 /1 0 0S2� Micron 620 28.3 0.63 240–320

Wx336 ST-Thomson 12 0.56 0.637 270–320

-50 -40 -30 -20 -10 010-12

10-11

10-10

10-9

10-8

10-7

320K 290K 260K

Abs

. Cur

rent

[A]

Gate Bias [V]

Fig. 16. Current–voltage characteristics of gated diodes pro-

cessed by Micron Semiconductors on TO69-M wafer

(B2 kO cm with /1 1 1S orientation) at three different tem-

peratures.


Semiconductors, ITE and SINTEF detector manu-facturers for their cooperation.

References

[1] A.S. Grove, Physics and Technology of Semiconductor

Devices, Wiley, New York, 1967.

[2] A. Cuevas, P.A. Basore, G. Giroult-Matlakowski,

C. DuBois, Proceedings of the 13th European

Photovoltaic Solar Energy Conference, Nice, France,

1995.

[3] ISE-TCAD Software and Manual, Integrated Systems

Engineering AG, Zurich, Switzerland.

[4] R.R. King, R.A. Sinton, R.M. Swanson, IEEE Trans.

Electron. Devices 37 (1990) 365.

[5] R.R. King, R.M. Swanson, IEEE Trans. Electron. Devices

38 (1991) 1399.

[6] C. Becker, C. G .oXssling, C. Lichau, T. W .ubben, R.

Wunstorf, Nucl. Instr. and Meth. A 444 (2000) 605.

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on thermal activation of interface-generated currents in high-resistivity silicon devices

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