Analog Integr Circ Sig Process (2006) 49:161–166DOI 10.1007/s10470-006-9351-7

MIXED SIGNAL LETTER

On the realization of the floating simulators using only groundedpassive componentsErkan Yuce

Received: 17 January 2006 / Revised: 15 March 2006 / Accepted: 31 May 2006 / Published online: 11 September 2006C© Springer Science + Business Media, LLC 2006

Abstract In this paper, two novel circuits for realizingfloating inductance, floating capacitance, floating frequencydependent negative resistance (FDNR) and grounded tofloating admittance converter depending on the passivecomponent selection are proposed. Both of the proposedsimulators employ second-generation current controlledconveyors (CCCIIs) and only grounded passive elements.The non-ideal current and voltage gain as well as parasiticimpedance effects on the first proposed circuit are inves-tigated. Also, simulation results using SPICE program aregiven for the first introduced floating simulator to verify thetheory and to exhibit the performance of the circuit.

Keywords Current controlled conveyor . Inductor .

Capacitor . FDNR

1 Introduction

A number of circuits employing current-mode active deviceswith greater linearity, wider bandwidth, less power dissi-pation and larger dynamic range than their voltage-modecounterparts have been given [1]. The circuits given in [2–7]can realize floating inductor employing a grounded capac-itor but the circuits [3–6] can realize floating FDNR em-ploying floating capacitors, at least one of two capacitorsis floating. Also, the circuits proposed as floating capacitorin [2, 4–7] employ a grounded capacitor. The circuit de-

E. Yuce (�)Electrical and Electronics Engineering Department,Bogazici University, 34342 Bebek-Istanbul, Turkeye-mail: dr erkanyuce@yahoo.com

veloped in [7] requires critical passive component matchingconditions.

Contrary to the previously proposed circuits given in [2–7], the proposed floating inductor, capacitor, FDNR simula-tors use only grounded capacitor or capacitors, and do notneed component matching constraints.

Although it is not easy to implement floating inductors inintegrated circuit (IC) implementation, some reported float-ing inductor simulators [2–23] employing various active de-vices such as current conveyors (CCs), current feedback op-erational amplifiers (CFOAs), etc. overcome the difficulty.Also, some circuits introduced in the literature can realizefloating FDNR [24–29] and some of the circuits reported inthe literature can realize floating capacitor [8, 30]. On theother hand, the circuit proposed as a floating inductor in [14]is actually a grounded inductor, which is shown in [15] by acomment.

In this paper, two circuits for the simulation of a float-ing inductance, capacitance, FDNR and grounded to float-ing admittance converter depending on the passive elementchoice are presented. Both of the proposed circuits consistof second-generation current controlled conveyors (CCCIIs)as active components such that the first one employs onedual output CCCII (DO-CCCII) and three plus-type CCCIIs(CCCII + s) and the second one derived from the first oneuses one CCCII + and two DO-CCCIIs. Moreover, both ofthe proposed circuits employ two to three grounded resistorsand one to two grounded capacitors as passive components.If the effects of non-ideal gains on the first proposed simula-tor are considered, the circuit can realize a lossless floatinginductance and capacitance, and can convert the groundedadmittance into the corresponding floating admittance with-out changing the original one.

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162 Analog Integr Circ Sig Process (2006) 49:161–166

2 Proposed floating simulators

DO-CCCII is a four-port current controlled conveyor repre-sented by the following equations:

IY = 0 (1a)

IZ+ = α IX (1b)

VX = βVY + RX IX (1c)

IZ− = −γ IX (1d)

The CCCII + is a three-port current controlled conveyorwith the same equations in (1) except (1d). α and γ arethe frequency dependent current gains besides β is the fre-quency dependent voltage gain. These gains are ideally equalto unity. Furthermore, current convention is such that all cur-rents flow into the CCCIIs.

Using (1b) and (1d), the port currents I1 and I2 in Figs. 1and 2 can be expressed as

I2

I1= −γ

α(1e)

Hence, the value of the ratio of the port currents I1 and I2

depend on the non-ideal current gains. Also, as explained in[2], these non-ideal current gains α and γ depend on the fre-quency of operation, temperature and transistor parametersof the CCCII.

Routine analysis of the circuits shown in Figs. 1 and 2gives the following short circuit admittance matrix:

[Y ] = Y1Y2

Y3Y4 RX

[1 −1

−1 1

](2)

Thus, the intrinsic resistances as define in [31], is givenby

RXk = VT

2I0k(3)

where VT is the thermal voltage and I0k is the bias currentof the kth CCCII. Also, RX in (2) is equals to (RX3 + RX4)and RX3 for the first and second circuits, respectively. More-over, I01 and I02 are chosen sufficiently large thus the first

Fig. 1 The first floatingsimulator employing onlygrounded passive components

Fig. 2 The second floatingsimulator network using onlygrounded passive components

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Analog Integr Circ Sig Process (2006) 49:161–166 163

and second CCCIIs behave like second-generation currentconveyors (CCIIs).

(i) If Y1 = G1, Y2 = G2, Y3 = sC3 and Y4 = G4 are chosenfor the circuits depicted in Figs. 1 and 2, the short circuitadmittance matrix of the floating inductance is found tobe

[YL ] = G1G2

sC3G4 RX

[1 −1

−1 1

]= 1

sLeq

[1 −1

−1 1

]

(4)

Hence, Leq = C3G4 RX/(G1G2) = R1 R2 RX C3/R4.(ii) If Y1 = G1, Y2 = sC2, Y3 = G3 and Y4 = G4 are

taken for the circuits in Figs. 1 and 2, the short circuitadmittance matrix of the floating capacitance is to be

[YC ] = sC2G1

G3G4 RX

[1 −1

−1 1

]= sCeq

[1 −1

−1 1

]

(5)

where Ceq = C2G1/(G3G4 RX ) = C2 R3 R4/(R1 RX ).(iii) If Y1 = y(s), Y2 = G2, Y3 = G3 and Y4 = G4 are

taken for the circuits shown in Figs. 1 and 2, the shortcircuit admittance matrix of the grounded to floatingadmittance converter is calculated as

[YC ] = G2

G3G4 Rxy(s)

[1 −1

−1 1

]=a y(s)

[1 −1

−1 1

]

(6)

Hence, a = G2/(G3G4 RX ) = R3 R4/(R2 RX ) is definedas a multiplier, and y(s) is the grounded admittance.

(iv) If Y1 = sC1, Y2 = sC2, Y3 = G3 and Y4 = G4 arechosen for the circuits in Figs. 1 and 2, the short circuitadmittance matrix of the floating FDNR is given as

[YD] = s2C1C2

G3G4 Rx

[1 −1

−1 1

]= s2 Dd

[1 −1

−1 1

](7)

Consequently, Dd = C1C2/(G3G4 RX ) = C1C2 R3 R4/

RX is obtained. As the frequency increases, the absolutevalue of the negative resistance decreases.

(v) If Y1 = G1, Y2 = G2, Y3 = sC3 and Y4 = sC4 aretaken for the circuits shown in Figs. 1 and 2, the shortcircuit admittance matrix of the floating FDNR is givenby

[YD] = G1G2

s2C3C4 RX

[1 −1

−1 1

]= Di

s2

[1 −1

−1 1

](8)

Therefore, Di = G1G2/(C3C4 RX ) = 1/(R1 R2 RX C3C4)is computed. As the frequency increases, the absolute valueof the negative resistance also increases. Both resistors butno capacitors of the circuits in Figs. 1 and 2 are connectedin series to the X-terminals of the CCCIIs for this passiveelement choice thus both circuits can be operated at highfrequencies [32 ]. Also, G1 and G2 can be removed and elec-tronically tunable floating FDNRs employing only groundedcapacitors can be obtained.

The grounded resistors of the proposed circuits canbe implemented employing voltage-controlled groundedresistors using CMOS transistors to tune the circuitselectronically [33].

It is essential to mention that if the Z + and Z− terminalsof the first DO-CCCII are interchanged, negative floatinginductor and capacitor, frequency dependent positive resis-tance and admittance converter with a negative multiplierare obtained.

If non-ideal gains α, γ and β are considered for thecircuit in Fig. 1, the short circuit admittance matrix in (2)converts to

[Yn1] = Y1Y2α2α4β1β2

Y3Y4 RX

[α1β3 −α1β4

−β3γ1 β4γ1

](9)

It is trustworthy to note that under non-ideal gain effects,the first presented simulator is lossless floating inductanceand capacitance depending on the passive element selection.

As stated in [34], the first proposed inductor is both shortcircuit and open circuit stable because the non-ideal gainsare in the form of multipliers.

If parasitic resistance (Rx in series ideally equals to zeroand Ry = 1/Gy and Rz = 1/Gz in parallel ideally equal toinfinity) and capacitance (Cy and Cz in parallel ideally equalto zero) effects on the impedances of the circuit in Fig. 1 areconsidered, the following impedances are obtained:

(a) Second-port is grounded.

Zin1 = V1

I1=

(1

s(CZ1+ + CY 3) + G Z1+ + GY 3

)//ZL

(10)

Here,ZL =(Y3+s(CZ2+CY 1)+G Z2+GY 1)(Y4+s(CZ4+CY 2)+G Z4+GY 2)RX(

Y11+RX1Y1

) (Y2

1+RX2Y2

)(11)

(b) First-port is grounded.

Zin2 = V2

I2=

(1

s(CZ1− + CY 4) + G Z1− + GY 4

)//ZL

(12)

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164 Analog Integr Circ Sig Process (2006) 49:161–166

Fig. 3 Internal structure of the DO-CCCII

Fig. 4 Parasitic impedances of the Z terminals of the DO-CCCII

Also, if Z P1 = 1/(s(CZ1+ + CY 3) + G Z1+ + GY 3) andZ p2 = 1/(s(CZ1− + CY 4) + G Z1− + GY 4) are defined, theshort circuit admittance matrix in (2) using Eqs. (10)–(12)turns to

[Y ] =[ 1

Z P1//ZL− 1

ZL

− 1ZL

1Z P2//ZL

](13)

Note that the terms 1/(s(CZ1+ + CY 3) + G Z1+ + GY 3)and 1/(s(CZ1− + CY 4) + G Z1− + GY 4) in (10) and (12) areeffective at very high frequencies. There are also high andlow frequency limitations depending on the passive elementselection.

If Y1 = G1, Y2 = G2, Y3 = sC3 and Y4 = sC4 aretaken for the circuit in Fig. 1 as in case V, the first de-veloped circuit has limitations at low frequencies due toterms s(C3 + CZ2 + CY 1) + G Z2 + GY 1 and s(C4 + CZ4 +

CY 2) + G Z4 + GY 2 as given in (11) thus the limit at lowfrequencies is found as

f � 1

2πmax

{G Z2 + GY 1

C3 + CZ2 + CY 1,

G Z4 + GY 2

C4 + CZ4 + CY 2

}(14)

As it is seen from (14), C3 and C4 should be chosen largein order to decrease the limit at low frequencies.

Fig. 5 A band-pass filter example

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Analog Integr Circ Sig Process (2006) 49:161–166 165

Fig. 6 Both of the ideal and simulated responses of the filter in Fig. 5. ––– Ideal response - - - - - Simulated response

Also, if Y1 = sC1, Y2 = sC2, Y3 = G3 and Y4 = G4

are chosen as in case IV, the limitation at high frequenciesoccurs thus the limit at high frequencies is found to be

f � 1

2πmin

{1

C1 RX1,

1

C2 RX2,

G3 + G Z2 + GY 1

CZ2 + CY 1,

G4 + G Z4 + GY 2

CZ4 + CY 2

}(15)

It is seen from (15) that C1 and C2 are chosen as smallas possible and also RX1 and RX2 are reduced using properdesign so as to increase the high frequency performanceof the circuit. On the other hand, the terms (G3 + G Z2 +GY 1)/(CZ2 + CY 1) and (G4 + G Z4 + GY 2)/(CZ4 + CY 2) in(15) are effective at very high frequencies.

3 Simulation results for the proposed inductor

In order to illustrate the frequency domain performance ofthe proposed network in Fig. 1, it is simulated with SPICEprogram. The DO-CCCII is simulated using the internalstructure in Fig. 3 with DC power supply voltages equalto ± 2.5 V. The CCCII realization is simulated with the pa-rameters of the bipolar junction transistors in [35].

Parasitic impedances of the Z + and Z− terminals ofthe CCCII in Fig. 3 are depicted in Fig. 4 in which parallelparasitic resistances RZ+ = RZ− = 40.4 k� and parallelparasitic capacitances CZ+ = CZ– = 2.3 pF are calculatedusing SPICE program.

In order to show the frequency domain performance of theproposed circuit, the second-order band-pass filter examplein Fig. 5 is simulated with SPICE program thus I01 = I02

= 1000 µA, I03 = I04 = 26 µA, G1 = G2 = G4 =1 mS and C3 = 0.5 nF are chosen to obtain inductanceLeq = 0.5 mH. Furthermore, I01 = I02 = 1000 µA, I03

= I04 = 26 µA, G1 = G3 = G4 = 1 mS and C2 =0.5 nF are taken to obtain capacitance Ceq = 0.5 nF. Also,Req = 1 k� is chosen. Both of the ideal and simulated band-pass (Vout/Vin) filter responses are depicted in Fig. 6 in whichresonance frequency (fo) and quality factor (Q) are computedas 318.3 kHz and 1, respectively.

4 Conclusion

The proposed circuits in this paper employ only groundedpassive components, and require no critical componentmatching constraints thus it is easy to fabricate the presentedcircuits in fully IC technology. The values of the floating in-ductor, capacitor, FDNR and the multiplier of the groundedto floating admittance converter can be changed electroni-cally in IC process. It is expected that the proposed inductorsimulators will be very useful in analog filter designs, para-sitic inductor cancellations and oscillator realizations.

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