off-chip interconnects in wireless hardware — a tutorial ... · off-chip interconnects in...

October 27, 2014 Jan Hesselbarth

Off-Chip Interconnects in Wireless Hardware — a tutorial : technologies and trends —

by Jan Hesselbarth, University of Stuttgart

FP7–ARTISAN training, Belfast, October 27, 2014

Outline:

Introduction

Solder contacts

Wire bonds

Flip chip bonds

On-chip antennas and radiation coupling

< 1 >


Why Off-Chip Interconnects ?

Required. Multi-disciplinary. Not following Moore‘s law. Expensive

< 2 >

Integrated circuit:- mostly for signalprocessing

- low voltage, low power

- cheap

Antenna(s)

Sensors

Actuators

Data I/O

Power supply

Thermal / cooling

Interconnects.

Issues:- performance

. RF

. thermal

. mechanical- flexibility- testabilty- form factor- weight- cost cost cost


A bit of history: The first transistor contacted

… the first bipolar transistor by Bardeen, Brattain, Shockley, 1947

< 3 >

[ wik

iped

ia]


A bit of history: The first russian color TV

… 1970: semiconductors were mostly tubes and passives had wire contacts

< 4 >

[ you

tuve

]


Integrated circuits – Two levels of packaging

… in the majority of cases, to reduce overall cost, integrated circuits are

1st placed into a package ( first level packaging), eg, by wire bonds;

2nd soldered onto a circuit board ( second level packaging), eg, SMT

< 5 >

… this basic concept has not much changed since the early 1970s

[ wik

iped

ia]

die attachleadframe

wire bond die

mold

DIL package


Outline:

Introduction

Solder contacts

Wire bonds

Flip chip bonds



Second level packaging – Soldering (1/2)

… makes a solid connection between metals at not-so-high temperatures

< 6 >

phase diagram of PbSn:… the solder is a mixture of (two) metals,

to reduce the melting temperature

… the phase diagram of the metalmixture shows the temperatureswhere one part or the other is solid or liquid

… the mixture is eutectic when there is a complete transition between liquid and solid at a single temperature

… in reality, solder is often non-eutectic as parts of the to-be-soldered metals go into solution

… eutectic solder examples: Sn48In52: 117°C; Sn63Pb37: 183°C;Sn95Ag4Cu: 217°C; Au80Sn20: 280°C

[ wik

iped

ia]


Second level packaging – Soldering (2/2)

… „lead-less solder“ (i.e., Sn95Ag4Cu) needs higher soldering temperatures

< 7 >

… the liquid solder “takes” contact metal into solution – thin traces disappear(never use Sn-solder on Au thin-/thick-film), thick contacts may change solder joint metallurgy causing bad connections (use Ni barrier)

… different solders for different temperatures allow for multi-level soldering. Example:

[ Hub

er+S

uhne

r]

1) AuSn (~300°C) to solder metalbaseplate on ceramic backside2) SnAg (~220°C) to solder SMTcomponents & flex connections3) glueing & wire-/flipchip-bonding chips4) SnAg (~220°C) flux-less to soldercover using locally embedded heaters


Outline:

Introduction

Solder contacts

Wire bonds

Flip chip bonds



First level packaging – Wire bonds (1/3)

… in the vast majority of cases, chips arebonded into a plastic package

< 8 >

[ mic

row

aves

&rf,

Jun

e 20

, 201

3 ]

die attachleadframe

wire bond die

mold

… pro: protected: easy handling, marking,shipping, mounting, soldering, …

… con: heatsinking (higher thermal resis-tance), RF performance deteriorated

Intel 8742



… for modern chips with many contacts,wire bonds may become very dense, or chips even may be stacked

< 9 >

[ Fraunhofer IZM ] [ wikipedia ]

… this is typically not (yet?) the case for RF chips


… a bond wire is placed between two landing pads

- bond wire diameter 20…100 μm or ribbon of width 20…200 μm

- Au or Al

- wire and pad are connected by pressure, friction (eg. ultra-sonicvibration) and heat (eg. pre-heated board to 120°C for Au bonds)

< 10 >

… wire bond technology for RF is black magic with many parametersbut is astonishingly reproducible



Wire bonds – ball-stitch bonds

< 11 >

… ball-stitch bonding technique:

- cheap/standard tools

- long bonds not good for RF

flash forms ball 2x „pressure + ultra-sonic“ „clamp + up“

capillary tool

[ SP

T ]


Wire bonds – wedge-wedge bonds

… wedge-wedge bonding technique

- rather specific tools

- short RF bonds feasible

< 12 >

2x „pressure + ultra-sonic“ „clamp + up“

wedge tool

[ SP

T ]

… short vs.„very-short“RF bond :

[ Fra

unho

fer I

ZM ]


Wire bond frequency behaviour (1/4)

… the chip-to-board bondwire can be seen as series inductance

< 13 >

bondwire ≅ 2 ln 4 nHcm H … distance wire to planar groundD … wire diameter

… a very rough estimate: a 1mm long bond wiregives -10 dB reflection already at approx. 5 GHz!

… series inductance of a thin wire parallel over ground:

… the chip-to-board bondwire shows low-pass behaviour:

board

chipbond ground

heatsink frequency / GHz|S

11| /

dB

… better performance at higher frequency by lowering the bond inductance:shorter bonds, thicker bonds (or two parallel bonds or ribbon)



… a shorter bond will push the lowpass edge frequency upwards:

< 14 >

board

chipbondground

heatsink frequency / GHz

|S11

| / d

B

… compensation of bondwire inductance by shunt capacitancewill push the lowpass edge frequency upwards:

frequency / GHz

|S11

| / d

B

„L“„C“„L“ „LCLCL“ !



… bond length cannot be shortened infinitely. For narrowbandsystems, half-wavelength bondwires could be a solution

- λ/2 GSG bondwires for 122 GHz:

< 15 >

[S. Beer, KIT Karlsruhe]



… perhaps new wirebond technology could lead to shorter bonds:

- three-turn coil made of inkjet-printed sintered colloidalsuspensions; „wire“ diameter here: < 2 μm

< 16 >

[N. S

chirm

er, J

. Hes

selb

arth

et a

l., A

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ett.,

201

0]


Outline:

Introduction

Solder contacts

Wire bonds

Flip chip bonds



Flip chip bonds

… much shorter and thicker than a wirelower inductance ☺

< 17 >

… can be

- directly glued,

- soldered,

- thermosonic-bonded,

- glued stud bumps

not really a processfor series production

bumps made by platingof solder plus reflow

tricky but highestcontact density

„balls“ can be madefrom studs with „coining“

[ FH

Buc

hs ]

low-temperature process


Flip chip bonds – Related RF problems

… the chip-to-board transition (in particular, CPW) has lowest inductance ☺

< 18 >

… : on-chip top metal and board top metalcreate a parallel-plate transmissionline which causes coupling, resonance effects and possiblya strong excitation of surface waves

… : on-chip transmission-line structures are de-tuned by the proximityof board dielectric or board top metal or – worst – underfill

… : thermal expansion mismatch between chip and board is difficultto accomodate if underfill is not an option

… : heat removal needs special attention (problems can be alleviatedby additional bumps or thermally conductive underfill or backsideheat pads)

… : inspection, test, repair is rather difficult


Outline:

Introduction

Solder contacts

Wire bonds

Flip chip bonds



… example 1 : on-chip dipolecouples directly to E-fieldof rectangular waveguideTE10 mode

- bandwidth 20…30% ok

- expensive mount

- chip test ?

Radiation coupling from chips into guided waves (1/3)

… insertion loss of both bond wires and compensation structuresbecomes prohibitive beyond ~ 200 GHz

< 19 >

… off-chip transmission media beyond few hundred GHz are rectangularwaveguide or some dielectric waveguide (not: microstrip, CPW), therefore coupling from chip to microstrip/CPW makes no sense

bias

wav

egui

de

[W.R. Deal et al., “Demonstration of a 0.48 THz Amplifier Module Using InP HEMT Transistors,” IEEE Microw. Wireless Comp. Lett., May 2010]

InP 480 GHz LNA:


… example 2 : on-chip dipolecouples to E-field of dielectricimage guide Ex11 mode

- narrowband ~10%

- compatible with PCBtechnology except forimage guide dielectric layer

- chip test possible usingdielectric probes (research)


< 20 >

25 mm

[N. Dolatsha, J. Hesselbarth, “Millimeter-wave chip-to-chip transmission using an insulated image guide excited by an on-chip dipole antenna at 90 GHz,” IEEE Microw. Wireless Comp. Lett., May 2012]


… example 3 : spherical dielectricresonator placed on-chip couples to waveguide(research):

- placement of sphere in asmall on-chip ditch whichis made in the back-end-of-line chip process

- can be placed anywhereon the chip (not at the edge)

- lowest transmission loss fromtransistor to waveguide

- narrowband ~10%

- standard chip test with probesbefore sphere is mounted?


< 21 >

board

chip

line

dielectricresonatorsphere

air-filledmetalwaveguide

hole


… on-chip antennas for wireless transceiversare the dream of system engineers:

- baseband-only chip interface- small cheap and scales with Moore‘s law- ?

Radiation from chips – on-chip antennas (1/4)

< 22 >

… in reality, design of on-chip antennas has many specific problems:

- size: a length dimension of half a free-space wavelength is required.Smaller structures are much worse. An usage area of (λ/2)2 will showa directivity of approx. 5…7 dBi.Chip area of that size can be veryexpensive!

15 GHz on-chip meanderdipole of 2mm length

[K.K. O et al., „On-chip antennas in silicon ICs and their application,“ IEEE Trans. Electron Dev., July 2005]



< 23 >

chip

undopedsilicon wafersilicon lens

silicon chip

- substrate modes: due to thehigh εrel of the chipsubstrate, the on-chipantenna tends to„radiate into the chip“(dipole: 5% into airand 95% into silicon)

a hemispherical lenshelps to avoid reflectionsfrom chip backside

- packaging: any packaging in the reactive near-field will de-tune the antenna, whereasfurther away it will act as a radome

[A. Babakhani et al., „A 77 GHz 4-element phased array receiver with on-chip dipoleantennas in silicon,“ ISSCC 2006]


- loss / efficiency / gain: silicon „normally“used for CMOS, BiCMOS etc. isconductive to an extend that it actslike a RF absorber. GaAs and InPare much better in that regard. Useof the back-end layers only (andshielding the lossy silicon) leadsto very thin and lossy / narrowbandantennas.


< 24 >

- testing: the chip needs to betested in radiation modeor with probes beforeadditional antennastructures are mounted.This is non-standard.

24 GHz on-chip meanderdipole with 10% efficiency

[K.K. O et al., „On-chip antennas in silicon ICs and their application,“ IEEE Trans. Electron Dev., July 2005]

90 GHz on-chip slot ring in CMOS with 7% efficiency

[J.M. Edwards, G.M. Rebeiz, „High-efficiency silicon RFIC millimeter-wave elliptical slot-

antenna with a quartz lens,“ IEEE AP-S 2011]



< 25 >

… best compromise on all (?) mentionedissues is to place the excitation strucurein the back-end layers on top of the chip(shielding the substrate) and to excitatesome resonating structure above the chip.

Additional requirements like small footprintand testability need to be met (to be shown), then the dielectric resonating sphere is best.

[Y.-C. Ou, G.M. Rebeiz, “On-chip slot-ring andhigh-gain horn antennas for millimeter-wave wafer-

scale silicon systems,” IEEE Trans. MTT, 2011]

[J. Hasch, U. Wostradowski, S. Gaier, T. Hansen, “77 GHz radar transceiver with dual integrated antenna elements,” GeMiC, 2010]

metal horn

ring sloton quartzmicrostrip

feed on chip

patch on quartz

frequency-scaled prototype of a dielectricresonating sphere antenna fed by microstripline resonators on very thin substrate

off-chip interconnects in wireless hardware — a tutorial ... · off-chip interconnects in...

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