nuvoton nuc140 32-bit arm cortex-m0 microcontroller

7/31/2014 Getting started with Nuvoton NUC140 32-bit ARM cortex-M0 Microcontroller

http://nuvotonnuc140.blogspot.in/ 1/8

This blog presents articles on using KEIL and getting started with Nuvoton's NUC140 series 32 bit ARM cortex-M0

Microcontrollers. All these articles are based on Nuvoton's NUC140 EVM board. These articles are aimed at

helping/tutoring and sharing technical articles on programming the 32 bit microcontroller from Nuvoton. Please share

your comments and suggestions, if any (politely). The idea of this blog is learn from sharing knowledge so everyone can

benefit.

Getting started with NuvotonNUC140 32-bit ARM cortex-M0Microcontroller

Wednesday, July 30, 2014

Know your chip on NUC140 EVM board

The highlights of the NUC140 chip on the learning board:

1. Maximum supported CPU frequency via PLL is 50Mhz.

2. Maximum supported CPU frequency via external crystal is 24Mhz

3. Has inbuilt RTC with crystal of value 32.768Khz soldered to the learning board.

4. It can also run out of internal oscillator value of 22.1184Mhz.

5. Know your NUC140 series on your Learning board (EVM) of Nuvoton. The CPU name is

NUC140VE3AN*.

NUC series in Nuvoton means it is a 32 bit microcontroller series.

1 in letter 140 means: It has 1 core only i.e. Cortex M0.

4 in letter 140 means: It belongs to the connectivity range.

0 in letter 140 currently does not hold any specific meaning.

V in VE3AN means: LQFP100 package

E in VE3AN means: 128KB APROM size

3 in VE3AN means: 16KB RAM size

A in VE3AN is reserved for future feature additions/revisions

N in VE3AN means: temperature range supported by chip is: -40C to +85C.

The chip is based on ARM v6-M architecture.

8. It has 128KB for Program FLASH, 16KB for SRAM, 4KB Data flash and 4KB of LDROM

(bootloader) and 76 IOs.

9. The page erase size of the dataflash is 512 bytes.

10. It has an inbuilt 12 bit resolution SAR ADC.

11. It has an inbuilt temperature sensor with an accuracy of +/-1 degree.

12. For the automotive line, it has support for BOSCH CAN 2.0 A/B and LIN support.

13. It has 4-32bit timers, 3-UARTs, 4-SPI channels, 2-I2C channels, 1-2.0v full-speed USB.

14.It has 8-16bit PWM channels and 2-Analog Comparators and 1-12S/AC97.

*There are other versions of NUC140 also available as per this ordering mechanism:

Rohit

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Know your chip on NUC140 EVM board

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All About your NUC140



Posted by Rohit at 11:07 AM No comments:

Labels: 32-bit ARM CortexM0, NUC140

Location: Ahmedabad, Gujarat, India

The nested vectored interrupt controller (NVIC) supports tail-chaining and late-arrival to assist in

developing true real time embedded applications.

Tail chaining is a method where the ISR, when it has executed and is about to return

back to the main method and is in the process of restoring the state of the registers, if

during that period another ISR occurs then the overhead of restoring and saving of the

state is reduced by directly allowing the NVIC to jump from one ISR to the other and

there by saving time in ISR overheads.

Late-arrival is a method where when one ISR is about to get executed (but not

started), if another higher priority ISR fires then the NVIC allows the higher priority ISR

to execute first there by eliminating any delay to allow the most highest priority ISR to

execute.

It is very important to understand the variety of clock options provided by the controller

which clocks the various peripherals. It is hence important to understand the clock

options to calculate the clock signal timings.

NUC140 Hardware chip ordering options as provided by Nuvoton

The CLOCK CONTROLLER of this chip:

Recommend this on Google

Monday, March 31, 2014

Embedded World's - Hello World - Toggling the GPIO.

Coding conventions followed in CMSIS:

1. All the data ty pes used in CMSIS is based out of stdint.h file. Data structures for core

registers are defined in the CMSIS header core_cm0.h file.

2. The core registers, peripheral registers and the CPU instructions follow capital

naming convention. Eg: NVIC->ISER[0], GPIOA->ISRC,

3. Peripheral access functions and interrupts use camel casing convention. Eg:

DrvGPIO_Open().

4. CMSIS allows C++ like commenting method (eg: // this is used for commenting.)

Finally , we are there on the m ain subject : Getting started!

So let us attempt to write our first example for toggling GPIO (Embedded world's "HELLO

World" using Keil. It should be straight forward port for IAR and other tool chains, I guess

though I cannot comment on that much since I have not had an experience using them for

this controller.



Understanding the NU-LB-NUC140 board for the LED experiment:

The chip used on this EVM board is NUC140VE3CN. This board is powered by an external 12MHz

crystal as well as 32.768Khz crystal for RTC applications. In this experiment we will attempt our

first "Hello World" program by lighting up the LED for sometime and switching it off and continue

doing that. The LEDs on this EVM board are connected on GPIO-PortC on pins -12,13,14 & 15.

These LEDs are connected in SINK mode. Hence to turn on a LED you must place a ZERO on the

GPIO pin and to switch off you must place a ONE.

NUC140 has 80 general purpose IOs.

80 IOs are arranged in GPIOA, GPIOB, GPIOC, GPIOD, GPIOE.

On reset all IO pins stay in Quasi-Bidirectional mode.

IOs as outputs can support source/sink capability.

First Step: Creating your project in KEIL:

1. Open KEIL -> New uVision Project ->



Here is the main program:

#include "NUC1xx.h"

#include "Driver\DrvSYS.h"

#include "Driver\DrvGPIO.h"

void delay_loop(void)

{

uint32_t i,j;

for(i=0;i



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Posted by Rohit at 6:22 PM 2 comments:

Labels: 32-bit ARM CortexM0, Hello World on NUC140, Toggling GPIO on a 32bit uC

//Considering 1tick = 12Mhz so for 1 sec, reload value = 12000000.

SysTick->LOAD = 12000000; //Reload value in register for SysTick for 1 sec delay

SysTick->VAL = (0x000000); //default value of SysTick Current value register.

//Switch on sysTick timer.

//System Clock source is (optional) external reference clock

SysTick->CTRL = (1



Posted by Rohit at 4:04 PM No comments:

Labels: NUC140, NUC140 Device interfaces

Com piler support built into CMSIS: Currently three main compilers are supported by

CMSIS namely , armgcc from ARM REAL v iew, iccarm from IAR EWARM and gcc from GNU

compiler collection. All the functions in the core peripheral access lay er are reentrant and

can be called from different interrupt serv ice routines. The exception handers are given a

suffix __Handler while the external interrupt handlers are given a suffix __IRQHandler.


What is CMSIS?

CMSIS is an acrony m for Cortex Microcontroller Software Interface Standard.

CMSIS is an abstract lay er that supports developers and vendors in creating reusable

software components for ARM Cortex-M based sy stems. This lay er is useable for Cortex-

M0,M0+, M1 M3/M4 lay ers as well.

A brief glance into Cortex-M0,M0+, M1, M3 and M4 architectures:

Cortex-M0: The ARM Cortex-M0 processor is the smallest ARM processor

available. The exceptionally small silicon area, low power and minimal code

footprint of the processor enables developers to achieve 32-bit performance at

an 8-bit price point.

Supports 3-stage pipeline, thumb2, hardware-single-cy cle (32x32)

multiply hardware.

Supports 1 NMI and 32 phy sical interrupts.

Has only 56 instructions and has 'C-friendly ' architecture.

Cortex-M0+: The ARM Cortex-M0+ processor is an adaption of Cortex-M0 but

with more improved performance and reduced energy footprint.

Supports 2-stage pipeline, thumb2, hardware-single-cy cle(32x32)

multiply hardware.

Cortex-M1: The ARM Cortex-M1 processor is the first ARM processor designed

specifically for implementation in FPGAs.

Supports 3-stage pipeline, thumb2 and big & little endian

configuration.

Cortex-M3: The ARM Cortex-M3 processor is the industry -leading 32-bit

processor for highly deterministic real-time applications, specifically developed

to enable partners to develop high-performance low-cost platforms for a broad

range of dev ices including microcontrollers, automotive body sy stems, industrial

control sy stems and wireless networking and sensors.

The Cortex-M3 NVIC is highly configurable at design time to deliver up

to 240 sy stem interrupts with indiv idual priorities, dy namic

reprioritization and integrated sy stem clock.

Supports 1 NMI and 240 phy sical interrupts with 8 to 256 level

priorities.

Supports hardware div ide, single cy cle-multiply and saturated math

support.

Cortex-M4: The ARM Cortex-M4 processor is the latest embedded processor

by ARM specifically developed to address digital signal control markets that

demand an efficient, easy -to-use blend of control and signal processing

capabilities.

Supports 3-stage pipeline with branch prediction and thumb2.

Supports hardware-div ide, 8/16 bit SIMD arithmetic.

Supports single precision floating point unit.

Supports Memory protection unit and deterministic operations.



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Posted by Rohit at 2:27 PM No comments:

Labels: CMSIS, Know ing CMSIS

Continuing further on CMSIS:

In order to reduce cost and software complexity and the fact that there are too rapid changes on

the technology front, CMSIS provides a uniform hardware abstraction layer that governs the way we

write and debug software by ensuring software re-useability.

CMSIS structure consists of three layers:

1. Core peripheral Access Layer (CPAL)

2. Middleware Access Layer (MAL)

3. Device peripheral Access Layer (DPAL)

Functionality of each CMSIS layer:

Core Peripheral Access Lay er: This lay er is prov ided by ARM. The lowest level defines

addresses, and access methods for common components and functionality that exists in

every Cortex-M sy stem. Access to core registers, NVIC, debug subsy stem is prov ided by

this lay er.

Middleware Access Lay er:This layer is defined by ARM, but is also adapted by silicon

vendors for their respective devices.The Middleware Access Layer defines a common API for

accessing peripherals.

Device Peripheral Access Lay er:This lay er is prov ided by the silicon vendor and

contains the hardware register addresses and other dev ice specific access functions.

CMSIS functional Flow (Courtesy: https://w w w .doulos.com)




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