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Note su Note su LLinear inear FFeedback eedback SShifthift RRegisteregister

24/12/201324/12/2013

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A Linear Feedback Shift RegisterLinear Feedback Shift Register is a sequential shiftregister with combinational logic that causes it to pseudo-randomly cycle through a sequence of binary values.

FeedbackFeedback around an LFSR's shift register comescomes fromfrom a a selectionselection ofof pointspoints ((tapstaps)) in the register chain and constitutes XORing these taps to provide tap(s) back intothe register.

Register bits that do not need an input tap, operate as a standard shift register. ItIt isis thisthis feedback feedback thatthat causescausesthe the registerregister toto looploop throughthrough repetitiverepetitive sequencessequences ofofpseudopseudo--randomrandom valuevalue.

The The choicechoice ofof tapstaps determinesdetermines howhow manymany valuesvalues therethereare in a are in a givengiven sequencesequence beforebefore the the sequencesequence repeatsrepeats.

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Pseudo Pseudo RandomRandom BinaryBinary SequenceSequence (PRBS)(PRBS)

It is It is ‘‘randomrandom’’ in a sense that the value of an element of in a sense that the value of an element of the sequence is independent of the values of any of the the sequence is independent of the values of any of the other elements. other elements.

It is It is 'pseudo''pseudo' because it is deterministic and after N because it is deterministic and after N elements it starts to repeat itself, unlike real random elements it starts to repeat itself, unlike real random sequences.sequences.

…… If one know the If one know the ““present statepresent state”” as well as the positions as well as the positions of the XOR gates in the LFSR, of the XOR gates in the LFSR, one can predict the one can predict the ““next next statestate””. This is not possible with truly random events.. This is not possible with truly random events.

…… The The output output stramstram is reversibleis reversible, an LFSR with mirrored , an LFSR with mirrored taps will cycle through the output sequence in reverse taps will cycle through the output sequence in reverse order.order.

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A n-bit Linear Feedback Shift Register (LFSRLFSR) is a nn--bit bit lengthlength shiftshift registerregister with feedback to its input.

The feedback is formed by XORingXORing or XNORingXNORing the outputs of selected stages of the shift register - referredto as 'tapstaps' - and then inputting this to the least significantbit (stage 0).

The 'linear' part of the term 'LFSR' derives from the factthat XOR and XNOR are XOR and XNOR are linearlinear functionsfunctions.

Note also that the LS bitLS bit of the shift register is, byby conventionconvention, shown at the left hand side of the shiftregister, with the output being taken from the MS bitMS bit at the right hand side.

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An LFSRLFSR will produce a pseudorandompseudorandom sequencesequence ofof lengthlength(2(2n n –– 1) 1) states (where n n isis the the numbernumber ofof stagesstages) if the LFSR is of maximal maximal lengthlength (i.e. all possible values (22n n ) minus the “zero state”).

The sequence will then repeat from the initial state for aslong as the LFSR is clocked.

An LFSR is of 'maximal' length when the sequencesequence it generates passes through all possible 2passes through all possible 2nn--1 values1 values.

There can be more more thanthan oneone combinationcombination ofof tapstaps thatthat givegivemaximal maximal lengthlength forfor eacheach LFSRLFSR.

IMPORTANT !IMPORTANT !The LFSR sequencesequence dependsdepends on on

the the seedseed valuevalue, the , the taptap positionspositions and the and the feedback feedback typetype.

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A binary sequence of A binary sequence of N bitsN bits has has m onesm ones and and NN--m zerosm zeros, , is pseudois pseudo--random (PRBS) if its autocorrelation function, random (PRBS) if its autocorrelation function, C(C(νν),),

has only two values:has only two values:C (C (νν) = m ) = m if if νν = 0 (mod N)= 0 (mod N)C (C (νν) = m) = mcc if if νν ≠≠ 0 (mod N)0 (mod N)

wherewherecc = (m = (m −− 1)/(N 1)/(N −− 1)1)

is called the duty cycle of the PRBSis called the duty cycle of the PRBS..

∑ −=

= +×=

−=1

0)()(

)1(,...,1,0Nj

j jj

j

aaC

Njfora

νν

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In an LFSR, the bits contained in selected positions in In an LFSR, the bits contained in selected positions in the shift register are combined in some sort of function the shift register are combined in some sort of function and the result is fed back into the register's input bit. and the result is fed back into the register's input bit.

By By definition,thedefinition,the selected selected bit values are collected bit values are collected before the register is clockedbefore the register is clocked and the result of the and the result of the feedback function is inserted into the shift register feedback function is inserted into the shift register during the shift, filling the position that is emptied as a during the shift, filling the position that is emptied as a result of the shift.result of the shift.

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Register bits that do not need an input tap, operate Register bits that do not need an input tap, operate as a standard shift register. It is this feedback that as a standard shift register. It is this feedback that causes the register to loop through repetitive sequences causes the register to loop through repetitive sequences of pseudoof pseudo--random value. random value.

The choice of taps determines how many values there The choice of taps determines how many values there are in a given sequence before the sequence repeats. are in a given sequence before the sequence repeats.

The implemented LFSR typically uses a The implemented LFSR typically uses a oneone--toto--many many structurestructure, rather than a many, rather than a many--toto--one structure, since one structure, since this structure always this structure always has the shortest clockhas the shortest clock--toto--clock clock delay pathdelay path..

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The bit positions selected for use in the feedback function The bit positions selected for use in the feedback function are called "taps". The list of the taps is known as the are called "taps". The list of the taps is known as the "tap sequence". "tap sequence".

By convention, By convention, the output bit of an LFSR that is n bits the output bit of an LFSR that is n bits

long is the nlong is the nthth bit;bit;

the input bit of an LFSR is bit 1the input bit of an LFSR is bit 1..

Using XOR functionUsing XOR function …… when the contents of the when the contents of the register are all zeroes, i.e. when the LFSR is in the zero register are all zeroes, i.e. when the LFSR is in the zero state, then the LFSR will never change state!state, then the LFSR will never change state!

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Because each state can have only once succeeding Because each state can have only once succeeding state, state, an LFSR with a maximal length tap sequencean LFSR with a maximal length tap sequence will will pass through every nonpass through every non--zero state once and only oncezero state once and only oncebefore repeating a state.before repeating a state.

One corollary to this behavior is the output bit stream. One corollary to this behavior is the output bit stream. The period of an LFSR is defined as the length of the The period of an LFSR is defined as the length of the stream before it repeatsstream before it repeats. The period, like the state . The period, like the state space, is tied to the tap sequence and the starting value. space, is tied to the tap sequence and the starting value. As a matter of fact, the period is equal to the size ofAs a matter of fact, the period is equal to the size ofthe state space. The longest period possible corresponds the state space. The longest period possible corresponds to the largest possible state space, which is produced by to the largest possible state space, which is produced by a maximal length tap sequence. (Hence "maximal length").a maximal length tap sequence. (Hence "maximal length").

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A maximal length tap sequence describes the exponents in A maximal length tap sequence describes the exponents in what is known as a what is known as a primitive polynomial mod 2primitive polynomial mod 2..Example,Example,a tap sequence of 4, 1 describes the primitive polynomiala tap sequence of 4, 1 describes the primitive polynomialx^4 + x^1 + 1.x^4 + x^1 + 1.

Finding a primitive polynomial mod 2 of degree n (the Finding a primitive polynomial mod 2 of degree n (the largest exponent in the polynomial) will yield a maximal largest exponent in the polynomial) will yield a maximal length tap sequence for an LFSR that is n bits long.length tap sequence for an LFSR that is n bits long.

There is no quick way to determine if a tap sequence is There is no quick way to determine if a tap sequence is maximal length. However, maximal length. However, there are some ways to tell if there are some ways to tell if one is not maximal lengthone is not maximal length::1) Maximal length tap sequences always have an even 1) Maximal length tap sequences always have an even number of taps.number of taps.2) The tap values in a maximal length tap sequence are all 2) The tap values in a maximal length tap sequence are all relatively prime.relatively prime.

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A tap sequence like 12, 9, 6, 3 will not be maximal length A tap sequence like 12, 9, 6, 3 will not be maximal length because the tap values are all divisible by 3.because the tap values are all divisible by 3.Discovering one maximal length tap sequence leads Discovering one maximal length tap sequence leads automatically to another. automatically to another.

If a maximal length tap sequence is described by If a maximal length tap sequence is described by [n, A, B, C][n, A, B, C], ,

another maximal length tap sequence will be described by another maximal length tap sequence will be described by [n, n[n, n--C, nC, n--B, nB, n--A]A]. .

Thus, if [32, 3, 2, 1] is a maximal length tap sequence, Thus, if [32, 3, 2, 1] is a maximal length tap sequence, [32, 31, 30, 29] will also be a maximal length tap [32, 31, 30, 29] will also be a maximal length tap sequence.sequence.

An interesting behavior of two such tap sequences is An interesting behavior of two such tap sequences is that that the output bit streams are mirror images in timethe output bit streams are mirror images in time..

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PseudoPseudo--RandomRandom Bit Bit SequenceSequence generatorgenerator

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Feedback Feedback PolynomialPolynomial

119116112

181412

14171819

11131416

4101112

4568

34

12

++++

++++

++++

++++

++

++−

xxxxxxxxxxxx

xxxxxxxxbit

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A 4A 4--bit bit registerregister withwithfeedback feedback tapstaps at the 3at the 3--th and 4th and 4--th th bitsbits

isis maximal maximal lengthlength..

44--BITBIT

21 3

++

4PRBS outputPRBS output

All 15 states!!Maximal length

1111011100110001100001000010100111000110101101011010110111101111

……

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44--BITBIT

21 3

++

4PRBS outputPRBS output

1111011100111001110011101111

……

Only 6 states!!

A 4A 4--bit bit registerregister withwithfeedback feedback tapstaps at the 2at the 2--nd and 4nd and 4--th th bitsbits

isis notnot maximal maximal lengthlength..

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44--BitBit LFSR [4, 1] States and OutputLFSR [4, 1] States and Output

15)12(:

4 =−

LengthMaximal

XORXOR

11 44

A 4A 4--bit bit registerregister withwithfeedback feedback tapstaps at the 1at the 1--th and 4th and 4--th th bitsbits

isis maximal maximal lengthlength..

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The implemented LFSR uses a oneone--toto--manymany structurestructure, rather than a manymany--toto--oneone structurestructure, since this structurealways has the shortest clock-to-clock delay path.

The need to combine many taps into a single feedback nodecan lead to multiple levels of logic. The maximum clock rate of the above 88--bit LFSR in bit LFSR in manymany--toto--oneone topologytopology, will bedependent on the propagation delay through the feedback logic, minimizing this will increase the maximum clock rate.

LFSRLFSR88--bitbit

tapstaps: 2,3,4,8: 2,3,4,8

ManyMany--toto--oneone structurestructure

21 43 65 87

++++++

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OneOne--toto--manymany structurestructure

It has the shortest clock-to-clock delay path.

There is now only one gate between each stage and the maximum clock rate is now dependent on the propagationdelay through that one gate instead of the delay through the two levels of gates in the many-to-1 topology.

LFSRLFSR88--bitbit

tapstaps: 2,3,4,8: 2,3,4,8

11 22 33 44 55 66 77 88

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1 N-10

++ManyMany--toto--oneone structurestructure

FlipFlip--Flop Flop ““numberingnumbering””

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11-- LFSR 16LFSR 16--bit Fibonacci VHDL Code: bit Fibonacci VHDL Code: manymany--toto--oneone structurestructure

The feedback tap numbers in white correspond to a primitive polynomial so the register cycles through the maximumnumber of 65535 (216 - 1) states excluding the all 0's state. The state ACE1 shown (hex) will be followed by 5670 (hex).

2 N1

++

ManyMany--toto--oneone structurestructure forfor NN--bitbit LFSRLFSR

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The The followingfollowing code code isis anan implementationimplementation ofof thisthis 1616--bit bit Fibonacci LFSR: Fibonacci LFSR:

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The initial value of the LFSR, called the seedinitial value of the LFSR, called the seed, is initialized to “000...01” in the code but it could be changedit could be changed to any N-bit number.The tapstaps usedused forfor thisthis 1616--bit Fibonacci LFSRbit Fibonacci LFSR are [16,14,13,11][16,14,13,11] so it's why the polynome constant in the VHDL file above is coded as “1011010000000000” in binary.

If you want to try for exampleexample to simulate a 55--bit Fibonacci bit Fibonacci LFSRLFSR, just change the N constant to 5 in the code above and the polynome constant to “11101” corresponding to the tapstaps[5,4,3,1][5,4,3,1]. The LFSR cycles through (2(255 -- 1)1) = 31 different states before it repeats.

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22-- LFSR 16LFSR 16--bit bit GaloisGalois VHDL Code: VHDL Code: oneone--toto--manymany structurestructure

Let's have a look at this linear feedback shift register.The register numbers in whiteThe register numbers in white correspond to the same primitive polynomial as the Fibonacci example but are counted are counted in reverse to the shifting directionin reverse to the shifting direction. This register also cycles through the maximal number of 65535 states excluding the all 0's state. The state ACE1 (hex) shown will be followed by E270 (hex).

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The The followingfollowing code code isis anan implementationimplementation ofof thisthis 1616--bitbitGaloisGalois LFSR: LFSR:

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The tapstaps usedused forfor thisthis 1616--bit bit GaloisGalois LFSRLFSR are [16,14,13,11][16,14,13,11] so it's why the polynome constant in the VHDL file above is coded as “1011010000000000” in binary.

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http://www0.egr.uh.edu/Courses/Ece/ECE5440/ece5440_Lhttp://www0.egr.uh.edu/Courses/Ece/ECE5440/ece5440_LFSR_Counters.pdfFSR_Counters.pdf

LFSRTestbench.zipLFSRTestbench.ziphttp://www.fpga4fun.com/Counters3.htmlhttp://www.fpga4fun.com/Counters3.html

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RandomRandom bit bit generatorgenerator in VHDLin VHDL

ENTITY top ISPORT (

clk : IN bit;noisebit : OUT bit);

END top;ARCHITECTURE translated OF top ISSIGNAL lfsr : bit_vector(17 DOWNTO 0) := "000000000000000000";BEGINnoisebit <= lfsr(0) ;PROCESSBEGINWAIT UNTIL (clk'EVENT AND clk = '1');lfsr <= lfsr(16 DOWNTO 0) & (lfsr(17) XNOR lfsr(10));END PROCESS;

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Code for implementing a 16Code for implementing a 16--bit PRBS realized by bit PRBS realized by writing VHDL programwriting VHDL program

In the program the logic implemented is realized by In the program the logic implemented is realized by shifting the input through the Dshifting the input through the D--flip flops and feed flip flops and feed backing the outputs of some registers known as taps again backing the outputs of some registers known as taps again into the first register after passing them through a XOR into the first register after passing them through a XOR gate.gate.The process of realizing LFSR is carried out by first The process of realizing LFSR is carried out by first developing the VHDL code for a Ddeveloping the VHDL code for a D--flip flop. The same Dflip flop. The same D--flip flop code is then called 16 times in the main program flip flop code is then called 16 times in the main program code to realize the required LFSR.code to realize the required LFSR.In the developed code tapings are taken from 1In the developed code tapings are taken from 1stst ,2,2ndnd ,4,4thth

and 15and 15thth taps so as to obtain the maximum length of taps so as to obtain the maximum length of binary digits produced.binary digits produced.It is necessary that the initial input to the PRBS It is necessary that the initial input to the PRBS generator be equal to 1, the output of the XOR gate.generator be equal to 1, the output of the XOR gate.

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VHDL CODE FOR DVHDL CODE FOR D--FLIP FLOPFLIP FLOP

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VHDL CODE FOR PRBSVHDL CODE FOR PRBS

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VHDL CODE FOR PRBSVHDL CODE FOR PRBS

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VHDL CODE FOR PRBSVHDL CODE FOR PRBS

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Generatore digitale di impulsi con ritardi Generatore digitale di impulsi con ritardi ““randomrandom”” [1/2][1/2]

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Generatore digitale di impulsi con ritardi Generatore digitale di impulsi con ritardi ““randomrandom”” [2/2][2/2]

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Generatore di Pattern Digitale Analizzatore di Stati LogiciSistema sotto Test

Utilizzo di un Generatore di Pattern Digitale (Utilizzo di un Generatore di Pattern Digitale (GPDGPD) e di un ) e di un Analizzatore di Stati Logici (Analizzatore di Stati Logici (ASLASL) ) per stimolare e rivelare la risposta di un per stimolare e rivelare la risposta di un Sistema Sotto Test (Sistema Sotto Test (SUTSUT))

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Schema a blocchi di un Generatore di PatternSchema a blocchi di un Generatore di Pattern

…… un un singolo singolo canalecanale……

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Schema a blocchi di un Generatore di PatternSchema a blocchi di un Generatore di Pattern

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LFSR:LFSR:BibliografiaBibliografia

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http://www.ece.ualberta.ca/http://www.ece.ualberta.ca/~elliott~elliott/ee552//ee552/studentAppNotesstudentAppNotes/1999f//1999f/Drivers_EdDrivers_Ed//lfsr.htmllfsr.html

The Art of Electronics The Art of Electronics -- Horowitz and HillHorowitz and Hill

http://http://emmanuel.pouly.free.fremmanuel.pouly.free.fr//fibo.htmlfibo.htmlXILINX XILINX -- XAPP 052 XAPP 052 -- JulyJuly 7,1996 (7,1996 (VersionVersion 1.1) 1.1)

ApplicationApplication Note Note byby Peter Peter AlfkeAlfke

http://www.markharvey.info/http://www.markharvey.info/fpgafpga//lfsrlfsr//lfsr.htmllfsr.html

http://www0.egr.uh.edu/Courses/Ece/ECE5440/http://www0.egr.uh.edu/Courses/Ece/ECE5440/ece5440_LFSR_Counters.pdfece5440_LFSR_Counters.pdf

LFSRTestbench.zipLFSRTestbench.ziphttp://www.fpga4fun.com/Counters3.htmlhttp://www.fpga4fun.com/Counters3.html

File=thread47313.pdfFile=thread47313.pdf 231213231213

http://www.nunoalves.com/http://www.nunoalves.com/classesclasses//fall11fall11--cpe462/cpe462/slidesslides/topic/topic--09a.pdf09a.pdf

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http://www.fermilecce.gov.it/areahttp://www.fermilecce.gov.it/area--download/finish/download/finish/2323--profprof--angeloangelo--neve/neve/1818--generatoregeneratore--digitaledigitale--didi--ritardiritardi--random.pdfrandom.pdf

http://ethesis.nitrkl.ac.in/59/1/10307017.pdfhttp://ethesis.nitrkl.ac.in/59/1/10307017.pdf

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LLinear inear FFeedback eedback SShifthift RRegisteregister::

Simulazioni con Simulazioni con LLogicogic WWorksorks

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(2(244 –– 1) = 15 stati1) = 15 stati

LFSRLFSR 44--bitbit

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LFSRLFSR 88--bitbit

(2(288 –– 1) = 255 stati1) = 255 stati

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LFSRLFSR 1616--bitbit

(2(21616 –– 1) = 65535 stati1) = 65535 stati