NONVOLATILE SPINTRONICS: PERSPECTIVESON INSTANT-ON NONVOLATILENANOELECTRONIC SYSTEMS

K. L. WANG and P. KHALILI AMIRI*

Electrical Engineering DepartmentUniversity of California, Los Angeles

Los Angeles, CA 90095, USA*pedramk@ucla.edu

Received 21 December 2011Accepted 5 July 2012

Published 7 November 2012

Instant-on nonvolatile electronics, which can be powered on/o® instantaneously without the loss ofinformation, represents a new and emerging paradigm in electronics. Nonvolatile circuits consistingof volatile CMOS, combined with nonvolatile nanoscale magnetic memory, can make electronicsnonvolatile at the gate, circuit and system levels.When high speedmagneticmemory is embedded inCMOS logic circuits, it may help resolve the two major challenges faced in continuing CMOSscaling: Power dissipation and variability of devices. We will give a brief overview of the currentchallenges of CMOS in terms of energy dissipation and variability. Then, we describe emergingnonvolatile memory (NVM) options, particularly those spintronic solutions such as magneto-resistive random access memory (MRAM) based on spin transfer torque (STT) and voltage-controlledmagnetoelectric (ME)write mechanisms.Wewill then discuss the use of STTmemory forembedded application, e.g., replacing volatile CMOS Static RAM (SRAM), followed by discussionof integration of CMOS recon¯gurable circuits with STT-RAM. We will then present the scalinglimits of the STT memory and discuss its critical performance parameters, particularly related toswitching energy. To further reduce the switching energy, we present the concept of electric ¯eldcontrol of magnetism, and discuss approaches to realize this new mechanism in realizinglow switching energy, allowing for implementation of nonvolatility at the logic gate level, andeventually at the transistor level with a magnetoelectric gate (MeGate). For nonvolatile logic(NVL), we present and discuss as an example an approach using interference of spin waves, whichwill have NVL operations remembering the state of computation. Finally, we will discussthe potential impact and implications of this new paradigm on low energy dissipation instant-onnonvolatile systems.

Keywords: Nonvolatile memory; nonvolatile logic; spin transfer torque; MRAM; STT-RAM;voltage control of magnetism; MeRAM; spin waves; scaling.

1. Introduction

The trend of the scaling of the CMOS feature sizehas followed Moore's Law for more than ¯ve dec-ades.1 This continuing CMOS scaling currently faces

a major challenge due to increasing energy dissipa-

tion per unit area, among others.2 The increase in

power dissipation results from the increase of static

leakage power as well as the continued increase of

SPINVol. 2, No. 2 (2012) 1250009 (22 pages)© World Scienti¯c Publishing CompanyDOI: 10.1142/S2010324712500099

1250009-1

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

density as the feature size is scaled down.3 Theformer is a consequence of the fact that the powerneeds to be continuously applied to CMOS circuitsin order for them to retain their information, that is,CMOS circuits are volatile in keeping their statesafter computation or performing logic operations.In addition, the dynamic switching energy per unitarea has also been increasing continuously due tothe increase of device density. This increase is aresult of the fact that dynamic power dissipationdensity per switching is a function of the number ofelectrons, since carriers in the device are indepen-dent.4 The quest for novel low dissipation devices,circuits and systems is thus one of the most criticalfor the future of semiconductor technology andnanosystems.

Today, at the system level, the information of asystem is stored in two manners: (i) temporally inStatic Random Access Memory (SRAM) usingCMOS circuits as embedded memory, and DynamicRandom Access Memory (DRAM) as a principalworking memory; and (ii) the system informationis permanently stored in the hard disk when thesystem is powered down. This memory structurewas made due to the lack of fast, energy-e±cient,cost e®ective, and high density nonvolatile memory(NVM). Spintronic devices, i.e., those utilizing thefundamental exchange interactions of electron spinsmay o®er very high speed (<1 ns) as illustrated inTable 1, which compares them with other memoriesin terms of their key parameters such as speed,energy, density, and endurance. Table 2 gives theprincipal interaction physics and their character-istics which di®erent memory devices are derivedfrom. Generally speaking, there are two types ofspintronic devices: one uses the manipulation ofsingle or a few spins (as in the case of quantum in-formation) and the other uses collective spins (as inthe case of nanomagnetics). For this paper, we will

focus on the latter, as single spin electronics requiresoperation at low temperature due to the fact thatthe Zeeman energy of single spin is on the order of0.058meV at 1 Tesla, much smaller than kT at roomtemperature and consequently the state cannot bemaintained for a su±cient time at room temperature.In addition, for CMOS, in which electrons are notcorrelated, the switching (dynamic) energy is de¯nedby the Maxwell, Landau, and Shannon limit and willbe still larger than NkTln2,4 where N is the numberof electrons for a switch. In contrast, the collectivespins of a magnet can be treated as a single elementwhen considering the switching energy, i.e., kTln2,indicating N times saving in the fundamental energylimit.17 Clearly, as the scaling continues, theswitching power dissipation per unit area will con-tinue to increase as the density increases. Further-more, we will only discuss material systems usingmetallic materials for magnetism, but will notaddress the topic using semiconductors, such as di-lute magnetic semiconductors.5,6 The reason of thischoice is that using metallic systems, the fabricationprocess may be easily integrated with CMOS sincethey can be implemented in the back end of lineprocessing (metallization).7

The modulation of magnetic moments withelectric voltage and current in magnetic nano-structures o®ers an exceptionally promising set ofcandidates for fast nonvolatile applications (seeTable 2). Examples of spintronic e®ects which havebeen utilized for memory are tunneling magnetore-sistance (TMR) and spin transfer torque (STT),7�17

which rely on the spin-dependent tunneling andangular momentum transfer between current andelectron spin in a nanomagnet. These principleshave been used, for example, in magnetoresistiverandom access memory (MRAM) based on STT(i.e., STT-RAM).14�30 This is in contrast withexisting memory devices such as volatile high speed

Table 1. Comparison of NVM technologies: Flash, Ferroelectric (FE), Phase-Change (PC),Resistive (R), Spin Transfer Torque (STT), and Magnetoelectric (Me) memories. MeRAMvalues are estimates/projections.

Flash FERAM PCRAM RRAM STT-RAM MeRAM

Write energy per bit > 1 nJ � 1 pJ � 100 pJ � 1 pJ < 100 fJ < 1 fJSpeed 1�s�1ms � 50 ns � 50 ns � 10 ns 1�10 ns 1�10 nsEndurance Low High Low Low Very High Very High

Density (F 2) 4�8 6�10 6�10 6�10 8�20 4�8

Maturity Product Product Product R&D R&D Research

K. L. Wang & P. K. Amiri

1250009-2

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

embedded memories (e.g., SRAM having the speedon the order of that of CMOS circuits). Others, suchas Flash and Resistive RAM are nonvolatile butslow and have low endurance due to their intrinsicmechanisms (Table 2). Magnetic memory simul-taneously o®ers all the needed features of highspeed, high density, high endurance and reliability,and nonvolatility as shown in Fig. 1. While STT iscurrently being addressed for standalone memoryapplications, the convenience of integration withCMOS makes the device and the technology idealfor embedded applications as well.

From Table 1, it is clear that STT-RAM hasmany orders of magnitude improvements in energyand speed compared to nonvolatile Flash. In

addition, compared with SRAM for embeddedapplications, STT-RAM o®ers comparable speedwith the added bene¯ts of high density and non-volatility, enabling a new class of instant-on nano-electronic systems beyond the conventional-scaledCMOS electronics (when integratedwithCPUon thesame chip). From another point of view, spintronicmemories such as STT-RAM in principle o®er lowervariability due to reduced quantum °uctuations,31

which have plagued and limited the scaling of thenumber of electrons in CMOS. Beyond memory, thisnew concept of instant-on nonvolatile electronics isof interest for logic applications as we argue as fol-lows. When the size is decreased, the leakage currentdue to tunneling (e.g., from the source to the drain

Table 2. Comparison of physical interaction mechanisms used in memory and logic technologies.

Interaction type Interaction rangeEnergy limit torealize switch Speed limit

Size limit of device atroom temperature

Applications andexamples

Coulombinteraction(electron/holetransport)

Long rangeinteraction, theenergy decaysas �1/r

E ¼ CV 2=2. Thepredicted energyconsumption is

0.01 fJ/bit.a;2

RC time constant andtransit time �order of ps or less,i.e., speed may beup to THz

range.b;70,98

Tunneling limitingthe size � 5 nm inthe transportdirection.c

Transit timedevice, e.g., CMOSdevices

Exchangeinteraction(spintronics)

Short range

interaction.d;99Ex ¼ JSiSj J is the

exchangeconstant.e;1,71,99

0.01�0.1 ps. Thecorrespondingfrequency would be

10�100THz. f;98

Ex � ET ¼ kBT ,giving a limit of afew nm.g

STT devices,spin wave devices,

and others.h

Magneticdipole�dipoleinteraction

Long rangeinteraction, theenergy decays

as �1=r3.99

Magnetic dipole ¯eld/

potential. i;99Order of magnetic

resonancefrequency,0.1� 100GHz.99

Ex � ET ¼ kBT ,giving a limit of afew nm.g

Nanomagneticdevices, magneticcellularautomata.77

Coulombinteraction (iontransport)

Long rangeinteraction

Resistive powerdissipation

RC time constant andtransit time �order of ns— up toGHz operation

�1 nm in transportdirection for highIon/Io®

ResistiveRAM.100,101

Notes:aV is the operating voltage domain and C is the capacitance. At nanoscale, it is the Coulomb blockade energy E ¼ e2=C, and it isdue to the quantization of charge in the single electron device.b For ballistic transport with cross-sectional dimensions in the range of quantum mechanical wavelength of electrons, the capaci-tance values and drain source spacing are typically small.c The limit can be also looked at from the energy point of view, given the Coulomb blockade energy, Ec > KT , yielding typically5 � 10 nm3 in volume.d For exchange interaction, Ex, the electron wavefunctions need to couple with each other of collective spin moments, Si, and thusthe interaction distance is at atomic scale.e The energy is needed to °ip the local collective spin moment at one site by exchange interaction.f The time needed for exchange interaction.g When the exchange energy is overcome by thermal energy, ferromagnetism is lost. The interaction will depend on the materials: forhard magnetic materials, the size will be smaller. The size is needed to maintain ferromagnetism and will depend on materials.h Nanomagnetic devices are preferred for room temperature operation. On the other hand, single spin manipulation uses exchangeinteraction for mostly low temperature.i The energy needed to °ip magnetic moment by external magnetic dipole, Ed ¼ ��0mimj=ð4�r3Þ, where mi and mj are twomagnetic moments.

Nonvolatile Spintronics: Perspectives on Instant-On Nonvolatile Nanoelectronic Systems

1250009-3

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

of the transistor) will continue to increase and thusit is anticipated this leakage current may impedefurther scaling. However, if devices/circuits canbe turned on and o® on demand and their statesare nonvolatile when they are o®, this leakage cur-rent may be reduced, and thus it will allow forscaling the feature size to go down to smaller values(e.g., 2 nm).

While bene¯ting from the inherent advantages ofa magnetic memory (high speed and nonvolatility),the scalability of STT-RAM in terms of size andenergy consumption will be ultimately limited dueto the fact that its underlying mechanism is current-driven control of magnetism. The use of the current-driven switching dictates a high current °ow in thememory array and the chip, limiting the energy-e±ciency of STT-RAM and causing it to be toopower-hungry for ultralow-energy high densitypower applications.15,16,21 To further realize the fullpotential of instant-on nonvolatile electronics, vol-tage control of high speed and high density non-volatile magnetic memory is being explored usingmagnetoelectric (ME) materials. This research aimsat realizing voltage control of magnetism as thesolution to enable the ultralow-power, ultrafastmemories of the future.

This paper is organized as follows. Section 2 o®ersan overview of STT-RAM technology, as it is themain current spintronic contender for instant-onnonvolatile electronics; thus we will also highlightsome of its recent advances. Section 3 illustrates

the potential system level advantages of integratingsuch a nonvolatile spintronic memory with CMOS,including memory replacement of SRAM, hybridCMOS-MTJ recon¯gurable circuits and other cir-cuit blocks. Section 4 will look at beyond-STTmagnetic memory solutions, in particular, addres-sing ultralow-power memory using voltage controlof magnetism. The reduction of switching energiesbrought about by the new advances on electric-¯eld-controlled magnetic switching will enable energyimprovements on magnetic devices not just formemory, but also for logic applications. Section 5will give an example of a nonvolatile logic (NVL)circuit design using such a principle associated withthe voltage control of spin wave propagation. A briefdiscussion of another approach using nanoscalemagnets will also be provided to contrast the spinwave approach. Finally, Sec. 6 provides a perspec-tive on the future development in these areas aswell as its impact on next generations of electronicsystems.

2. Magnetic Memory Using STT

2.1. STT-RAM background and devicearchitectures

MRAM and its variations, in particular spin transfertorque (STT-RAM) memory, have generated anexplosion of technological and research interest inrecent years. Because of its fundamental principlesas discussed earlier, STT o®ers low area, high speedand high endurance for electronic systems, as well asnonvolatility due to the collective behavior of thespins in the free layer, and is thus ideal for embeddedapplications. The typical simpli¯ed structure ofSTT-RAM is illustrated in Fig. 2; it consists of avery thin free magnetic layer, a pinned layer anda thin tunnel oxide layer, which is normallyMgO. Some of the details of typical structurescan be found in Refs. 15, 16 and 21. The magneti-zation directions and anisotropies of the free andpinned layers give rise to di®erent designs andperformance, as will be discussed later. STT-RAMis often regarded as a potentially universal memorytechnology due to its high speed, density, non-volatility, and very high endurance. It also o®ers theadditional advantage of being more scalable (unlikeOersted-¯eld-switched MRAM). It has recently beenshown that STT-RAM can also achieve fairly lowswitching energies of � 100 fJ (compared to, e.g.,

Fig. 1. STT-RAM on the memory landscape, o®ering bothnonvolatility and a better speed versus density tradeo® com-pared to existing technologies. Di®erent STT-RAM devicestructures (see Sec. 2) may be designed for various high speed(embedded) or high density (standalone) applications.

K. L. Wang & P. K. Amiri

1250009-4

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

Flash or ¯eld-switched MRAM), and thus is ofparticular interest in a number of embedded appli-cations such as in mobile communications andcomputation systems. (For comparison, it should benoted that CMOS switching energy is on the orderof 1 fJ (or 10�15 J) for the 32 nm node). For STT, thewrite process is performed by passing currentthrough a magnetic tunnel junction (MTJ) totransfer electron spins, inducing a torque to changethe magnetic polarization of the layer accordingto the direction of current. The di®erent states ofthe MTJ, i.e., parallel and anti-parallel directions ofthe free and the pinned layers, give rise to a currentmemory loop and can be read via TMR as shownin Fig. 2(b), which gives the quasi-static I�V relationas well as the pulsed R�V characteristics (Fig. 2(c)).

STT-RAM is a NVM candidate for replacingseveral existing memory technologies. It is a strongcontender to replace embedded high speed, rela-tively low energy but volatile SRAM, as it o®erscomparable or superior speed, unlimited endurance,and improved density, and more importantlywith additional features such as instant-on andnonvolatile characteristics (Fig. 1 and Table 1).Likewise, it also may be used in replacement ofstandalone as well as embedded DRAM, where STTo®ers not only superior speed, but also nonvolatilitywith comparable densities, as well as orders ofmagnitude improvements in write energy and speedcompared to nonvolatile Flash memory.

In this section, we will brie°y provide an overviewof STT-RAM technology. We will review the majorperformance metrics and their state of the art. Wewill highlight the important design tradeo®s andchallenges for the successful commercialization of

this technology, followed by a discussion on scaling tonext generations.

From the device structure, the available optim-ization schemes for improvement of each perform-ance metric (e.g., in the typically used CoFeB�MgOMTJ cells used for STT-RAM) can be generallydivided into three parts:

(I) Barrier engineering: MgO barrier thicknessa®ects resistance-area (RA) product, TMR,and endurance of the magnetic bit.

(II) Free layer engineering: This includes (ofteninter-related) parameters such as composition,saturation magnetization, shape, size, andanisotropy of the free layer. The combinationof these parameters a®ects the thermal stab-ility (i.e., retention time), switching currentdensity, and write energy of the magnetic bit.

(III) Polarizer (pinned layer) engineering: Polarizercomposition and con¯guration (e.g., in-planeversus perpendicular) a®ects the spin transfere±ciency, switching times, and switchingenergy.

In the following we will discuss each of the abovecomponents in meeting the challenges and willdescribe several pathways for improving STT-RAMperformance.

From a device structure point of view, one canenvision three di®erent ways to realize STT-RAMmemory cells. These are illustrated in Fig. 3. In thefully in-plane (I-STT-RAM) (top) (e.g., Refs. 11, 14,15 and 24), both the magnetization directions of thefree and ¯xed layers are parallel and lie in the sampleplane. An elliptical shape is usually used to provideshape anisotropy for the bit. Perpendicular

(a) (b) (c)

Fig. 2. STT-RAM cell switched by electric currents driven by an MOS transistor (a), and its quasi-static (b) and pulsed (c)switching characteristics (from Ref. 20). The MTJ on the left is shown in a stack at the metal contact of the drain of a MOS. TheMTJ stack also has a pinned layer on top of a very thin MgO tunneling oxide layer and a free layer in the bottom. The free layer maybe switched so that parallel as well as anti-parallel directions with respect to the pinned layer may be accomplished by the currentdirection.

Nonvolatile Spintronics: Perspectives on Instant-On Nonvolatile Nanoelectronic Systems

1250009-5

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

anisotropy (i.e., the magnetization direction pre-ferably being out of the plane) in these layers eitherdoes not exist or is not large enough to pull theirmagnetization direction out of the sample plane.This is the earliest and easiest to realize MTJstructure, and has been thus studied the most overthe past years. In the fully perpendicular (P-STT-RAM) case as shown in the middle of Fig. 3 (e.g.,Refs. 26 and 30), both the magnetization directionsof the free and ¯xed layers are parallel in the verticaldirection, i.e., in this case both layers have a largeenough perpendicular anisotropy which overcomestheir in-plane shape anisotropy, setting their mag-netization directions perpendicular to the sampleplane. The main advantage of the P-STT-RAMstructure (middle) compared to I-STT-RAM is bet-ter scalability and the potential to realize higherdensities. This is because the structure can be madein circular shape, in contrast with I-STT where anelliptical shape is used for maintaining the shapeanisotropy along the major axis of the ellipse formemory. Both structures, however, su®er from asmall spin torque during the initial incubation stageof magnetization switching, a consequence of theirparallel-magnetized equilibrium states, which limitstheir switching speed to � 1 ns. This problem isaddressed in the third combined (C-STT-RAM)structure (e.g., Refs. 19, 32 and 33) (bottom), whichcombines in-plane and out-of-plane polarizers withan in-plane free layer. The large torque due to theperpendicular polarizer in this case kicks the free

layer magnetization out of the sample plane,whereupon it precesses around the out-of-planedemagnetizing ¯eld. This form of resonant preces-sional switching allows for very fast write times onthe order of � 100 ps.19,32�37 The additional in-planepolarizer provides an additional torque and serves asa reference layer for readout. Thus, this high speedfeature is desirable for embedded instant-on non-volatile applications. The high endurance STT-RAMhas been recently studied and assessed to be amongthe best for embedded memory.38

2.2. STT-RAM performance metricsand optimization

The two fundamental performance metrics of STT-RAM at the MTJ cell level are its switching energyand thermal stability factor (particularly forstandalone memory). The stability factor is given by� ¼ MsHkV =2kT , where Ms is the saturationmagnetization of the free layer, V is its volume, Hk

is the magnetic anisotropy ¯eld, k is the Boltzmannconstant, and T is the temperature.15,22 The valueof � de¯nes the magnetic bit's stability againstfalse switching events due to thermal activation(i.e., retention time). For I-STT and C-STT devices,Hk is mainly determined by the in-plane shapeanisotropy (i.e., the energetic preference for themagnetization to align along a preferred direction asdetermined by the shape of the magnetic bit), whilein P-STT it is determined by the perpendicularanisotropy of the free layer. The write energy is theenergy required to bring about a current-inducedswitching event, i.e., to write a bit of magneticinformation. The write energy is closely related to—and needs to be optimized together with — theswitching current (which a®ects the transistor size),write voltage (which a®ects endurance), as well asthe thermal stability, as described below.

A key advantage for the introduction of the STTwrite mechanism in MRAM development has beento lower the switching current and energy requiredto write the magnetic state of the bit. Unlike tra-ditional (toggle) MRAM designs of magnetic ¯eldswitching with driving current, STT-RAM can bescaled down much better with shrinking devicedimensions (i.e., advancing technology nodes) andthus current. (Nevertheless, further reduction inswitching current of STT-RAM bits is needed asit limits the transistor size (hence density) of the

Fig. 3. Various con¯gurations of MTJ stacks. (Top) I-STTstructure with an in-plane magnetization using shape aniso-tropy, (Middle) P-STT with a perpendicular magnetiza-tion o®ering high density, and (Bottom) C-STT by combiningthe I-STT and P-STT structures, o®ering extremely highspeed.

K. L. Wang & P. K. Amiri

1250009-6

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

STT-RAM circuit at the present). For applicationsof instant-on nonvolatile electronics, speed andwrite energy are the two most important par-ameters. We discuss the switching energy next.

The write energy of an STT-RAM bit forswitching from the anti-parallel (high resistance,AP) state to the parallel (low resistance, P) state isgiven by15,21:

EAP!Pw ¼ V ðPsw; �Þ2�=RAP; ð1Þ

where V ðPsw; �Þ is the write voltage at the devicecorresponding to a switching probability of Psw, � isthe write pulse width, andRAP is the MTJ resistancein the anti-parallel state. The write energy forswitching from the parallel to anti-parallel statesEP!AP

w can be obtained similarly using the parallelstate resistance RP (instead of RAPÞ, and is ingeneral di®erent, due to di®erences in both switchingcurrent and resistance in the two cases.20,21 For arelatively long pulse width � , where the pulse issquare shaped, Eq. (1) is a simpli¯ed form of themoregeneral expression for write energy in the form ofR �

0ðV ðPsw; tÞ2=RÞdt. A useful ¯gure of merit for

comparing di®erent MTJ designs are the mean writeenergies EAP!P

w;m or EP!APw;m for Psw ¼ 0:5, although

one should note that for practical applications muchlower write error rates (WER ¼ 1� PswÞ arerequired. Combined with the need to ensure reliablememory operation while accounting for process andoperation temperature variations, this results inlarger practical write energy values, depending onarray size and design speci¯cations.

It can be seen from Eq. (1) that for energy-e±cientoperation, a critical condition is to maintain a lowmeanwrite voltage Vm¼V ðPsw¼0:5; �Þ¼Jc;mð�ÞAR, whereA is the MTJ area, R is the resistance in the P or APstate, and Jc;m is the (pulse-width-dependent) meanswitching current density. Themeanwrite energy canthus be rewritten as15,21:

Ew;m ¼ Vmð�Þ2�=R ¼ Jc;mð�Þ2A2R�; ð2Þwhere R is the resistance in P or AP state dependingon switching direction. The switching current densityincreases with reducing pulse width, and is welldescribed by Jc;m ¼ Jc0ð1þ �0=�Þ (in the short-pulseballistic limit) for elliptical magnetic bits smallenough to exhibit single-domain behavior.17 Theswitching current density Jc0 is given by17:

Jc0 � ð2e�Mst=}�ÞðHk þ ðHd �Hk?Þ=2Þ; ð3Þ

where � is the free layer damping factor, � is the spintransfer e±ciency, Ms and t are the free layer satur-ation magnetization and thickness,Hk is the in-planeshape-induced anisotropy ¯eld, Hd � 4�Ms � Hk isthe out-of-plane demagnetizing ¯eld, and Hk? is thefree layer perpendicular anisotropy.

It should be mentioned that, in addition to theSlonczewski STT,8 the so-called ¯eld-like torque39,40

can have a signi¯cant e®ect on switching dynamicsin MgO-based MTJs. An additional torque whichhas recently been increasingly studied inCoFeB�MgO-based MTJs is the interfacial voltage-induced anisotropy change.41,42 Both of these e®ectscan signi¯cantly modify the switching current den-sity of the device.

Based on the foregoing discussion, one canidentify the following strategies for minimizing writeenergy of MTJ cells:

2.2.1. Minimization of the MTJ resistance R

In order to minimize the MTJ resistance, thinnerMgO barriers in the MTJ cell must be used but are inpractice limited by the MgO barrier quality. Figure 4shows typical dependence of RA product and TMRon the MgO barrier thickness in CoFeB�MgOMTJs, measured on a single wafer with varying MgOthicknesses.20,21 For reliable array operation, oneneeds to choose theMgO thickness to be high enoughto ensure large TMR and small device-to-devicevariation. A second concern is the device breakdownvoltage and endurance for thinMgO(number ofwritecycles to failure). Figure 4(c) shows an endurancetesting result for a device with RA ¼ 3:5 ohm-�m2,with a mean write voltage of � 0.6V at 5 ns writetime, when extrapolated to an endurance of >1016

write cycles, although the latter may not be criticaldepending on application.

Figure 5 shows the dependence of write energyand switching current density on RA product in atypical in-plane CoFeB/MgO/CoFeB tunnel junc-tion. The write energy can be reduced by usingdevices with lower RA (i.e., thinner MgO barriers).However, note that the switching current densityincreases with reduced MgO thickness, possibly as aresult of higher e®ective damping [� in Eq. (3)] inthe free layer due to the reduced MgO quality forlow RA devices. This indicates that the write vol-tage does not scale in a linear fashion with reducedRA. For AP to P operation and vice versa, theseparameters will scale di®erently.

Nonvolatile Spintronics: Perspectives on Instant-On Nonvolatile Nanoelectronic Systems

1250009-7

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

2.2.2. Reduction of the switching currentdensity

While the write energy performance can beimproved by reducing both A and Jc0, one mayneed to account for the simultaneous e®ect of

these parameters on reasonable thermal stability,even though the stability issue may not be as criticalfor embedded applications. A useful ¯gure ofmerit for minimization purposes is the switchingcurrent divided by the thermal stability factor,given by:

Ic0=� � ð4e�kBT=}�Þð1þ ðHd �Hk?Þ=2HkÞ: ð4ÞFrom this equation and Eq. (3), it can be seen that,while reducing the device area A leads to a reductionof switching current, Ic0=� is una®ected by thischange. Increasing the thickness t of the magneticfree layer, on the other hand, will increase Hk andreduces Ic0=�. Scaling of in-plane-magnetized MTJsto smaller areas (and higher densities) thereforeneeds to be accompanied by increasing the free layerthickness, in order to allow for the desired stabilityfactor.

By the inspection of the last term of Eq. (4), apromising approach to improve the switching energy

(a)

(b)

(c)

Fig. 4. Dependence of MTJ resistance-area (RA) product (a)and TMR ratio (b) on the MgO barrier thickness in aCoFeB�MgO MTJ with RA ¼ 3:5�-�m2, and accelerateddielectric breakdown measurements for endurance testing (c) onsimilar devices, indicating an endurance of > 1016 write cyclesafter extrapolation to the operation voltage of � 0.6V (fromRef. 21).

Fig. 5. Write energy (a) and switching current density (b) forboth switching directions in CoFeB�MgO MTJs as a functionof RA product (from Ref. 20).

K. L. Wang & P. K. Amiri

1250009-8

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

is to increase signi¯cantly the perpendicular aniso-tropy in the free layer. This is because increasingHk? can reduce Jc by partially cancelling the e®ectof the out-of-plane demagnetizing ¯eld Hd.

24�28

A signi¯cant interface-induced perpendicularanisotropy in Fe-rich CoFeB ¯lms24,29,30,43 allowsfor switching current reduction by partial cancella-tion of the out-of-plane demagnetizing ¯eld inCoFeB�MgO MTJs. This approach is advan-tageous since the CoFeB�MgO material system hasbeen shown to demonstrate large TMR valuesrequired for circuit applications, and unlike otherapproaches, it does not necessitate the use of mul-tilayer structures for perpendicular anisotropy.Figure 6 shows the dependence of the switchingcurrent density on the free layer thickness (CoFeB)in MTJs, demonstrating e®ectively that as thethickness of the CoFeb layer is decreased, the per-pendicular anisotropy, Hk? increases. A typicalstructure consists of a Co40Fe40B20 (¯xed layer)/MgO/Co20Fe60B20 (free layer) MTJ with60� 170 nm in-plane dimensions. A comparison ofFe-rich MTJs to control devices with a Co-rich freelayer having a free layer thickness of 1.80 nm shows areduction of the average quasi-static switching cur-rent density by> 40% (from� 2.8 to� 1.6MA/cm2Þdue to the presence of the perpendicular anisotropy.Note that this improvement in the switching current(hence energy) versus thermal stability tradeo® isrealized despite an increase in the saturation magne-tization (from � 1000 to � 1300 emu/cc, not shown),which can only come from the increase of perpen-dicular anisotropy. The data shown in Fig. 6 areswitching current densities for a 10 ns write time.A clear reduction of the switching current densitycan be observed when the free layer thicknessis reduced, reaching � 4MA/cm2 for a free layerthickness of 1.69 nm. Note that this reduction ismuch more signi¯cant than one might expect fromthe reduction of the free layer volume alone, andhence it must come from the increased e®ect of theperpendicular interfacial anisotropy for thinner¯lms.

Finally, it should be noted that for a number ofapplications, in particular when STT-RAM is usedas an embedded memory, the requirements onretention time may be signi¯cantly relieved, allow-ing for smaller acceptable values of the thermalstability factor �. In such settings, smaller cell sizeand higher energy-e±ciency may be more importantconstraints, and one could thus envision STT-RAM

designs where the thermal stability is sacri¯ced toachieve a lower switching current density. Thiswould allow for the STT-RAM switching energies tobe further reduced by at least one order of magni-tude beyond what is possible for standalone or sto-rage applications, where nonvolatility is the majordesign criterion.

2.2.3. Perpendicular magnetic layers

For devices with a large enough perpendicular ani-sotropy where Hk? > Hd, the free layer can bemagnetized perpendicular to plane. For fully per-pendicular MTJs with perpendicular free and ¯xedlayers, the switching current density is given byJc0 � 2e�MsHkt=}�, where Hk is now the perpen-dicular anisotropy and the corresponding ¯gure ofmerit for switching current divided by thermalstability is15,30:

Ic0=� � 4e�kBT=}�: ð5ÞIt is immediately seen that this value can be sub-stantially smaller than that in the I-STT-RAMcase. Little has been reported on the dynamicproperties and short-pulse switching characteristicsof such P-STT-RAM structures, however. Onlyrecently,30,44 there have been reports both on highTMR > 100% and reasonable switching behavior insuch devices, demonstrating their promise for high-density-scaled P-STT-RAM beyond the limit ofI-STT-RAM technology. Interestingly, to date, themost promising material for these structures is

Fig. 6. Switching current density at 10 ns write time, as afunction of free layer thickness in a CoFeB�MgOMTJ with Fe-rich CoFeB free layer, exhibiting signi¯cant perpendicular ani-sotropy. Note that the switching current reduction is muchlarger than what would be expected from the reduction of thefree layer volume alone, and can thus be attributed to theincreased e®ect of the perpendicular interfacial anisotropy forthinner ¯lms, leading to a reduced write current for bothswitching directions (from Ref. 24).

Nonvolatile Spintronics: Perspectives on Instant-On Nonvolatile Nanoelectronic Systems

1250009-9

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

Fe-rich CoFeB similar to the ¯lms used for reducingswitching currents in I-STT-RAMdevicesmentionedabove.24

A C-STT-RAM structure, which only has onepolarizer orthogonal to the free layer, on the otherhand, can exhibit low write energy through adi®erent avenue, i.e., by realizing it with a muchfaster write time. Figure 7 shows switching resultson an MTJ with this type of combined orthogonalstructure, where the perpendicular polarizer iscomposed of a Co/Pd-based multilayer coupled to athin CoFeB ¯lm adjacent to the MgO barrier toenhance the current spin polarization from thispolarizer (b).19 One challenge in this structureresults from the use of two MgO barriers, which canincrease the RA product and hence result in anincrease of the write energy and write voltage. Sincethe perpendicular polarizer in this case does notcontribute to TMR and is only used for switching,

its associated MgO layer also reduces the overallTMR ratio of the device, by presenting an additionalparasitic resistance. These problems can be overcomeby replacing the MgO barrier at the perpendicularpolarizer with a metal (i.e., similar to a GMRstructure). The TMR has been shown to increase to� 100% in this manner.33

Due to the high speed, low energy consumption,and its nonvolatility, STT-RAM may provide aplatform for a new generation of instant-on recon-¯gurable electronics. The next section will giveexamples of the use of MTJs in conjunctionwith CMOS, and how they can be used to enhanceperformance on a system level. This will be followedby a discussion of pathways for the realizationof even more energy-e±cient magnetic memoriesbeyond-STT.

3. Nonvolatile Circuits with HybridCMOS and STT-RAM

As mentioned before, while memory is the mostimmediate application area of MTJs, nanomagneticdevices also o®er opportunities for integration oftheir inherent nonvolatility for application of circuitfunctions. Magnetic NVL o®ers the possibility ofsigni¯cantly reduced standby power consumption,for energy-e±cient systems and for realizing instant-on nonvolatile operations, e.g., enabling processorsto take up an un¯nished computational task after apower failure without the need to start over (boot-ing). Further from the system point of view, thevoltage applied to the devices may be turned o®when they are idle while a higher voltage can beapplied for high speed operation. Thus together,NVM and logic based on spintronic nanodevices cancreate a new class of nonvolatile electronics, whichmay o®er superior performance and new function-alities compared to today's CMOS technology.

We will discuss the potential integration of STTdevices for several levels of applications or di®erentgranularities from the circuit point of view: repla-cing SRAM, and complementing recon¯gurablecircuits (e.g., Field Programmable Gate Arrays orFPGAs), logic circuits, and eventually to the gateand transistor levels. This di®erence of the levels inintegration will depend on the energy and speed ofSTT memory cells, and hence as the progress onreducing switching energy is continued, the inte-gration may be moved down to the gate level forrealizing the instant-on nonvolatile electronics.

(a)

(b)

Fig. 7. (a) Schematic of the material stack, with an in-planeCoFeB free layer sandwiched between two in-plane and out-of-plane polarizers. (b) STT switching measurement results on anoncollinear (orthogonal) C-STT memory cell showing writetimes down to 140 ps (from Ref. 19).

K. L. Wang & P. K. Amiri

1250009-10

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

To date, the minimum switching energy achievedfor STT memory cells20,21,45�48 is on the order of� 100 fJ, which is about 2�3 orders of magnitudelarger than that of CMOS (i.e., �1�2 fJ for a 65-nmCMOS gate). Thus, as far as write energy is con-sidered, the MTJ-based nonvolatile logic circuitwhich requires frequent MTJ switching is hardlypower-e±cient. Signi¯cant scaling of each param-eter is needed to make the MTJ-based nonvolatilelogic circuits energetically competitive with CMOS.Such scaled devices would be potentially compellingfor integration with CMOS for a variety of appli-cations. Clearly, signi¯cantly scaled MTJ deviceswill be possible for low switching energy throughfurther advances in materials such as perpendicular¯lms. The ultimate size will be limited by the ani-sotropy of the material, de¯ning its stability. As thesize is reduced, harder magnetic materials may beused to prevent the layers from becoming super-paramagnetic so that stability of nanoscale bit cellcan be maintained. It is important to note, however,that even with the use of materials with highperpendicular anisotropy, the write current ofP-STT-RAM does not scale with device size as it isproportional to the thermal stability factor, henceimpeding its true scalability. Nonetheless, the energyaccording to Eq. (5) can be scaled to about 10 fJ (tobe discussed next) by relaxing the nonvolatilityrequirements with proper refresh and archivingmemory management in order to minimize theenergy of circuits and to achieve instant-on non-volatile systems. At present the CMOS-STT inte-gration approach may still be suitable for special orniche logic applications, where the CMOS logic gatesneed not be operated frequently.

To be thermally stable for nonvolatility on areasonable time scale (e.g., hours or days forembedded applications versus �10 years for storageapplications), a single magnetic bit may only requirea thermal stability factor � ¼ Eb=kT of, e.g., �20,corresponding to an energy barrier Eb of � 0.08 aJ.(As stated before, for archival applications, largerarrays will have more stringent requirements onthermal stability, i.e., a thermal stability of� 80�100 for fairly large arrays to ensure long-termnonvolatility.) For today's STT, it is noted thatthere is a vast gap between the < 1 aJ energy barrierof thermal switching (which is a measure of theminimum attainable write energy) and the practicalvalues of � 100 fJ for STT memory cells. Becauseof today's high switching energy (about 100X of

CMOS), the applications are limited to cachesreplacing volatile SRAM and integrating them withlarge circuits such as core and FPGAs. Generally,the fractional writing frequency of STT-RAM overCMOS logic operations (or number of CMOS in acircuit) should be limited to n¼EL/EM , whereEL and EM are the switching energies of CMOS andSTT, respectively. For the implementation of STTfor caches (in replacing CMOS SRAM), Smullen38

has discussed the energy improvements for threelevels of caches. Their simulations of severaldi®erent con¯gurations at the 32 nm node show thatthe energy and other performance parameters(delay, area, etc.) can be improved by a factor ofabout ¯ve by relaxing the nonvolatility [or � inEqs. (3) and (4)] and by using only a single MTJ cellas compared with CMOS SRAM (six transistors) asshown in Fig. 8.38

FPGAs and look-up-table-(LUT)-based recon¯-gurable logic are other examples of implementing theMTJ-based nonvolatile logic, since they require noswitching of storage cells during the logic operations.Recent work49,50 shows that CMOS/MTJ hybridLUT-based logic circuits that incorporate MTJs fornonvolatility (Fig. 9) are able to gain an overallperformance bene¯t, without paying a penalty inspeed or dynamic switching energy. A similar studyof hybrid CMOS-STT FPGA51 gives only a factor oftwo improvement. To achieve realistic nonvolatileelectronics, the integration will need to go down tosmall circuit or logic level and eventually the tran-sistor level, and the switching energy must be scaleddown further to be comparable to or better thanthat of CMOS. Alternatively, di®erent but more

Fig. 8. Energy-e±ciency of hybrid SRAM and STT-RAMcache hierarchies. The use of the hybrid architecture with arelaxed nonvolatility requirement reduces energy-delay productas well as increasing density (from Ref. 38).

Nonvolatile Spintronics: Perspectives on Instant-On Nonvolatile Nanoelectronic Systems

1250009-11

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

energy-e±cient mechanisms need to be explored.The latter will be discussed later in this paper.

There have been several proposals on imple-menting such a nonvolatile logic circuits throughCMOS-MTJ hybrid integration. Usually a senseampli¯er is used to read the total resistance di®er-ence between two groups of MTJ stacks at their lowor high resistance states and to restore the readoutvoltage to a proper value for subsequent logicoperations.52�54 Others implement CMOS/MTJhybrid logic gates that have MTJs as both memorycells and functional inputs to latch data, which isalso referred to as a logic-in-memory (LIM)architecture.55�57 However, most of these proposalsare conceptual with rare energy and performanceanalysis. A recent study that evaluates the energyperformance of the MTJ-based logic-in-memory

(LIM-MTJ) architecture (Fig. 10) in comparisonwith static and dynamic CMOS implementations,shows that LIM-MTJ has no tangible advantage inenergy performance over its equivalent CMOSdesign.49 This is due to the fact that write energies inSTT devices are still too high compared to CMOS.We will discuss potential use of beyond-STTsolutions to resolve this issue in the next section. Webelieve at present, on one hand it is necessary toimplement MTJs only into parts of large scale cir-cuits, while on the other hand a new generation oflow switching energy devices with e±ciency com-parable to that of CMOS is needed for the inte-gration to the logic gate level. Nevertheless, eventoday's STT-RAM devices can provide tangiblebene¯ts when considering that they reduce standbypower due to their nonvolatility.

(a) (b)

Fig. 9. Schematic diagrams of (a) CMOS-only and (b) hybrid CMOS-MTJ lookup table circuits. The nonvolatile MTJ-basedmemory in (b) can be gated and set to sleep mode, in order to save standby power. An overall improvement in energy-e±ciency canbe obtained in this manner by using the hybrid structure with NVM (¯gure from Ref. 50).

(a) (b)

Fig. 10. (a) Schematic of nonvolatile hybrid CMOS-MTJ logic and (b) a hybrid CMOS-MTJ dynamic current-mirror-logic 1-bit fulladder (from Ref. 49).

K. L. Wang & P. K. Amiri

1250009-12

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

4. Beyond-STT: ME Memoryfor High Energy-E±ciency

To dramatically improve the energy-e±ciency ofmagnetic memory andmake it suitable for integrationwith CMOS for nonvolatility at the gate level we needto further reduce the switching energy of nonvolatileelements. For this purpose, one may use an alternateapproach: voltage-induced switching of magnetiza-tion, as opposed to current-driven STT switching.a

Electric ¯eld control ofmagnetism (magnetic momentor anisotropy or both), similar to that of MOSstructure as illustrated in Fig. 11 can lead to a newparadigm, enabling ultralow-power nonvolatile mag-netic memory solutions (see performance metrics inTable 1).

Figure 11 illustrates several di®erent principles ofelectric ¯eld control of ferromagnetism: (1) thecontrol of surface ferromagnetism by changing theCurie temperature with a surface carrier e®ect58,59

[Fig. 11(b)], (2) the control of magnetic anisotropyby magnetostriction of a thin magnetic ¯lm with

strain60,61 [Fig. 11(c)], and (3) the change of surfaceanisotropy41,62 [Fig. 11(c)]. In the ¯rst approach, ithas been theoretically predicted that the control ofsurface carrier density of the Thomas�Fermi layercan lead to the surface modi¯cation of magnetictransition through carrier-mediated phase tran-sition, and a change of Tc by a few tens of degrees isanticipated.58,63 This theoretical prediction was ex-perimentally demonstrated in a thin Co ¯lm case, inwhich�Tc of 12K was shown with an electric ¯eld of�2 MV/cm.64 The second principle uses magneto-striction or the use of multiferroic materials. Thereare several approaches to the use of multiferroicsincluding single phase and synthetic multiferroicmaterials. One example is to use synthetic multi-ferroic heterostructures consisting of piezoelectricand ferromagnetic materials to realize voltage con-trol of magnetization as illustrated in Fig. 11(b).60

In this case, a voltage applied to the material stackgenerates a mechanical strain in the piezoelectricmaterial. Due to the magnetostrictive property of

Thin FMCarrier density at TF layer

Hi k Insulator

NM metal contact

(a)

M

T

T∆ C

(b)

NM metal contact

PMN-PT (0.5mm)

Thin FM (e.g., Ni)

M

(c)

dxydz2FM metal

Hi k Insulator

(d)

Fig. 11. Principles of electric ¯eld control of magnetism. (a) Control of surface magnetic phase transition via the Thomas�Fermilayer at the interface where extraordinary surface enhancement occurs. The result of Curie temperature shift is shown on the right(b). (c) Magnetostriction: Magnetic anisotropy as a®ected by the strain via piezoelectric material. (d) Interfacial magnetic anisotropycontrolled by an electric ¯eld. For example, shown are occupancies of the di®erent 3d orbitals at the interface as changed by anapplied electric ¯eld. In turn the spin�orbit interaction results in a reorientation of the magnetic moments.

aThe power dissipation due to the use of current does not necessarily imply high power. For current-driven switching, the powersupply usually needs to be of a high voltage due to the device resistance, resulting in high I

2

R loss.

Nonvolatile Spintronics: Perspectives on Instant-On Nonvolatile Nanoelectronic Systems

1250009-13

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

the adjacent magnetic ¯lm, this strain can lead to areorientation of magnetization as a result of the MEe®ect. The third principle is to use an electric ¯eld tocontrol the orbital occupancies of di®erent sym-metries of surface atoms, this in turn results in thechange of symmetry of the orbitals, and conse-quently, the magnetic surface anisotropy can bealtered through spin�orbit interaction.41,65�69 A fewmagnetic switching experiments have been demon-strated based on the above principles. For example inthe case of using magnetostriction, Figs. 12(a) and12(b) show experimental evidence of ME voltagecontrol of magnetization for a 30 nm magneto-strictive Ni ¯lm deposited on a piezoelectric PMN-PTsubstrate.60 Magneto-optical Kerr e®ect (MOKE)measurements are obtained to show that a 90� reor-ientation of the easy axis can be observed with ¯elds� 0.14MV/m (or 1.4kV/cm). This experimentdemonstrates voltage-controlled reorientation ofmagnetization, as well as nonvolatility — requiringno continuously applied voltage to keep the magne-tization in the reoriented state, thus demonstrat-ing an electric-¯eld-controlled nonvolatile magneticmemory operation. A critical requirement for thisscheme is that the magnetic ¯lm must have a largemagnetostriction coe±cient. The saturation magne-tization (Ms) of the magnetic ¯lm needs to be opti-mized based on a tradeo® between ME coupling andthermal stability. While a smallMs increases theMEcoupling and reduces the write voltage, a largeMs isdesirable for a reasonable retention time and thermal

stability for nonvolatility (similar to � ¼ MsHkV =2kT in the case of in-plane MRAM).

This type of memory takes advantage of thebuilt-in strain of the piezoelectric layer prior to themagnetic ¯lm deposition (i.e., through partial polingof the piezoelectric material and subsequent depo-sition of the magnetic ¯lm), thus allowing one torealize permanent and reversible reorientation of themagnetization between two perpendicular in-planedirections.60 This experiment provides a criticalproof of concept for a new Magneto-Electric Ran-dom Access Memory (MeRAM) based on thesetypes of synthetic multiferroic heterostructures. Thestate of such a memory bit can be readout, forexample, by fabricating the magnetostrictive layerinto a MTJ structure to allow for resistive TMRreadout.

Energy loss in such a MeRAM consists of theenergy capacitively stored in the memory cell, whichwill be probably dissipated into the ground via aresistive path similar to the CV 2 energy loss inCMOS switches, where C is the device capacitanceand V is the applied voltage. Likewise, additionalenergy loss may be associated with leakage currentthrough the device during switching. Another sourceof energy loss may come from the poling process, i.e.,hysteresis of the multiferroic (or ferroelectric) ma-terial; this energy loss may be reduced if devices aredesigned such as to minimize or eliminate the needfor poling to achieve magnetic switching. Giventhe nonvolatility of a circuit based on such an ME

(a) H jjX (b) H jjYFig. 12. Magnetization rotation and switching by electric ¯eld in 30 nm Ni ¯lms on a piezoelectric PMN-PT substrate. Permanentand reversible voltage-induced 90� switching of the magnetic easy axis is achieved in this system, as demonstrated by MOKEmeasurements for di®erent electric ¯elds (from Ref. 60). The magnetic moment is along the x-direction with no bias; it switches to they-direction when a bias of 0.14MVcm�1 is applied. (a) MV loop at di®erent biases with the magnetic ¯eld along the x-axis; (b) withthe magnetic ¯eld along the y-axis. Arrows indicate the order in which the electric ¯eld is applied in the experiment in order to switchthe magnetization.

K. L. Wang & P. K. Amiri

1250009-14

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

switch, which eliminates all standby power, as wellas the dramatic reduction in dynamic power due toelectric ¯eld control, ME devices may form the basisfor a new paradigm of inherently nonvolatile andhighly energy-e±cient magnetic logic. It will allowfor further size scaling of CMOS by toleratingsomewhat larger leakage as devices may be poweredo® from time to time. The read speed limit of suchdevice will be fundamentally similar to CMOS ifcurrent is used to read the state.

Another example of electric-¯eld-driven magneticswitching may use the interfacial magnetic aniso-tropy mentioned in the previous sections, particu-larly the recently discovered electric-¯eld-dependentanisotropy41,42,62,70 at the interface of oxides (e.g.,MgO) and magnetic ¯lms. Voltage-induced switch-ing of magnetization using this mechanism has beenrecently demonstrated71�73 as illustrated in Fig. 13,which also shows the basic structure (a). The deviceis similar to a conventional MTJ with a thickerdielectric layer. The magnetic anisotropy change canbe utilized to bring about switching of the free layer,

as illustrated by R�V curves shown in Fig. 13(b).A critical challenge of this approach is the use of amagnetic ¯eld in order to determine the switchingdirection in some cases or the use of precise timing fortoggle switching to the opposite magnetic direction.These requirements make the circuit designs morecomplicated and result in an additional overhead forread/write as well as for increasing the write energy.(However, other innovative approaches to eliminatethese requirements are in progress.)

Realization and scaling of MeRAM will allow forultralow-power nonvolatile electronics far beyondwhat is possible based on other NVM technologies(Table 1). The energy consumption of a MeRAMcell consists of a CV 2 term, where C is the cellcapacitance and V is the write voltage, as well as aV 2t=R term due to leakage through the device(which is material- and thickness-dependent andshould be minimized), in which R is the device re-sistance and t is the switching time. While MeRAMswitching energies can be lower by � 2�3 orders ofa magnitude, estimated using, e.g., the technologynode of 65 nm and the present material systems usedin STT-RAM,41,42,60,62,70 continuing scaling andmaterial developments will further reduce MeRAMenergies to the atto-Joules regime. Such low energyoperation is fundamentally beyond the reach ofSTT-RAM. While STT-RAM has been predicted toapproach write energies of a few 1 fJ (¼ 10�15 J) atthe 10 nm node,47 we project MeRAM to reach� 10 aJ (¼ 10�17 J) for similar dimensions. This willenable nonvolatility to be implemented at thetransistor level and may make possible high speed,low dissipation instant-on information processingsystems.

It should be noted that low write voltages are a keyrequirement for realizing the low energy dissipationfor MeRAM, and recent experiments have indicatedthat switching using such low voltages (<1V) isindeed possible using this approach.71�73 The readenergy may be equally important for applications.However, given that typical readout using TMRwould use only a fraction of the write voltage, the readenergy would be even smaller and hence will not limitthe overall energy consumption of the device.

The ultimate scaling limit (hence achievableenergy-e±ciency) for these kinds of magneticMeRAMs will be determined by the development ofmaterials with high perpendicular magnetic aniso-tropy, to ensure that the cells remain nonvolatilewith high enough thermal stabilities. As the volume

(a)

(b)

Fig. 13. MeRAM cell (a) exhibiting voltage-controlled mag-netic anisotropy (VCMA), where switching (b) of a magneticfree layer is achieved without the use of spin-polarized currents.Note that switching in both anti-parallel (AP, high resistance)to parallel (P, low resistance) and P to AP directions can beperformed with voltages of the same polarity, con¯rming thatthe switching is not induced by STT (see Refs. 71�73).

Nonvolatile Spintronics: Perspectives on Instant-On Nonvolatile Nanoelectronic Systems

1250009-15

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

of magnetic bits is reduced with scaling, themagnetic anisotropy of the free layer materialswill thus have to increase to maintain stability.Based on current projections47 with an additionalconsideration of shorter retention time for embed-ded application, we anticipate that MeRAM may bescaled down to a few nm; the development of hardermagnetic materials and other voltage-controlledmechanisms for MTJs could potentially make thescaling go even further.

Next, we will discuss a fully magnetic (ratherthan hybrid with CMOS) approach for NVL usingsuch ME e®ects.

5. Fully Magnetic NVL

To date a number of promising ideas have emergedfor spin-based logic.74�83 This section presents ap-proaches to all-magnetic design for NVL and cir-cuits. As pointed out before, there are two majorapproaches to spin-based logic devices: (i) Usingcollective spins for the development of magneticdevices and circuits,74,76,77,82,83 and (ii) the use ofspin in addition to charge for improving deviceperformance (e.g., Spin-Modulator or Spin-FETdevices such as that in Ref. 78). (From the materialspoint of view, there are two major di®erent classes ofmaterials used for spintronics: namely, dilute mag-netic semiconductor and metallic systems). Forcollective spin devices, magnetic logic devices maybe realized by exploiting physical mechanisms suchas dipole�dipole or exchange interactions for non-volatile logic circuitry (see Table 2). We will limitour discussion to mostly our spin wave bus (SWB)approach, but a brief discussion of nanomagneticlogic (NML) based on dipole-coupled magnetic cel-lular automata will also be included later in thissection.74,77 Both these approaches each haveadvantages and limitations in terms of their scal-ability, power dissipation, defect tolerance, andtheir compatibility with CMOS-based circuits. Inthe SWB approach, information is transferred viaexchange-coupled spins in a continuous magneticmedium (thin ¯lm), in contrast with the nanomag-netic dipole-coupled logic devices, in which eachelement is coupled via magnetic dipole interaction toneighboring elements as will be discussed later(Table 2). Figure 14 illustrates the SWB logicapproach and its basic operation principle. A spinwave is a collective excitation of spins due toexchange interaction, which can also be viewed as a

magnonic wave as shown in Fig. 14(a). SWB usesspin wave interference for various gate operations;the result of the operations can be readout by anonlinear switch (a ME gate, very much similar to aMeRAM cell) in the ¯nal stage as the results ofcomputation as illustrated in Fig. 14 and detailedin Fig. 16.83

Using SWB,84�87 we have previously proposedand developed the concept of magnonic logic cir-cuits, where an applied in-plane magnetic ¯eld isused to control the spin wave propagation frequencyand dispersion characteristics. The basic structureuses a magnetic ¯lm as a spin conduit of wavepropagation as SWB shown in Fig. 14, where theinformation can be coded into the phase of a pro-pagating spin wave and the logic functions are

(a)

(b)

(c)

Fig. 14. (a) A spin wave, viewed as a collective excitationof exchange-coupled spins in a ferromagnetic medium with anonzero wave vector. (b) Illustration of a device using two inputelements where spin waves are excited inductively using elec-trical currents passing below the SWB, and are detectedinductively by reading out a voltage at the output element. (c)Schematic of a logic circuit based on SWB and ME gates. TheME devices are used for input and output functions, interfacingwith spin waves propagating in the SWB.83

K. L. Wang & P. K. Amiri

1250009-16

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

performed using spin wave interference in the bus. Aprototype device is illustrated in Fig. 14(b), showingtwo microstrip lines (S1 and S2) acting as the spinwave input with a third microstrip (S3) used toreadout the signal. The amplitude and phase ofpropagating spin waves can be modulated by anapplied or an e®ective magnetic ¯eld, the latter ofwhich can be produced by a ME gate (MeGate) as inthe case of MeRAM devices. In this case, themodulation of magnetic ¯eld is done via electric ¯eldas discussed previously through the change ofmagnetic anisotropy. Spin wave generation anddetection at the input and output can also beachieved by ME gates for higher energy-e±ciency.This approach combines several advantages: (i) in-formation transmission is accomplished withoutelectron transport enabling one to minimize powerdissipation in the interconnects; (ii) ability to usewave superposition in the SWB to enhance func-tionality, while switching is done at readout; (iii) anumber of spin waves with di®erent frequencies canbe simultaneously transmitted among a number of

spin-based devices (i.e., frequency multi-plexing).75,83 There are other approaches, which arebased on spin wave Mach�Zehnder-type inter-ferometer proposed in recent years,88,89 where spinwave amplitude was used to de¯ne the logic state ofthe output. In contrast, in SWB, information iscoded into the phase of the spin wave signal. Twologic states 0 and 1 can be assigned to two phases ofthe spin waves having the same amplitude. In thisapproach, data processing is accomplished via thechange of the phase of the propagating spin waves(as illustrated in Figs. 14(a) and 16).

Using the latter approach, a prototype majoritygate has been demonstrated. Figure 15(a) (top)shows a photo of the test chip used in the exper-imental study of a prototype majority (MAJ) gate.Each of the ¯ve wires of Fig. 15(b) can be used as aninput or an output port for which microwavecoplanar structures are used, similar to the basicstructure shown in Fig. 14(b). In order to demon-strate a three-input one-output MAJ gate, three ofthe ¯ve wires were used as input ports, and two

(a)

Y

X

H

NiFeSilicon substrate

SiO2

Detector

Input1

ϕ=0 ϕ=0

Input2

ϕ=0

Input3

(b)

0.00 0.16 0.32 0.48 0.64 0.80-3

-2

-1

0

1

2

3 in-phase 2 in-phase, 1 out-of-phase1 in-phase, 2 out-of-phase

3 out-of-phase

Vol

tage

(m

V)

Time ( ns)

Spin-wave signal @ H = -95 Oe, f = 3 GHz

(c) (d)

Fig. 15. Prototype majority (MAJ) gate. The image of the prototype four-terminal spin wave device for MAJ logic demonstration isshown on top left (a) and the schematic of the central device on the top right (b). The experimental data illustrating device operationis given in the bottom left (c) with the logic table on the bottom right (d). The operation frequency is 3GHz.

Nonvolatile Spintronics: Perspectives on Instant-On Nonvolatile Nanoelectronic Systems

1250009-17

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

other wires were connected in a loop to detect theinductive voltage produced by the spin wave inter-ference, Fig. 15(b). The plot in Fig. 15(c) shows theoutput inductive voltage detected from di®erentcombinations of spin wave phases. An electric cur-rent passing through each wire generates an Oerstedmagnetic ¯eld, which, in turn, excites spin waves inthe ferromagnetic layer. The direction of the current°ow (the polarity of the applied voltage) de¯nes theinitial spin wave phase. The relative phases betweenthe waves excited by the wires may be 0 or �, for thesame or opposite direction of the current. Thedi®erent curves in Fig. 15(c) depict the inductivevoltage as a function of time for di®erent combi-nations of the spin wave phases (e.g., 000, 0�0, 0��,���) as illustrated in Fig. 15(d). The phase of theoutput inductive voltage corresponds to the ma-jority of phases of the interfering spin waves. Thedata are taken for 3GHz excitation frequency and atbias magnetic ¯eld of 95 Oe (perpendicular to thespin wave propagation). Note that this bias mag-netic ¯eld may be replaced with a MeGate. Allmeasurements are performed at room temperature.This simple demonstration of the concept used amagnetic ¯eld to control the phase of the propa-gating spin wave. The use of electric ¯eld control ofspin wave (i.e., ME gates) for the same purpose willsigni¯cantly reduce the dissipated energy by manyorders of magnitude as previously discussed forelectric-¯eld-controlled magnetic memory.

This prototype device demonstrates the feasi-bility of building wave-based MAJ logic gates,which are of great value for logic circuitry. Ingeneral, majority logic is more powerful for imple-menting a given digital function with a smallernumber of logic gates than CMOS.90 For example, afull adder may be constructed with three majoritygates and two inverters (3ME gates and 2 phasemodulators). In contrast, a Boolean-based im-plementation requires a larger circuit with seven oreight gate elements (about 25�30 transistors).91

The main reason majority logic has been out offashion for decades is that its CMOS realization isine±cient, while using spin waves will alleviate thisshortcoming.

NVL circuits can be constructed using SWBstructures and ME gates83 as illustrated inFig. 14(c). An illustration of the nonvolatile logicgate operation with electric ¯eld control of spinwaves is shown in Fig. 16. In the illustration, weshow the use of ME gates with the SWB, where spin

wave excitation and storage of the ¯nal compu-tational result (output) are done via ME gates. Theonly nonmagnetic input required for the circuit is aclock applied to the ME gates for triggering theswitching at the output end and the spin wavegeneration at the input bit. The direction ofswitching is determined by the spin wave phase atthe output cell.83 The voltage pulses are convertedinto spin waves (magnons), then, the data trans-mission and processing within the SWB is accom-plished via spin waves only. Nonvolatility isaccomplished through the ME gate like the memorydevices discussed before: (i) output data from eachcomputational step is stored in a ME memory cell,which can be switched by the spin wave under theMeGate, assisted by a pulsed bias voltage. The biasis used to reduce the energy barrier for facilitatingthe switching by the spin wave (resulting in a vol-tage-assisted spin-wave-induced switching process).The direction of switching is determined by the spinwave phase; (ii) a ME cell generates a spin wave forthe next computational step with the next clockcycle and the spin wave phase is determined by itsmemory state through exchange and/or dipolecoupling to the SWB. Logic functionality is achievedas a sequence of the ME switching events, whereeach ME gate changes its state (°ips magnetization)according to the magnetization of the preceding cellsvia propagating and interfering spin waves asassisted by the MeGate bias.

Energy-e±cient electric-¯eld-induced generationof spin waves is a key requirement for this NVLscheme to work. For ME gates, we have recentlysuccessfully demonstrated this e®ect using a multi-ferroic heterostructure, showing spin waves gener-ation by voltage in a capacitive ME gate andpropagating over distances of up to 40micrometers.92

Once switched, the ME gate preserves magnetizationtill the next computation step. The latter makes itpossible to eliminate the need for static power con-sumption and at the same time drastically reducesthe active power. The minimum energy of the spinwave switching is limited by the thermal noise onlyand can be very close to kT, with the majorityof the energy required for switching being providedby the clock (voltage) signal. Additional examplesof di®erent nonvolatile magnonic logic circuits basedon this concept are given in Ref. 83. These SWB logicdevices may also be further integrated with CMOSto make nonvolatile hybrid CMOS/magnetic logiccircuits.

K. L. Wang & P. K. Amiri

1250009-18

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

A di®erent approach to realizing spin-based NVLis the use of magnetic quantum dot cellular auto-mata (MQCA), also referred to as nanomagnet logic(NML).74,77,93�95 The NML approach relies on thetransfer of information via consecutive switchingevents in rows and columns of dipole-couplednanomagnets. Initial demonstrations used bothferromagnetic74 and anti-ferromagnetic77 dipolecoupling of adjacent nanomagnets to bring aboutthe consecutive switching events. Both isotropic,circular,74 and elliptical nanomagnets exhibitingshape anisotropy96 have been used for this purpose,and logic gates based on the NML approach weredemonstrated.77 The NML approach is similar inconcept to the earlier idea of using electrostaticallycoupled arrays of quantum dots in an electrostatic

quantum dot cellular automata (EQCA) struc-ture.97 EQCA, however, is not easily realizable atroom temperature,77 while MQCA does not su®erfrom this problem as the nanomagnetic dots can bedesigned to exhibit stable magnetization at roomtemperature due to the use of collective spins. Aninteresting feature of the NML approach is its in-herent nonvolatility, provided that the magneticbits are su±ciently stable to retain their infor-mation beyond the time scales used in the com-putation. Given that individual dots are onlycoupled via dipole interaction, however, scaling ofthe NML approach entails the use of materialswith a high anisotropy (as previously discussed formemory) in order to ensure stability. Moreover,due to the need for a full switching of each bit, the

(a) (b)

(c) (d)

Fig. 16. Schematic of input (a, b) and output (c, d) cell operation in the all-spintronic spin-wave-based NVL scheme. Inputvoltage pulses excite spin wave signals, which propagate through the SWB. The phase of the generated spin wave is determinedby the state of the input memory cell via dipole or exchange interaction. The ME gates excite and store spin wave information. Atthe output end, the ME gate is switched by the arriving spin wave, with the switching direction being determined by the spinwave phase. A bias voltage is applied by the clock to reduce the energy barrier to allow for the spin wave to switch the state of theME cell.

Nonvolatile Spintronics: Perspectives on Instant-On Nonvolatile Nanoelectronic Systems

1250009-19

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

speed of logic circuits based on this concept isdetermined by the speed of magnetic-¯eld-inducedswitching (� nanoseconds) of the nanomagnets inan array.

The SWB and NML approaches o®er di®erentvariability and scalability behaviors. While in theNML approach a minimum uniformity among di®er-ent cells has to be maintained in order to allow forcircuit operation, this issue is to some extent resolvedin the SWB approach due to the use of a continuousmedium. The SWB approach, on the other hand, maysu®er from challenges due to the nonuniformities ofpropagation speed and delay due to issues such asedge roughness variation, di®erent propagationangles, and di®erent propagation lengths in di®erentparts of the circuit. It should be noted as the size andthe separation gap of nanomagnets are furtherreduced, the exchange coupling strength will increase,and spin waves will propagate through. Then MQCAor NML eventually approaches the SWB.

6. Summary

Collective spin devices, or metallic magnetic deviceshave advantages of high speed, nonvolatility andbeing able to operate at room temperature. Sincedevices/circuits may be turned on and o® ondemand, thus it may allow CMOS to further scale tosmaller feature sizes without much static leakage.Likewise, the dynamic switching energy may bereduced as well, while retaining minimal variability.In addition, these metallic devices can be con-veniently processed and integrated with today'sCMOS technology. We discussed the state of the arttechnology for spin transfer torque memory (STT-RAM). Although the switching energy of STT is onthe order of 100 fJ (or about 100� higher than thatof today's CMOS), the integration of the nonvolatileSTT-RAM memory has been already shown to leadto advantages in terms of energy-e±ciency anddensity when integrated with CMOS at the block/circuits level. In particular, embedded applicationswhere STT-RAM replaces traditional SRAMon-chip memories are an example of this. The inte-gration may further advance to the gate and even-tually to the transistor level as the energy-e±ciencyof the magnetic memory elements is improved. Thiswill be possible, for example, through the develop-ment of voltage-controlled ferromagnetism anddevices. We discussed several principles of electric¯eld control of magnetism. The topic will be much

pursued in the future for realizing MeRAM and MEgates, with dramatically higher energy-e±ciencyand scalability than those of STT-RAM. The workwill continue to focus on reducing the write energy,improving the speed and making it more convenientto integrate with CMOS transistors. With MeRAM,it should be possible to make low levels of circuits/systems nonvolatile and eventually to integrate it atthe gate level. For the latter, it will be important tomake the reading signal from the MeGate as close tothat of CMOS (Vdd) as possible. Eventually, withthe enhanced energy-e±ciency of nonvolatile spin-tronic devices, all-magnetic logic schemes such asSWB and NML, where CMOS is replaced and/orcomplementedwith entirely spin-based logic circuits,will also become viable. Thus, these nonvolatilespintronic devices may transform electronic systemsto result in a new era of instant-on nonvolatilenanoelectronics.

References

1. G. E. Moore, Electron. Mag. 38 (1965).2. International technology roadmap for semi-

conductors (2011).3. T. N. Theis and P. M. Solomon, Proc. IEEE 98,

2005 (2010).4. S. Salahuddin and S. Datta, Appl. Phys. Lett. 90,

093503 (2007).5. F. X. Xiu et al., Nanotechnology 21, 375606 (2010).6. K. L. Wang and F. X. Xiu, Thin Solid Films 518,

S104 (2010).7. C. J. Lin et al., 45 nm low power CMOS logic com-

patible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell,Electron DevicesMeeting(IEDM), Baltimore, MD, 7�9 December 2009,IEEE International (2009), p. 1.

8. J. C. Slonczewski, J. Magn. Magn. Mater. 159, L1(1996).

9. L. Berger, Phys. Rev. B 54, 9353 (1996).10. E. B. Myers et al., Science 285, 867 (1999).11. J. A. Katine et al., Phys. Rev. Lett. 84, 3149 (2000).12. S. S. P. Parkin et al., Nat. Mater. 3, 862 (2004).13. S. Assefa et al., J. Appl. Phys. 102, 063901 (2007).14. Y. M. Huai et al., Appl. Phys. Lett. 84, 3118 (2004).15. E. Chen et al., IEEE Trans. Magn. 46, 1873 (2010).16. K. Lee and S. H. Kang, IEEE Trans. Magn. 47, 131

(2011).17. J. Z. Sun, Phys. Rev. B 62, 570 (2000).18. L. Q. Liu et al., Appl. Phys. Lett. 94, 122508 (2009).19. G. E. Rowlands et al., Appl. Phys. Lett. 98, 102509

(2011).20. Z.M. Zeng et al.,Appl. Phys. Lett. 98, 072512 (2011).

K. L. Wang & P. K. Amiri

1250009-20

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

21. P. K. Amiri et al., IEEE Electron. Dev. Lett. 32, 57(2011).

22. P. Upadhyaya et al., J. Appl. Phys. 109, 07C708(2011).

23. H. Zhao et al., J. Appl. Phys. 109, 07C720 (2011).24. P. K. Amiri et al., Appl. Phys. Lett. 98, 112507

(2011).25. T. Moriyama et al., Appl. Phys. Lett. 97, 072513

(2010).26. H. Meng and J. P. Wang, Appl. Phys. Lett. 88,

172506 (2006).27. S. Mangin et al., Appl. Phys. Lett. 94, 012502

(2009).28. S. Mangin et al., Nat. Mater. 5, 210 (2006).29. S. Yakata et al., J. Appl. Phys. 105, 07D131 (2009).30. S. Ikeda et al., Nat. Mater. 9, 721 (2010).31. I. V. Ovchinnikov and K. L. Wang, Appl. Phys.

Lett. 92, 093503 (2008).32. A. D. Kent et al., Appl. Phys. Lett. 84, 3897 (2004).33. H. Liu et al., Appl. Phys. Lett. 97, 242510 (2010).34. D. E. Nikonov et al., J. Appl. Phys. 107, 113910

(2010).35. O. J. Lee et al., Appl. Phys. Lett. 99, 102507 (2011).36. C. Papusoi et al.,Appl. Phys. Lett. 95, 072506 (2009).37. A. Vaysset et al., Appl. Phys. Lett. 98, 242511

(2011).38. V. M. Clinton, W. Smullen, A. Nigam, S. Gur-

umurthi, M. R. Stan, Relaxing non-volatility forfast and energy-e±cient STT-RAM caches, 2011IEEE 17th Int. Symp. High Performance ComputerArchitecture, San Antonio, Texas, 12�16 February2011.

39. I. Theodonis et al., Phys. Rev. Lett. 97, 237205(2006).

40. J. C. Sankey et al., Nat. Phys. 4, 67 (2008).41. T. Maruyama et al., Nat. Nanotechnol. 4, 158

(2009).42. M. Endo et al., Appl. Phys. Lett. 96, 212503 (2010).43. A. Manchon et al., J. Appl. Phys. 104, 043914

(2008).44. D. C. Worledge et al., Appl. Phys. Lett. 98, 022501

(2011).45. J. M. Slaughter, Recent advances in MRAM tech-

nology, Device Res. Conf., 2007 65th Annual,South Bend, Indiana, 18�20 June 2007, p. 245.

46. W. H. Butler et al., Phys. Rev. B 63, 054416 (2001).47. A. Driskill-Smith et al., Latest advances and road-

map for in-plane and perpendicular STT-RAM,Memory Workshop (IMW), 2011 3rd IEEE Inter-national, Monterey, CA, 22�25 May 2011, p. 1.

48. Y. Huai, AAPPS Bull. 18, 33 (2008).49. F. B. Ren and D. Markovic, IEEE Trans. Electron.

Dev. 57, 1023 (2010).50. F. B. Ren, Energy-performance characterization of

CMOS/magnetic tunnel junction (MTJ) hybrid

logic circuits, M.Sc thesis, University of California,Los Angeles (2011).

51. S. Paul et al., Nanotechnol. IEEE Trans. 10, 385(2011).

52. H. Meng et al., IEEE Electron. Dev. Lett. 26, 360(2005).

53. S. Y. Lee et al., IEEE Trans. Electron. Dev. 55, 890(2008).

54. S. R. Patil et al., Design of a spintronic arithmeticand logic unit using magnetic tunnel junctions,Presented at the Proc. 5th Conf. ComputingFrontiers, Ischia, Italy (2008).

55. S. Ikeda et al., IEEE Trans. Electron. Dev. 54, 991(2007).

56. S. Matsunaga et al., Appl. Phys. Exp. 1, 091301(2008).

57. S. Matsunaga et al., Appl. Phys. Exp. 2, 023004(2009).

58. I. V. Ovchinnikov and K. L. Wang, Phys. Rev. B80, 012405 (2009).

59. D. Chiba et al., Nat. Mater. 10, 853 (2011).60. T. Wu et al., Appl. Phys. Lett. 98, 262504 (2011).61. G. Srinivasan et al., Phys. Rev. B 64, 214408

(2001).62. T. Nozaki et al.,Appl. Phys. Lett. 96, 022506 (2010).63. I. V. Ovchinnikov and K. L. Wang, Phys. Rev. B

78, 012405 (2008).64. D. Chiba et al., Nat. Mater. 10, 853 (2011).65. J. Alzate et al., MMM Conf., EG-11 (2011).66. J. Zhu et al., Phys. Rev. Lett. 108, 197203 (2012).67. C.-G. Duan et al., Phys. Rev. Lett. 101, 137201

(2008).68. M. Endo et al., Appl. Phys. Lett. 96, 212503 (2010).69. T. Nozaki et al., Appl. Phys. Lett. 96, 022506

(2010).70. Y. Shiota et al., Appl. Phys. Exp. 2, 063001 (2009).71. Y. Shiota et al., Nat. Mater. 11, 39 (2012).72. W.-G. Wang et al., Nat. Mater. 11, 64 (2012).73. J. G. Alzate et al., Voltage-induced switching of

CoFeB-MgO magnetic tunnel junctions, 56th Conf.Magnetism and Magnetic Materials, Scottsdale,Arizona (2011), p. EG-11.

74. R. P. Cowburn and M. E. Welland, Science 287,1466 (2000).

75. A. Khitun et al., J. Phys. D, Appl. Phys. 43, 264005(2010).

76. B. Behin-Aein et al., Nat. Nanotechnol. 5, 266(2010).

77. A. Imre et al., Science 311, 205 (2006).78. S. Datta and B. Das, Appl. Phys. Lett. 56, 665

(1990).79. G. A. Prinz, Science 282, 1660 (1998).80. S. A. Wolf et al., Science 294, 1488 (2001).81. D. E. Nikonov and G. I. Bouriano®, IEEE Trans.

Nanotechnol. 4, 206 (2005).

Nonvolatile Spintronics: Perspectives on Instant-On Nonvolatile Nanoelectronic Systems

1250009-21

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.

82. D. A. Allwood et al., Science 309, 1688 (2005).83. A. Khitun and K. L. Wang, J. Appl. Phys. 110,

034306 (2011).84. A. Khitun and K. Wang, Superlatt. Microstruct.

38, 184 (2005).85. A. Khitun et al., IEEE Trans. Magn. 44, 2141

(2008).86. Y. Wu et al., J. Nanoelectron. Optoelectron. 4, 394

(2009).87. A. Khitun et al., Superlatt. Microstruct. 47, 464

(2010).88. M. P. Kostylev et al., Appl. Phys. Lett. 87, 153501

(2005).89. T. Schneider et al., Appl. Phys. Lett. 92, 022505

(2008).90. A. R. Meo, IEEE Trans. Electron. Comput. EC-

15, 606 (1966).91. T. Oya et al., IEEE Trans. Nanotechnol. 2, 15

(2003).

92. S. Cherepov et al., Electric-¯eld-induced spin wavegeneration using multiferroic magnetoelectric cells,56th Conf. Magnetism and Magnetic Materials,Scottsdale, Arizona (2011), p. DB-03.

93. G. H. Bernstein et al., Microelectron. J. 36, 619(2005).

94. A. Orlov et al., J. Nanoelectron. Optoelectron. 3,55 (2008).

95. G. Csaba et al., IEEE Trans. Nanotechnol. 1, 209(2002).

96. A. Imre et al., Superlatt.Microstruct. 34, 513 (2003).97. I. Amlani et al., Science 284, 289 (1999).98. P. J. Burke, Solid-State Electron. 48, 1981 (2004).99. J. Stohr and H. C. Siegmann, Magnetism: From

Fundamentals to Nanoscale Dynamics (Springer,New York, 2006).

100. H. Akinaga and H. Shima, Proc. IEEE 98, 2237(2010).

101. R. Waser et al., Adv. Mater. 21, 2632 (2009).

K. L. Wang & P. K. Amiri

1250009-22

SPIN

201

2.02

. Dow

nloa

ded

from

ww

w.w

orld

scie

ntif

ic.c

omby

"U

NIV

OF

CA

LIF

OR

NIA

,LO

S A

NG

EL

ES"

on

03/2

8/13

. For

per

sona

l use

onl

y.