nonlinear equalization processor ic for wideband receivers

Nonlinear Equalization Processor qIC for Wideband Receivers and

SensorsSensorsWilliam S. Song, Joshua I. Kramer, James R. Mann,

Karen M. Gettings, Gil M. Raz, Joel I. Goodman, a e Gett gs, G a , Joe Good a ,Benjamin A. Miller, Matthew Herman, Thomas B.

Emberley, Larry L. Retherford, Albert H. Horst

HPEC 2009HPEC 2009

23 September 2009RESEARCH & TECHNOLOGY, INC.

This work was sponsored by DARPA under Air Force Contract FA8721-05-C-0002. Opinions, interpretations, conclusions

HPEC 2009-1WSS 9/23/2009

MIT Lincoln Laboratory

This work was sponsored by DARPA under Air Force Contract FA8721 05 C 0002. Opinions, interpretations, conclusions and recommendations are those of the authors and are not necessarily endorsed by the United States Government.

Outline

• Introduction– Nonlinear Equalization (NLEQ) applications– Nonlinear Equalization (NLEQ) applications– NLEQ program objective

• NLEQ processor architecture• VLSI NLEQ processors• VLSI NLEQ processors• Performance demonstration results• Summary

MIT Lincoln LaboratoryHPEC 2009-2

WSS 9/23/2009

High Dynamic Range Requirements for Military and Commercial Sensor Systems

Radar Receiver System Example Radar Receiver System

JammingRadar

Radar Receiver System Example Radar Receiver SystemInterference + Noise

Environment

B)

Clutter

Jammer

Dynamic Range

Target

Pow

er (d

B

Noise

g80->100 dB

Range

Small targets at or below noise level

• Radar, ELINT, SIGINT, Comm receiver systems must support high dynamic range operation

– To detect small targets/signals in interference/clutter environment


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To detect small targets/signals in interference/clutter environment– High signal-to-noise ratio and linearity required

Linearity Concerns in Highly Digitized Arrays and Frequency Channelized Systems

• Digital beamforming and frequency channelization increase in-band signal-to-noise ratio (SNR)Receiver ADCReceiver ADCReceiver ADC

Digital Sensor Array

• Non-linearity generated spurs and intermods can interfere with small signal detection

ece e CReceiver ADCReceiver ADCReceiver ADCReceiver ADCReceiver ADCReceiver ADC

Noise

Two-toneinput

Inter-

Pow

er Two-toneinput

Inter-mods

Pow

er Two-toneinput

Inter-mods

Pow

er

mods

Frequency

Noiseods

Frequency

Signal

Noiseods

Frequency

Receiver ADC FrequencyChannelizer Po

wer

Out-of-Band Noise

In-Band Noise


WSS 9/23/2009

Frequency FNyquist

NoiseFrequency Channelized Receiver

Nonlinear Equalization (NLEQ)

Rec A/DFrom Antennas

1

N

Digital ReceiverDigital Receiver

DigitalSignal

LNAAntennas

Sources of Nonlinearities

gProcessor


WSS 9/23/2009


Rec A/D

1

N


DigitalSignal

LNA


gProcessor

In-Band Intermodulation Distortions

Before Equalization

r (dB

)Po

wer

Frequency (bin)


WSS 9/23/2009



1

N


DigitalSignal

Processor

NonlinearEqualizer Digital

SignalLNA

Antennas


Processor

Inverts Nonlinearities

SignalProcessor


Before Equalization

r (dB

)

After Equalization

(dB

)

Pow

er

Pow

er (

Dynamic range improvement

Frequency (bin) Frequency (bin)


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1

N


DigitalSignal

DigitalSignal

Processor

NonlinearEqualizer Digital

Signal

+20~25 dB SFDR/IFDR

LNAAntennas


gProcessor Processor

Inverts Nonlinearities

SignalProcessor @500MHz BW

>1 Teraops< 2 Watts


Before Equalization

r (dB

)

After Equalization

(dB

)

Pow

er

Pow

er (

Dynamic range improvement

Frequency (bin) Frequency (bin)

• Nonlinear equalizer processor can reduce nonlinear distortion levels in analog and mixed signal circuitry


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g g y• Equivalent to having devices 10-20 years ahead of their time

Outline

• Introduction• NLEQ processor architecture• NLEQ processor architecture

– Processor architecture– Architecture optimization

• VLSI NLEQ processors• VLSI NLEQ processors• Performance demonstration results• Summary


WSS 9/23/2009

NLEQ Polynomial Nonlinear Filter Architecture

Z-α Pass-through Σ

Pass-through

Processing Elements

Z β XFIR

• Parameters to optimize:– Number of processing

elements

Z-β XFIRZ-β XFIR

Z-β

Z-γ1

XFIR ΣZ-β

Z-γ1

XFIR elements– Polynomial orders of

processing elements– Number of taps

Z-γ1Z-γ1

Z

Z γ1

Z-γΝZ-γΝ

– Delay values

Z-γΝZ-γΝ

MIT Lincoln LaboratoryHPEC 2009-10WSS 9/23/2009

Wideband NLEQ Processor Parameter Optimization

Z-α Pass-through

Z-β XFIR

Z-γΝ

Z-γ1

Z-γΝ

• Parameter selection


– 10 filters, 10 taps, 0-3 tap delay, 0-3 group delay, 3 pass through delay

Parallel NLEQ Processor Architecture Optimization

P P P P e

Distributed Polyphase Block-Floating-Point Residue Arithmetic Architecture

Low VT Dynamic Logic IC Layout

P P P P

P P P P

P P P P

Dis

trib

ute

Rea

ssem

ble

Design Feedback(Performance Trades)

Design Feedback(Performance Trades)

Sub-processor Task Distribution & Sizing

FIR1φ1

IC Architecture and Floor Plan

FIR1φN NLP1φ1 NLP1φN

P P P P P P P P P P P P

P P P P P P P P P P P PFIR1φ1 FIR1φ2 FIR1φ3 I/OClocksDesign

FIR1φ2 FIR2φN NLP2φ1 NLP2φN

FIRmφ1 FIRmφN NLPmφ1 NLPmφN





NLP1φ1 NLP1φ2 NLP1φ3

FIR2φ1 FIR2φ2 FIR2φ3Feedback

(Routing Efficiency)

Buses


Memory ControlEfficiency)

Measured Results: PRN Signal with Amplifier & ADC Distortions

TypicalUnequalized Equalized

In-band i d

Typical Response

intermods Harmonics

wer

(dB

FS)

wer

(dB

FS)

Pow

Pow

• Non-tonal signal experiment parameters– Amplifier in saturation region

M 104 i l d d i t tb d t– Max 104 included in testbed system– Pseudo-Random Noise (band-limited) input waveform

• Greater than 25 dB dynamic range improvement– In-band signal component is not distorted by the equalizer


In band signal component is not distorted by the equalizer

MIT Lincoln Laboratory

NLEQ Adaptive Equalization Performance

Adaptive Equalization PerformanceFully Adaptive

Partially Adaptive

Non-Adaptive-14

-12dB

Adaptive Equalization Performance

-18

-16

uctio

n in

em

ent (

dB)

-22

-20

ur R

edud

uFD

R Im

prov

e

Minimal performancelosses uses computationallyffi i t d ti

0 10 20 30 40 50-26

-24SpuIF efficient adaptive

algorithmNominal training temperature

Ambient Temperature in Degrees Celcius• Characterized Max 108 device sensitivity to changes in temperature• Applied adaptive equalizations

Fully temperature adaptive approach achieve good performance

Ambient Temperature (oC)


– Fully temperature adaptive approach achieve good performance– Partially adaptive approach can achieve similar performance with much

higher computational efficiency

Outline

• Introduction• NLEQ processor architecture• NLEQ processor architecture• VLSI NLEQ processors

– Enabling technologiesNLEQ4000 ultra wideband processor IC– NLEQ4000 ultra-wideband processor IC

– NLEQ500 wideband processor IC• Performance demonstration results• Summary• Summary


Nonlinear Equalizer Processor IC Development Process

Non-Linear EqualizerAlgorithm/Architecture

EQ FIRPartition FIR #1

×

H1

H2 +Partition FIR #2Distributed Polyphase IC ArchitecturePartition FIR #N

HJ

X(n) Y(n)

P P P P

P P P P

P P P P

P P P PDis

trib

utio

n

Rea

ssem

ble

ypResidue Arithmetic

FIR1φ1 FIR1φNNLP1φ1NLP1φNFIR1φ2 FIR2φNNLP2φ1NLP2φN

FIRmφ1 FIRmφNNLPmφ1NLPmφN

I/OClocks

Buses

NLEQ Signal Processor ICP P P PD R Memory Control

● 1.5 Tearops● 1.2 Watts

8

161

2 2

4

816

Optimal RegionDegree of Polyphasing

Throughput DensityPower Efficiency

Architecture Optimization

500 MH BW MAX108

Low Vt Dynamic Logic

124

8

4816

1

2

Level of Pipeline

EfficiencyThroughput Density Times Power Efficiency

500 MHz BW MAX108

Pow

er (d

B) Before NLEQ

After NLEQ


Frequency Bin

Architectural Comparison of Pentium 4 and MIT LL Processor Dies

Pentium 4 Die MIT LL Processor Die

ProcessorArray

• Single processor• Multiple caches and memory bus

• 1000’s of parallel processors• Local memory only• Multiple caches and memory bus

• Only core runs at high speed• General purpose processing• Large design team (>100)

• Local memory only• Entire die runs at high speed• Signal processing functions• Small design team (<10)


g g ( ) g ( )

Custom CMOS Circuit Design

Standard Cell Full Adder Full Custom Full Adder

• Custom logic and devices sizing• Manual device placement and

interconnect• Small area and power

consumption

• Pre-designed logic gates only• Automatic device placement and

routing• Large area and power

consumption


consumptionconsumption

Full Custom Low Threshold Voltage (VT) Dynamic Logic Circuits

Standard Cell Static Register Full CustomDynamic Register

Low VT Devices

Charge

Low VT Devices

P = ½CV2f

Leakage

● Frequent refresh● Bypass capacitors

Design Techniques

● Bypass capacitors● Signal isolation● Guard rings● Robust circuits

• Logic based computation and storage

• Many devices

• Charge based computation and storage

• Fewer devices


• Large area and power consumption • Small area and power consumption

NLEQ4000 Processor IC

• Up to 4,000MSPS• Selectable bit widths

– Up to 12 bits input

Wideband NLEQ Processor IC LayoutAnd BGA Package Up to 12 bits input

– Up to 16 bits output• LVDS and CMOS I/O• Programmable coefficients

And BGA Package

g• Block floating point residue

arithmetic

Parameter(IBM 0.13um)

Core Chip

Die Size 2.6 mm x 3.3 mm

6mm x 6mm

Power @1500MSPS

266mW 453mW

Power @4000MSPS

706mW 1219mW


NLEQ500 Processor

• Up to 500MSPS• Selectable bit widths

– Up to 18 bits input

IBM 0.13µm Die

– Up to 18 bits input– Up to 22 bits output

• Low voltage CMOS I/O• Programmable configuration and coefficientsg g• Block floating point residue arithmetic• Yield 14/15 for LowVt and 14/15 for RegVt

Parameter Core I/O ChipParameter(IBM CMOS 0.13um)

Core I/O Chip

Size 0.65mm x 1.4mm

N/A 2.2mm x 2.2mm

P @100MSPS 6 W 19 W* 25 W*

BGA

Power @100MSPS(Vdd=0.6V)

6mW 19mW* 25mW*

Power @500MSPS(Vdd=1.2V)

122mW 121mW* 243mW*


*With 50 Ohm Load Termination

Outline

• Introduction• NLEQ processor architecture• NLEQ processor architecture• VLSI NLEQ processors• Performance demonstration results

S• Summary


MAX108 Demonstration ResultsWithout NLEQ4000Without NLEQ4000

MAX108 ADC with NLEQ4000

NLEQ4000

With NLEQ4000

NLEQ4000MAX108

• ~21 dB linearity

Q

improvement demonstrated with NLEQ4000 IC at 1.5GSPS


Measured NLEQ Performance Improvement for Other ADCs

Interleaving Architecture~1 GHzImproved ~17 dB

Folding Architecture1.5 GHzImproved ~13 dB

National 81000 Atmel AT84AS008 Flash ArchitectureFlash Architecture~1.3 GHzImproved ~12 dB Entire Receiver Chain

30 MHz BWImproved ~12 dB


Maxim 109 LTC 2209

X-Band Receiver-on-Chip (RoC) Development Based on NLEQ DSP

BPF BPFLO

ADC NLEQ

Top View

MAX108

ADC NLEQRoC

Bottom View

LNA IF Amp

ADC

Bottom View

Mixer Integrated RoC Die360mW

• Linear dynamic range limited by the final IF amplifierNLEQ

360mW

Linear dynamic range limited by the final IF amplifier– NLEQ DSP to linearize the amplifier and ADC

• High performance and low power achieved with new analog/digital co-design paradigm


• Single die receiver implementation being explored

Summary

• Linearity enhancement required by DoD/commercial sensor/receiver applications

– Phased array sensors/receivers– Frequency channelized sensors/receivers

• MIT LL has developed high-throughput low-power nonlinear equalization signal processor ICs

– Massively parallel systolic architecturey p y– Polyphase distributed arithmetic processing– Block floating point residue number arithmetic– Full custom low-threshold-voltage dynamic logic

• Successful demonstration results• Successful demonstration results– >20 dB linearity improvement– NLEQ4000

Up to 4GSPS, <1.25WUp to 12 bit ADCsUp to 12 bit ADCs

– NLEQ500Up to 500MSPS, <0.25WUp to 18bit ADCs


nonlinear equalization processor ic for wideband receivers

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