noise margin criteria for digital logic

8/13/2019 Noise margin criteria for digital logic

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IEEl TRANSACTIONS ON EDUCATION, VOL 36

Noise Margin, NO. 4 , NOVEMBER 1993

Criteria for Digital Logic CircuitsJohn R. Hauser , Fellow, IEEE

,Lbstract-The concept of noise margin is very important intht design and application of digital logic circuits. Most engineersreiilize that is it in some way related to the transfer characteristicsof inverter circuits and most textbooks have some discussion ofnoise margin as related to different logic families. However, mosttextbook descriptions of noise margin are very incomplete and inm;i ny cases both contradictory and misleading. This discussionreyiews the noise margin issue, discusses many different criteriawti ich have been used to characterize logic gates and discussestht- standard treatments of noise margin in typical textbooks.Finally, a noise margin criteria is proposed as a replacement forthv standard textbook approaches.I. INTRODUCTION

HE first detailed publications dealing with noise margin

T nd its relationship to logic gate transfer characteristicsappear to be those of Hill in 1967 and 1968 [l] [ 2 ] . Hisdiicussion is very good and should be read by anyone inter-e.ted in noise margin and noise immun ity problems. Abou t1 [ 1years after Hills work, a series of papers appeared [3]-[6]dt scribing different approaches to dealing with noise marginatd proposing many methods of defining a noise margincriteria. This work was somewhat unified in 198 3 by Lohstroh[ ; ] who showed that most of the newly proposed noise margincriteria were all equivalent. More will be said about thise; rly work later, but it appears to be mainly ignored byci intemporary textbook authors in favor of more questionableaiid less complete discussions of noise margin concepts.The concept of noise margin for a logic family is simple,blit there are very subtle implications and restrictions. If oneh i s a logic gate, an invertor for example, which satisfied thert lationships

a idVIH > VIL (3)

t ien one can define high and low state noise margins by thec efinitions

N M H = VOH VIHN M L = VIL- VOL.

4)5 )

7ltese relationships can be graphically illustrated as in Fig. 1.imy invertor transfer characteristic H ( V )which falls within

Manuscript received July 1991.The author is with the Electrical and Computer Engineering Department,IEEE Log Number 9211752.IJorth Carolina State University, Raleigh, NC 27695.

363

Input Voltage (V)

Fig. I Illustration of logic levels 1~ I L 1 ~ >H and 1b~ along wit11one possible inverter transfer characteristic.

the unshaded area, such as the solid curve, will have noist:margins at least as good as given by (4) and 5). For positivi:noise margins, the ordering of the voltages will be as given inthe f igure, is . , VOL output low) < VIL input low) < VI,[(input high) < VOH output high). It is thus relatively easy todetermine if a logic family satisfies a given set of logic leveand noise margin relationships by seeing if all the transfercharacteristics fall within the required voltage ranges whichwould be the unshaded area in Fig. 1. If one wants definitionsand noise margins which are valid for some temperature rangeor statistical variation in transfer characteristics, then allcharacteristics must fall within the required unshaded area ofFig. 1. To accommodate a range of characteristic curves, thelogic levels must typically be shifted at the expense of thestated noise margins.The inverse of the problems shown in Fig. 1 is lessstraightforward. This is the problem of given a logic family ora transfer characteristic, what is the set of optimum logic11levels and the corresponding optimum or worst-case noisemargins? This is a problem addressed, to som e extent, by mostmodern textbooks on digital electronics. It is an importantquestion and concept since not all logic families have thesame noise margins, and the relative magnitudes of the noisiemargins are important in many applications.

At this point the use of the terms optimum and .worst-case i reundefined and therefore somewhat unclear.0162-8828/93 03,00 993 IEEE


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I0 V,L VI

Input VoltageD

f i g . 2. Typical inverter characteristic with -1 slope points identified asVJL nd V ~ H .

At this point it is important to review and understand thetandard textbook approach to the intrinsic logic levels andI oise margins of a logic family with an invertor characteristicsuch as shown in Fig. 2.The -1 slope points are typicallytaken as defining points for VIL nd V I H . his leaves VOH nd10~ to be defined and at this point textbook authors seem totie divided into two camps: a) those who take VOH nd VOLobe also given by the -1 slope points and b) those who take the:table logic states of an infinite chain of inverters or a bistableinvertor pair as defining V ~ Hnd VOL. hese two choices areillustrated in Fig. 3. The dotted curve in Fig. 3(b) representshe transfer characteristic with output and input axes reversed,md the intersection of the two curves represents the two stablettates of a pair of cross-coupled inverters. Also as pointed outinany years ago [1]-[3], these are also the stable states of annfinitely long string of inverters. A survey of about a dozenq ligital electronics textbooks showed them all using one or the)ther of these definitions to define logic levels and intrinsicioise margins [8]-[20]. The two definitions of VOH nd VOL)bviously give very different answers with regard to intrinsicioise margin properties.The definition of Fig. 3(b) appears to be more frequentlyised in present day textbooks in spite of the fact that the -1slope definition of Fig. 3(a) has some theoretical justificationwhile there appears to be little or no theoretical justificationor using the stab le logic states of F ig. 3(b) to define VOHand VOL. he definitions of Fig. 3(b) immediately run intotrouble with the very basic and simple concepts discussed in2onnection with Fig. 1. The transfer characteristic does notlie within the required shaded area of Fig. 1 and thus cannotrepresent a set of valid logic level definitions from which anymeaningful noise margins can be calculated. Th us the approachof Fig. 3(b) must be rejected as a valid noise margin approachin spite of the fact that it is used by several highly respecteddigital electronics textbooks. Problems with this approach werepointed out by Hill as early as 1967 [l]

lEEE TRANSACTIONS ON EDUCATION, VOL. 36, NO. 4, NOVEMBER 1953

0 V,L vwInput Voltage.

(a)

Input VoItage(b)

Fig. 3 . Typical choices for defining I ~ Hnd b ~sed in most logiccircuit textbooks. (a) -1 slope definition. (b) Bistable inverter pair lo gic statedefinition.

The -1 slope definitions of Fig. 3(a) pass the simple testof Fig. 1 and thus are possible logic levels and noise margindefinitions. In fact there is some theoretical justification Ibrthe -1 slope criteria for defining all four logic levels. If onemaximizes the sum of the two noise margins, i.e., NMH +N M L , then one finds that a maximum sum requires the -1slope definitions [7]. This appears to place this criteria ona sound theoretical justification. However, there are problemswith even simple logic circuits such as MOS inverters with thisdefinition. Since it maximizes the sum and not the individualterms, nothing p revents the m aximum sum from occurrj ngat points where one of the noise margins is zero or e\.ennegative In fact, a negative noise margin can be re1ativ:lyeasily obtained from otherwise perfectly valid MOS invertor


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IEEE rRANSACTlONS ON EDUCATION, VOL. 36, NO. 4, NOVEMBER 1993 365

I I

I 1

Slope = 1V, = 4.0VV, = 0.W-v, = 1.ovV,, = 2.5VNMH = 1.5VNM, = OSV-V = 2.5VV,, = 0.5VV = 2 . 9V = 2.5V -NM, = 0.OVNM, = 2.0V

0 1 2 3 4Fii 4. Illustration of a transfer curve withou t a unique -1 slope point.

cha +acteristicS.This is probably the reason many authors haveabandoned the definition of Fig. 3(a) in favor of that of Fig.3(h ). In the remainder of this paper the criteria of Fig. 3(a) willbe .eferred to as the nega tive slope criteria (NSC) and thatof IGg. 3(b)as the modified negative slope criteria (MNSC).One of the problems with the negative slope criteria isillustrated in Fig. 4. f the region of the transfer curve betweenA md B has slope -1, the -1 slope point is not uniquelydef ned and in fact will jump from point A to point B as theslolie goes through the -1 value. Shown in the figure are thetwo sets of noise margin values obtained from either pointA )r point B. Since it is unrealistic for the noise margins toabiuptly jump from one set of values to the other as the slopebetween A and B goes through -1, one would suspect thatneither set of values is a reasonable set of noise margin valuesfor the given transfer curve.h c e neither of the previous definitions used in modernelectronic textbooks provide an acceptable theoretical or prac-tic: 11 definition of logical levels or of intrinsic noise margins,on :must look for other criteria for establishing these levels.

11. BASICDEFINITIONSF LOGICLEVELS ND NOISEMARGINSrhe basic concept of noise margin is usually related to thenoise voltage at the gate of a long string of inverters whichis required to cause an upset in the logic levels after a verylai ge num ber of inverter stages. T he best-case noise m arginhas been defined as the noise required at a single gate in suchan infinite string to cause logic level upset [7]. Although thiscan be defined and easily evaluated it is of little practicalin portance since one is rarely interested in such an ideal case.

A second level of interest is that in which all low gates in alogic string have noise sources present or all high gates havenc vise sources. These cases can be referred to as single-sidednoise margins, i.e., S S N M H and SSNML.The worst-case noise condition occurs when noise sourcesais present at all inputs in a string of gates with all the lowg; e and high gate noise sources contributing in such a way

c oadsF-3fActive InvertersInput Voltage, A,,, Aovr

b)Fig. 5 . Illustration of transfer function shifts with high and low statenoise sources. (a) Cross-coupled inverter pair. (b) Inverter input-outputcharacteristics.

as to cause a maximum tendency to upset the logic levels[ l] 2 ] , 7] This is the condition under which one is normallyinterested in the m agnitudes of the noise m argins. Such infinitestrings of logic gates are equivalent, noise wise, to two cross-coupled inverters form ing a bistable flip-flop and such a simplecircuit can thus be used to establish worst case noise margins.If a flip-flop is not upset by two noise sources in series withthe high and low states, then finite strings of inverters will notbe upset. The remainder of this work will concentrate on suchworst-case noise margins.The operation of a cross-coupled inverter pair can ediscussed with reference to Fig. 5. Since A,,, becomes A,,and Ab,, becomes A I N , he solid curves A and A representthe two inverter transfer characteristics with points X and Erepresenting the two stable logic states. These values will br:referenced in subsequent figures as VLH nd,VLL.

A noise voltage associated with Aout or A,, will shift thesolid curve A vertically before it becomes the input ,for the Ainverter. Similarly a noise voltage associated with Aout or A I ~ J


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IEEE TRANSACTIONS ON EDUCATION, VOL. 36, NO. 4 NOVEMBER 199366

Von WkNMnI I T -I I I

VI, VIlnput Voltage

Fig. 6. Valid noise margins for a give n inverter character istic, using an areaembedded within the transfer curve loop.

will shift the solid curve A horizontally before it becomes aninput back to the A inverter. The dotted curves represent apair of transfer characteristics shifted due to a high state noiseN H and a low state noise N L .The corresponding stable statesmove to points X and Y . The inverter retains its high andlow states as long as the dotted curves continue to intersectin three points.This leads to an easy-to-interpret graphical approach to avalid set of noise margins for a given inverter characteristic.This is illustrated in Fig. 6where a cross-hatched rectanglehas been drawn inside the loop of the inverter characteristic,with one corner of the rectangle touching each solid curve.Any rectangle which can be drawn inside the characteristicloop represents a set of noise voltages (and correspondingVIL . I H , OL, OH) hich are at the limit of inverter sta-bility. When the rectangle becomes a square, one has theworse case equal noise margins (i.e., N M H = N M L ) .Whenthe rectangle becomes a vertical N M L = 0) or horizontal( N M H = 0) line, one has the worst case single-sided noisemargins.The existence and shape of the open loops in the transfercharacteristics determine the noise margin properties. Thefitting of a rectangular area within the loop allows one to definea whole range of valid noise margins but not a single set ofunique values. This is, however, the nature of noise margins.For a given inverter characteristic, one can, for example, tradea lower low state noise margin for an improved high statenoise margin.One must place additional restrictions on the noise marginsto obtain a unique set of noise margins. There are severalways in which this can be done. One can insist on equalnoise margins ( N M H= N M L ) n which case one m aximizesthe area of a square inside the inverter characteristic loop.If one maximizes the area of the rectangle, than one hasmaximized the product of the two noise margins (i.e. madeN M H N M L a maximum). These two criterions will bereferred to as the maximum equal criteria (MEC) and themaximum product criteria (MPC). For transfer curves whichare nearly symmetrical such as Fig. 5(b), these two criteriagive very close results.

TABLE ICALCULATEDOISEMARGINSV)

Several simple transfer curves, as seen in Fig. 7, can beused to illustrate noise margins with the previously discussedcriteria. The loops between the transfer curves range fmmhighly symmetrical to highly nonsymmetrical. Table I givesthe calculated noise margins according to the five differencecriteria previously discussed. F or a symm etrical transfer cu wesuch as Fig. 7(a), reasonable noise margin values are obtainedfor almost all the criteria. An exception is the MNSC whichpredicts too large a noise margin. This is typical of the MNS Ctechnique for all circuits. All techniques give essentially thesame result for the nonsymmetrical transfer curve of Fig.7(b). By all criteria except the MEC, the low noise margin isconsiderable larger than the high noise margin 2.60V versus1.00V). By insisting on equal noise margins, one is restrictedto a value of 1.00 V for both values.Only the ME C and MP C techniques give well defined valuesfor both transfer curves of Fig. 7(c) and (d). The transfer curveof Fig. 7(c) has no uniquely -1 slope point on the high outputrange and was discussed in connection with Fig. 3. Only thetechniques based upon the area (MEC and MPC) within thetransfer function loop give reliable values of noise margin.Fig. 7(d) has only one -1 slope point on the transfer curveand techniques requiring the location of the -1 slope valuesobviously fail for this case. It could be argued that the tramfercurve is somewhat contrived and doesn't correspond to myreal logic family. While this is true, a valid technique forevaluating noise margins should work for any transfer curvewhich has valid highflow logic states when used in a cross-coupled inverter configuration. Normally the negative s h p ecriteria and the maximum sum criteria give identical results.However in the case of Fig. 7(d) one can define the resultsfor the maximum sum criteria even though one cannot ob)aintwo - slope points. However, the maximum sum criteria sitillpredicts poor values since it predicts a zero value for one ofthe noise margins.From the previous discussion, it can be seen that only tech-niques based up on em bedding some area within the tran iferfunction loop gives reliable noise margin values for a widerange of possible transfer functions. The normal techniquesappearing in most modem electronic textbooks do not givereliable calculations of noise margins for a broad range oftransfer characteristics and frequently fail for simple NtOScircuits. The area technique goes back to basic definitions ofnoise margin shifts in the transfer functions and gives the only


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EEI: 'RANSACTIONS ON EDUCATION, VOL. 36, NO. 4 NOVEMBER 1993 367

4 4-- -2 3 35 . 2 d

g>6 . 2>

.

1

0 0

Input Voltage (Volts) Input Voltage Volts)(a)

4 4

Y-5 a 3g

39

: : 22 2 21

0 0

Input Voltage Volts) Input 4 oltage Volts)(c)

Fig 7. Illustration of noise m argin criteria for several transfer curv es. (a) Highly sym metr ic transfer curve. (b) Transfer curve with unequal hig h and OWlevel noise margins. (c) Transfer curve with ambiguous -1 slope point. (d) Transfer curve with only one -1 slope point.

re1 ,able method fo r evaluating noise m argins. T his result isno new but was discussed in many of the early papers onno se margin.[n comparing the maximum equal criteria and the maxim umpn )duct criteria, it appears un duly restrictive to insist o n anecl la1 high and low noise margin. A transfer characteristicsiriilar to that of Fig. 7(b) has a low noise margin whichis obviously considerably larger than the high noise margin.Tt is easily results from maximizing the area of a rectanglew thin the transfer function loop. Thus the preferred methodfo - evaluating noise margins must be to muximize the urea of

vectangle within the transfer function loop (or the maximump i qduct criteria).Part of the reason for the use of the -1 slope criteria in Input Voltage Volts)' tbooks is probably the fact that these points can be math- Fig, 8. Illustration of noise margin definitions for a family of transfer curve3.er iatically calculated for many logic families. The maximumai ea technique is easily understood from a graphical approach,bi it is not easily calculated for most real transfer functions.However, an easily calculated value, which is wrong, does not,ji.stify the continued use of this technique in present day orf l ture textbooks.The maximum product criteria is easily extended in conceptt': account for temperature variations in transfer curves or for

effects of parameter variation s in transfer curve characteristics.Consider, for example Fig. 8 where the shaded area is usedto include a family of transfer function characteristics dui:to parameter variations and/or temperature variations. Th:maximum area between the worst case curves still graphicall-ydefines a valid set of worst-case noise margins.


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1 i s IEEE TRANSACTIONS ON EDUCATION, VOL. 36. NO. 4 NOVEMBER 1993

111. SUMMARYTechniques for evaluating the noise margin for families oftigital logic circuits have been discussed and evaluated. Itt as been shown that the technique of evaluating the -1 slope

points on the inverter transfer function as used in most m oderntzxtbooks is not a valid and reliable approach to evaluatingf d s e margin values. It is argued that the most reliable andreasonable criteria is to maximize the product of the twoiloise margins. This is equivalent to maximizing the area of: rectangle embedded within the loop formed by the transferc.urves of an inverter pair.

Most of the material presented here is not new but can befound in the early literature on noise margin. However, becauseof the widespread use of the -1 slope criteria in modern1extbooks it appears that a re-look at basic approaches tonoise margins are in order. It is hoped that this discussion willdmulate further thought in this area and that future electronicTextbook authors will abandon the present approach in favor1)f a more realistic and valid treatment of the concept of noisenargin and how it relates to the transfer characteristic of logicircuits.

REFERENCESC. F. Hill, Definitions of noise margin in logic systems, Mullard Tech.Commun, no. 89 , pp. 239-245, Sept . 1967.-- Noise margin and noise immunity in logic circuits, Microelec-tron., vol. 1, pp. 16-21, Apr. 1968.J. Lohstroh, Static and dynam ic noise margins of logic circuits, IEEEJ . Solid-state Circuits, vol. SC-14, pp. 591-598< June 1979._ Calculation method to obtain worst-case static noise margins oflogic circuits, Electron. Lett, vol. 16, pp. 273-274, Apr. 1980.- The punch-through device as a passive exponential load in faststatic bipolar RAM cells, IEEE J Solid-State Circuits, vol. SC-14, pp.840-844, Oct. 1979.E. Seevinck, Deriving stability criteria for non-linear circuits withapplication to worst-case noise margin of IL, Electron. Lett., vol.16, pp. 867-869, Nov. 1980.1. Lohstroh, E. Seevinck, and J. DeGroot, Worst-case static noisemargin criteria for logic circuits and their mathematical equivalence,IEEE J . Solid-state Circuits, vol. SC-18, pp. 803-806, Dec. 1983.

[8] V. H. Grinich and H. G. Jackson, Introduction to Intqrated Circuits.New York: McGraw-Hill, 1975, pp. 111-113.(91 D. A. Hodges and H. G. Jackson, Analysis and Design of DigLalIntegrated Circuits.[lo] R. A. Colclaser, D. A. Neamen and C. F. Hawkins, Elcctronic CircaritAnalysis.[111 A. S. Sedra and K. C. Smith, Microelectronic Circuirs. Ne w Yo1 k:Holt, Rinehart and Winston, 1982, pp. 669473.[12) M. S. Ghausi, Electronic Devic es and Circuits: Discrete and 1ntegratc.d.New York: Holt, Rinehart and Winston, 1985, pp. 608-610.113) R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design T echn ipesfor Analog and Digital Circuits. New York: McGraw-Hill, 1990, pp.602-607.[14] J. P. Uyemura, Fundamentals o MOS Digital Integrated Circuits.Reading, MA: Addison-Wesley, 1988, pp. 83-86.[151 M. N. Horenstein, Microelectronic Circuits and D wic es. EnglewoodCliffs, NJ, Prentice-Hall, 1990, pp. 721-724.1161 C. A. Holt, Electronic Circuits. New York: Wiley, 1978, pp. 16C-102.[I71 P. R. Belanger, E. L. Adler and N. C. Rumin, Introduction to Circbitswith Electronics. New York: Holt, Rinehart and Winston, 1985, pp.329-331, 353-356.1181 J. Y. Chen, CMOS Devices and Technology for VLSI. EnglewcodCliffs, NJ: Prentice-H all, 1990, pp. 94-98.[I91 D. A. Pucknell and K. Eshraghian, Basic VLSI Design . EnglewcodCliffs, NJ: Prentice-Hall, 1988, pp. 244-245.[ZO] P. M. Chirlian, Analysis and Design o Integrated E lertronic Circusts.New York: Harper and Row, 1987, pp. 348-353.

New York: McGraw-Hill, 19x3, pp. 68-85.New York: Wiley , 1984 , pp. 155-156.

John R Hauser (S59-MSO-SM78-F-87) wasborn near Mocksville, NC, on September 19, 1938.He received the B.S. degree in electrical engineer-ing from North Carolina State University in 1160and the M.S. and Ph.D. degrees, also in electricalengineering, from Duke University, Durham, NC in1962 and 1964, respectively.In 1960 and 1961, he was with Bell TelephoneLaboratories, W inston-Salem, NC, where he workedon the design of electronic circuits. In June 162he ioined the Research Triangle Institute. D ur hm .where he did research work on semiconductor and m icroelectronic devices. Hejoined the faculty at North Carolina State University, Raleigh, in September196 6 where is presently a Professor of electrical engineering and Directoi ofthe Solid State Electronics Laboratory. His present interests are in the areasof microelectronics and solid-state devices.Dr. Hauser is a member of Eta Kappa Nu, Sigma Xi. and the Ameri:anPhysical Society.

noise margin criteria for digital logic

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