Noise Canceling in 1-D Data: Presentation #9

Seri Rahayu Abd RaufFatima BoujarwahJuan ChenLiyana Mohd SharippArti Thumar

M2

Mar 23rd, 2005Full chip LVS

Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware

Project Manager: Bobby Colyer

Status

• Design proposal (Done)

• Architecture proposal (Done)

• Size Estimates and Floorplan (Done)

• Gate Level Design

- Schematics (Done)

• To be done:– Layout (85%)– Spice simulation

Design Decisions

• Redesigned the horizontal FP Adder to be more similar to vertical floorplan

• Redesign buffers H-tree buffer to facilitate abutment with other cells

• Placement of AND gates and Mirror Adders in the Wallace tree

Last Week’s Floorplan

Current Floorplan

Old vs. New FP Multiplier (A)

Wallace Layout (old buffers)

Wallace layout (new buffers)

Old vs. New FP Adder (vertical)

FP Adder (old horizontal)

Floating Point Adder (horizontal)

Challenges…

• Finishing up layout

• Make sure that the signal strength is sufficient (buffering)

• Global wiring

• Shrinking functional blocks (white space)

Questions?