new technologies, materials or assembly processes...

iNEMI Assembly-Level Reliability Qualification for Enterprise PCBAs Final 1/26/2014

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New Technologies, Materials or Assembly

Processes: Assembly-Level Reliability

Qualification for Enterprise PCBAs

Revision: Final, Approved 1/26/2014

CHAIRS:

Aamir Kazi, Dell

Thomas Homorodi, Dell

CONTRIBUTORS:

(IN ALPHABETICAL ORDER BY COMPANY NAME)

Fubin Song, Celestica

Mitchell Ferrill, IBM

Jeffrey Lee, iST –Integrated Service Technology, Inc.

Tomy Dong, Lenovo

Vico Duan, Lenovo

Leo Zhao, Lenovo

John Godfrey, Microsoft

Ander Hsieh, Wistron

Jimmy Yang, Wistron

PROJECT MANAGER:

Mark Schaffer, iNEMI


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Table of Contents

Table of Contents ................................................................................................................ 2

1. Glossary of Terms ....................................................................................................... 3 2. Introduction & Scope................................................................................................... 4 3. Applicability and Scope............................................................................................... 4 4. Reference Documents .................................................................................................. 5

4.1. Assembly Materials Reference ............................................................................. 5

4.2. Printed Circuit Board and Assembly Reference .................................................. 5 4.3. Test Procedure Reference ..................................................................................... 5

5. Materials and Material Restrictions ............................................................................. 6 6. Assembly, Process & PCB Data Collection ................................................................ 6

7. Qualification Considerations ....................................................................................... 7 7.1. Test Sample Allocation ........................................................................................ 7

8. Qualification Sample Assembly .................................................................................. 9 8.1. Assembly, Rework and Repair Conditions .......................................................... 9

9. Testing ......................................................................................................................... 9 9.1. Overview .............................................................................................................. 9 9.2. Test Menu ............................................................................................................. 9

9.3. Test Vehicle........................................................................................................ 10 9.4. Functional Testing and Interconnect Verification .............................................. 10

9.5. Time Zero Characterization ............................................................................... 10 9.6. Test Menu Details .............................................................................................. 11

10. Accept/ Reject Criteria ........................................................................................... 13

11. Report Template..................................................................................................... 17

APPENDICES .................................................................................................................. 18


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1. Glossary of Terms

Abbreviation Expansion

ATC Accelerated Thermal Cycling

BGA Ball Grid Array integrated circuit

CM

Contract Manufacturer: an entity that is outsourced to build hardware under contract for

another entity, such as an OEM.

Customer A term used to refer to an OEM (in this document).

FR4

A grade of composite material, built with woven glass and flame-resistant epoxy resin,

which is then copper-laminated to manufacture PCBs.

HTB High Temperature Bake

IC Integrated Circuit

ICT

In-circuit tester: a bed-of-nails tester using pogo-pin probes to perform multiple

simultaneous electrical-check routines on a PCBA.

ODM

Original Design Manufacturer: an entity that designs and builds hardware for an OEM

that sells it under the latter's brand.

OEM

Original Equipment Manufacturer: in this case refers to the entity that commissions an

assembled PCBA/ product from an ODM or CM and sells it under its own brand. An

OEM may design the product, and have a CM build it, or may rely on an ODM to

design and build it.

PCB Printed circuit board - unassembled board before soldering processes.

PCBA

Printed circuit board assembly - board assembly with components after all solder

assembly processes are complete.

PTH Plated Through Hole

RoHS

The European Union's (EU) Restriction of Hazardous Substances Directive: legislation

regulating the use of materials deemed hazardous to the environment or health by the

EU, in electronics manufacturing consumable or non consumable.

SIR Surface Insulation Resistance

SMT Surface Mount Technology

TH Through Hole

THB Temperature and Humidity with Bias

TSS Thermal Ship Shock


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2. Introduction & Scope

This document provides requirements for the assembly-reliability qualification of Printed Circuit Board

Assemblies (PCBAs) on enterprise products. This document is scoped to apply to PCBAs in all enterprise

products (e.g. servers, storage, option cards, network switches, etc.). It serves to establish a common

hardware reliability qualification process for ODMs/ CMs manufacturing computing hardware (servers,

storage and switches) to be deployed in offices, datacenters, as well as environmentally controlled telecom

datacenters.

This document must be used to qualify new aspects of manufacturing and design such as, but not limited to,

new manufacturing facilities, changes in materials, process, and new design elements. It also applies to

repair facilities used for enterprise products employing rework solder processes

It was developed through an iNEMI industry project with the goals of:

Development of a standardized reliability qualification procedure for enterprise products using

existing industry specs for acceptability and testing of PCBAs.

Create a level playing field and setting consistent expectations across the industry

Resolving ambiguity with qualification processes at CMs/EMs to satisfy their various OEMs

qualification demands.

Have suppliers accept responsibility for qualification work.

Reduce cost for EMs/CMs/ODMs due to varied test protocols/qualification process flows to

comply with variances between multiple OEMs’ qualification requirements for similar hardware.

3. Applicability and Scope

This document IS: This document IS NOT:

Defining an OEM/industry-wide set of PCBA reliability qualification methods and processes (toolbox) for developed products using:

• new suppliers • new technologies • new materials • new processes

… as applies to ODM/CM PCBA manufacturers - Primary focus is on Enterprise products (including telecom data centers)

Intended for • Outdoor-telecom • Military/aerospace • Medical

For supplier qualifications intended to evaluate capability and quality. The document is meant to qualify new technologies where process development work is complete.

Early R&D for new technology/process or materials’ viability; not for process definition/development or material evaluation

Identification of Best Known Methods/ Practices in reliability of electronic OEMs for “new” qualifications.

Developing new reliability test standards/procedures/test methods Testing/materials resources commitment

Utilizes existing industry standards/procedures wherever appropriate.

Regulatory/environmental materials compliance


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PCBA-level qualification, with evaluation of risk sites on PCBs that depend on solder-assembly process

Re-creation of component qualification test methods and processes

A reliability qualification of newly developed solder assembly processes, technologies, materials at manufacturing facilities of new and existing suppliers.

Failure Analysis requirement/procedure development

Raw PCB material/ construction evaluation

Definition of test-level failure criteria. Definition of qualification-suite level failure criteria – this is the domain of each OEM, and defined by them

4. Reference Documents Listed below are pertinent references which include standards and procedures directly called out in the

succeeding sections as well as indirectly applicable to the assembly level The reader is directed to apply the

latest edition thereof, at the time of application.

4.1. Assembly Materials Reference Directive of the European Parliament and of the Council on the Restriction of the Use of Certain

Hazardous Substances in Electrical and Electronic Equipment, refer to latest release

Directive of the European Parliament and of the Council on Waste Electrical and Electronic

Equipment (WEEE Directive)

J-STD-004, Requirements for Fluxes

J-STD-005, Requirements for Soldering Pastes

J-STD-006, Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid

Solders for Electronic Soldering Applications

J-STD-075, Classification of Non-IC Electronic Components for Assembly Processes

J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface

Mount Devices

IPC-7095, Design and Assembly Process Implementation for BGAs

4.2. Printed Circuit Board and Assembly Reference IPC-A-610, Acceptability of Electronic Assemblies

IPC-6012, Qualification and Performance Specification for Rigid Printed Boards

IPC-6013, Qualification and Performance Specification for Flexible Printed Boards

J-STD-001, Requirements for Soldered Electrical and Electronic Assemblies

4.3. Test Procedure Reference IPC TM-650, Test Methods Manual

JESD22-A104, Temperature Cycling

IPC 9701, Performance Test Methods and Qualification Requirements for Surface Mount Solder

Attachments

IPC/JEDEC 9702, Monotonic Bend Characterization

IPC/JEDEC 9704, Printed Wiring Board Strain Gage Test Guideline

JESD22-B112, Package Warpage Measurement Of Surface-Mount Integrated Circuits At Elevated

Temperature

JESD22-B108, Coplanarity Test For Surface-Mount Semiconductor Devices


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5. Materials and Material Restrictions Allowable materials and the associated requirements are typically customer specific and therefore will not be defined in this document. A complete materials list, associated with the product(s) to be

assembled, shall be provided to the customer for review early in the engagement process. Any

customer specific materials and material requirements must also be identified and shared at the same

time.

Materials include, but are not limited to:

1. PCB raw materials – including solder mask and conductor surface coating/finish

2. Solder materials (bars, pastes, wire, preforms etc.)

3. Fluxes (wave, solder pot, touch up, etc.)

4. Adhesives (thermal and component securing)

5. Cleaners

6. Solder mask repair

7. Encapsulants

In general, the following will apply:

1. All materials must be EU ROHS compliant. Verification and documentation pertinent to this

is not within this document’s scope.

2. Materials shall be those commonly used and recognized in the industry. The contract

manufacturer or supplier must have performance data (quality, reliability, yield, etc.) to

support the use of any material.

3. Specific to the PCB,

a. Materials shall be thermally robust to the required assembly temperature profiles.

b. PCB surface finishes shall be chosen to ensure that the product performs to

customer’s required airborne contamination level.

6. Assembly, Process & PCB Data Collection The ODM/CM shall provide the following assembly process information when submitting test samples for

reliability evaluation to internal labs or third party labs.

The process profiles for critical assembly processes as shown below. Temperature monitoring

thermocouple location and mounting data may be required for verification.

o Reflow process profile showing ramp rates, peak temperatures and dwell times.

o Wave solder and selective solder process profiles showing preheat temperature, conveyor

speed, peak wave temperature, time over wave and cool down rates.

o Rework process temperature profiles for SMT and PTH components.

Solder, Solder paste, and flux specifications.

Assembly location and supplier name including second and third tier sub-suppliers (for plug-in

assemblies, daughter-cards, etc.).

Rework process specification and procedures, if and when selected components are expected to be

reworked in production for any reason.

The following information shall be provided for each PCBA submitted for reliability evaluation to internal

labs, third party labs, or qualification performed at the supplier. All the listed information might not be

easily obtained; in such circumstances, the OEM may use its discretion to waive part(s) of the information

requests listed below.


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PCB and Component reporting requirements Item Requirements

PCB

Specification

including

Documentation of compliance to appropriate internal and external PCB

component engineering spec.

Material description (FR4, Polyamide etc.), Laminate supplier(s) and PCB

Mfr(s).

Glass transition temperature (Tg,),

Thermal Decomposition temperature (Td),

Heat resistance for PCB (not PCB material only)

Surface finish

Coefficient of thermal expansion (CTE) data in X-, Y-, and Z-axes; below and

above Tg

Cross-section (stack-up) data showing, core thickness, minimum copper

thickness on surface Cu, PTH, Blind via and micro via

Minimum conductor spacing,

Surface Insulation Resistance (SIR) data

Components Documentation showing compliance with appropriate customer/ industry specs

for moisture sensitive components and for heat sensitive components

CTE data for SMT components without leads (coefficients X, Y, Z axes)

For packaged IC’s: rated heat resistance per MSL level per J-STD-020/ latest

rev (not applicable for passive/ non-IC components)

Heat resistance/ temperature sensitivity (Package Peak Reflow Temperature

Classification) for specifically sensitive non IC components (per J-STD-075)

Termination / lead finish, BGA Solder Alloy

7. Qualification Considerations

7.1. Test Sample Allocation The qualification effort requires system and PCBA allocations. Approximate sample allocation is provided

below for budgetary estimation. Final sample sizes will be determined after evaluation of the product under

review; based on the novelty or complexity characteristics of the assembly, additional samples may be

required. Certain test activities are required for all qualifications, while others are optional per table

following.


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Test/ Activity Always required? Yes/No Remarks

Visual Inspection Yes On all samples built for qualification

Cross section Yes On subsets of un-reworked, reworked, and post-test samples

Dye and Pry Yes On selected BGAs of subsets of un-reworked, reworked, and post-test samples

X-ray Yes On all samples built for qualification

Accelerated Thermal Cycling (ATC) Yes Required at every new design qualification cycle

Temperature and Humidity with Bias (THB) No

Optional, based conductor spacing: when reduced from previous generation; and other new features affecting current density

High Temperature Bake (HTB) No

Optional based on PCB material, solder joint under mechanical load; adhesives sensitive to LT temperature exposure

Mechanical Shock No Dependent on mechanical design and deployment environment

Mechanical Vibration No Dependent on mechanical design and deployment environment

Surface Insulation Resistance (SIR) No New fluxes/ flux combinations/ surface finish

Bend Testing No

Dependent on mechanical design and assembly, installation, deployment, repair/ rework conditions

In Circuit Test (ICT) Fixture Verification Yes

Required at every new design qualification cycle (unless ICT is not part of standard process)

Area Array Coplanarity testing No

Used to measure warp under reflow conditions for certain area array components susceptible to warp

Thermal Ship Shock (TSS) No

Used to simulate exposure during product transport (example, in trucks and airplanes)

The following chart provides sample sizes for each test:

Minimum Sample Sizes for Required Testing Additional Sample Allocations for Optional Testing All hardware to be inspected (non destructively) and pass relevant

functional/ electrical verification before and after testing

Thermal Cycle:

4 NonRW,

4 RW

Mechanical Shock:2 NRW, 2 RW

Vibration:2 NRW, 2 RW

9 PCBAs,

not re-worked

(NRW)

9 PCBAs:

Forced rework

(RW)

Functional Test,

Visual Inspection and

X-ray inspection:

All samples

Cross section 2 NRW, 2 RW;Dye and Pry

2 NRW, 2 RW

ICT Fixture

Verification

1 NRW,

1 RW

Temperature and Humidity with Biastest-vehicle boards;

2 NRW & 2 RW

High Temp Bake:2 samples, NRW 2 samples RW

SIR testing5 or more test

vehicles, with NRW and RW represented

on test coupons

Bend Testing2 NRW2RW

Thermal Ship Shock (TSS):

1 NRW1 RW

Area Array Coplanarity

1-3 NRW1-3 RW


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8. Qualification Sample Assembly

8.1. Assembly, Rework and Repair Conditions The majority of the qualification samples will be manufactured using the prime / initial assembly

processes (SMT, wave solder, press fit, etc). A subset of the qualification will have pre-selected

components removed and replaced with an identical component (forced rework). Typically forced

rework will be requested on the most complex components / technologies on the PCBA. The table

below provides a list of components that will likely be included in the forced rework plan. It should

be noted that rework of mirrored BGAs (opposite one another on the top and bottom side of the

PCB) is considered to be among the most difficult rework operations and should be included in the

qualification matrix if present. Some of the concerns to be assessed for mirrored BGA designs are:

(a) Confirm there is no degradation of the solder joints opposite to the one being reworked

(b) Verify that no damage is done to the PCB material

(c) Determine if site dress and fluxing of the reworked site results in excess flux flowing through the

PTHs to the component on the opposite side

The forced rework plan must be approved by both the customer and contract manufacturer. The

rework methods / techniques and thermal profiles should be reviewed with and approved by the

customer prior to commencing rework. The detailed rework procedures must be available for each

component type and the operators must be sufficiently trained and certified to perform these rework

operations..

If rework / repair is done in multiple facilities, for example both at the original contract manufacturer

and at a warranty repair center, then it will generally be expected that forced rework samples from each

location be included in the qualification matrix.

Component Rework Levels X-ray Inspect

(if possible) Large, high I/O BGA 1X & 2X Y

Socket(s) / hybrid LGA 1X & 2X Y Connector(s) 1X & 2X Y PBGA(s) 1X & 2X Y QFP(s) 1X & 2X Y FC-QFN 1X & 2X Y

Fine pitched BGA(s) 1X & 2X Y Memory Connectors 1X & 2X Y

9. Testing

9.1. Overview When technology, material, process, contract manufacturer, or combinations of these factors

warrant a reliability evaluation, eligible tests, which may be requested by the customer, are listed in

the “Test Menu” section below. Accelerated Thermal Cycling (ATC) shall be the minimum test

requirement.

9.2. Test Menu The following tests may be required by the customer for reliability evaluation:

I. Accelerated Thermal Cycling (ATC)

II. Temperature and Humidity with Bias (THB)

III. High Temperature Bake (HTB)


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IV. Mechanical Shock

V. Mechanical Vibration

VI. Surface Insulation Resistance (SIR)

VII. Bend Testing

VIII. In Circuit Test (ICT) Fixture Verification

IX. Thermal Ship Shock (TSS)

Thermal Ship Shock, mechanical shock, and mechanical vibration may be requested as stand alone

tests or they may be used as hardware preconditioning steps prior to other tests, such as ATC. The

specific menu items to be executed shall be agreed to between the contract manufacturer and the

customer.

9.3. Test Vehicle The standard reliability test vehicle shall be functional product in a configuration as specified by or

agreed to by the customer. Exceptions are as follows:

1. If SIR testing is requested, the IPC-B52 test vehicle shall be utilized rather than functional product

2. Special test vehicles, such as one with daisy chained components, may be requested for any test

menu reliability evaluation. When this avenue is chosen, specific test and pass/fail criteria shall be

agreed to between the contract manufacturer and customer.

9.4. Functional Testing and Interconnect Verification Functional testing shall be used to confirm the product is operating properly and as a high level

verification that PCBA interconnects are intact. ICT, when applicable, should be performed during

the product assembly process, as ICT generally provides a more thorough evaluation of interconnects.

Functional testing alone is not adequate to verify PCBA interconnect and therefore a “Pass” is not

sufficient to achieve qualification, unless agreed to by the customer. Post stress test completion,

destructive analysis shall be performed to assess PCBA interconnects integrity. The specific

component locations and interconnects to be evaluated must be agreed to between the customer and

the contract manufacturer. Dye/Pry and cross-sectioning are the standard methods for evaluating

interconnect integrity. For components with a large number of I/O, such as BGAs, the dye/pry

method provides a simple method to evaluate the integrity of all interconnects in the least amount of

time.

9.5. Time Zero Characterization Time zero characterization, at a minimum, shall include functional testing and visual inspection. X-

ray and/or acoustical microscopy inspection may also be requested by the customer as additional

characterization methods. Requirements and criteria are to be agreed between the customer and

contract manufacturer.

The visual inspection standard for PCBAs shall be IPC-610 (latest version) to Class 2 criteria. If either

the contract manufacturer or the customer have inspection standards that differ from IPC-610,

especially if the criteria is less stringent than IPC-610 – Class 2, then these shall be discussed and

agreed to prior to beginning the reliability evaluation. Also, if there are inspection requirements above

those specified in IPC-610, these should be highlighted.

Procedure:

1. 100% inspect each board (attempt to identify root cause of any functional fails ) 2. Record any defects (should list board #, components, and defects observed).

3. Investigate IPC-610 or functional failures and identify corrective actions; perform analysis as

necessary (with customer agreement)

4. Disposition PCBAs to their designated reliability tests.; if there is fallout for defects (i.e. -

functional fails and/or inspection fails), the contract manufacturer and customer must agree

as to how to proceed.in populating the reliability tests


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9.6. Test Menu Details

A.) Accelerated Temperature Cycling

- Test Conditions: 0 to 100°C

- Test Specification: JESD22-A104 (latest version) – Condition J / Soak Mode 3; Ramp rate

15°C/min or less typical, 10°C to 14°C/minute preferred; Minimum soak time of 10 minutes

each temperature extreme.

- Required Test Cycles: 1000 cycles (minimum – additional cycling may be required by

the customer)

- Functional Readout Times: Time zero, post 250 cycles, post 500 cycles, post 1000

cycles (minimum – additional readout times may be requested by the customer)

PCBAs shall be instrumented with thermocouples and cycling performed to ensure t h e h a r d w a r e

complies with the JESD22-A104, Condition J, Soak Mode 3, and associated ramp rate requirements.

Locations of the thermocouples on individual test samples and which sample locations in the thermal

cycle chamber should be profiled shall be agreed with the customer prior to beginning the profiling work.

The final ATC profile shall be agreed to by the customer prior to proceeding with the thermal cycling

test.

B.) Temperature Humidity with Bias

- Test Conditions: 40°C/85% RH

- Required Test Hours: 400 hours minimum

- Functional Readout Times (if monitoring is not possible in stress chamber): Time zero, post

200 hrs, post 400 hrs.

Functional hardware shall be configured in the stress chamber such that it can be powered and

exercised.

Acceleration models RH from JEP122g (Failure Mechanisms And Models For Semiconductor Devices)

may be employed.

C.) High Temperature Bake

- Test Conditions: 125 -0/+5°C

- Test Specification: None

- Required Test Time: 1000 hours (minimum – additional test time may be required by

the customer)

- Functional Readout Times: Time zero, post 500 hours, post 1000 hours (minimum –

additional readout times may be requested by the customer)

It should be noted that some components cannot tolerate a 125°C bake for 1000 hrs. The PCBA bill of

materials should be reviewed to determine what components, if any are at risk. If there are components

at risk, the test temperature may need to be reduced and test time increased to values agreed to by both

the contract manufacturer and the customer.

PCBAs shall be instrumented with thermocouples and baking performed to ensure t h e t e s t

h a r d w a r e complies with the specified temperature range. Locations of the thermocouples on

individual test samples and which sample locations in the oven should be profiled shall be agreed with the

customer prior to beginning the profiling work. The optimized profile is to be shared with and agreed to

by the customer prior to proceeding with the HTB test.

D.) Mechanical Shock

- Test Conditions: As specified and/or agreed with the customer

- Test Specification: As specified and/or agreed with the customer

- Required Test Time: As specified and/or agreed with the customer


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- Functional Readout Times: Time zero, post mechanical shock (minimum)

Mechanical shock may be used to simulate two conditions – 1) product shipping shock and 2) product

operational shock. Test parameters will generally vary depending on which type of shock testing is

chosen. When evaluating shipping shock, the various methods that the PCBA can be shipped should

be taken into consideration (examples. – individual shipping box, installed in a higher level assembly

shipped in a box, or shipped installed in a system). PCBAs shall be instrumented such that it is assured

the product complies with the agreed to test conditions.

E.) Mechanical Vibration

- Test Conditions: As specified and/or agreed with the customer


- Required Test Time: As specified and/or agreed with the customer

- Functional Readout Times: Time zero, post mechanical vibration (minimum)

Mechanical vibration may be used to simulate two conditions – 1) product shipping vibration and 2)

product operational vibration. Test parameters will generally vary depending on which type of

vibration testing is chosen. When evaluating shipping vibration, the various methods that the PCBA

can be shipped should be taken into consideration (examples. – individual shipping box, installed in a

higher level assembly shipped in a box, or shipped installed in a system). PCBAs shall be instrumented

such that it is assured the product complies with the agreed to test conditions.

F.) Surface Insulation Resistance

- Test Conditions: 40°C, 90%RH, 5V

- Test Specification: IPC 9202 Conditions as per table 8-1)

- Test Vehicle: IPC-B-52

- Reference Documents: IPC 9203, IPC 9201-A, IPC 5702

- Required Test Time: 168 hours minimum

- Functional Readout Times: As specified in IPC 9202

Test chamber to be set up, profiled, and brought up to test conditions as specified in IPC 9202.

G.) Bend Testing

- Test Conditions: As specified in IPC-9702

- Test Specification: IPC-9702, IPC-9704 (latest versions)

- Required Test Time: As specified in IPC-9702 and IPC-9704

- Functional Readout Times: Time zero, post bend testing

This testing is to be conducted with daisy chained test vehicles as discussed in the latest versions of

IPC-9702 and IPC 9704, which address 4-point bending and spherical bending respectively. As IPC-

9704 does not prescribe max principal strain limits for SAC alloys, mutually agreed-upon limits shall

be established prior to testing.

H.) In-Circuit-Test Fixture Verification

- Test Conditions: Functional product in ICT fixture with multiple actuations


- Required Test Parameters:

o Test hardware to be instrumented with strain gauges at component/ PCBA

locations mutually agreed to by supplier and OEM. IPC/JEDEC 9704, Printed

Wiring Board Strain Gage Test Guideline, is to be followed for strain gauge

placement.

o Minimum requirement: 5 ICT fixture actuation cycles minimum, 1 minute “rest”

minimum between actuations


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o Over stress: It is also recommended that at least one sample be exposed to an over

stress condition. Over stress can be induced either by a high number of actuations

cycles or by exceeding the maximum measured deflection/displacement. The over

stress requirements shall be defined by the customer.

- Functional Readout Times:

o 5 Actuation cycle test: Time zero after the 5 th actuation cycle (minimum) –

customer may request that full ICT testing be performed on each actuation

o Over stress test: To be defined by the customer

o Measured strain not to exceed previously agreed-to limits generally prescribed by

component manufacturer(s), at any time during the test.

I.) Thermal Shock Stress

- Test Conditions: -40 -5/+0°C to +65 -0/+5°C, goal hardware to dwell a minimum of 10

minutes at each extreme (dwell is intended to assure that all hardware equilibrates at each

temp extreme)

- Test Specification: None

- Test Chamber: Two compartment (air to air) style chamber preferred, but if unavailable,

standard one compartment chamber may be utilized with shortest cycle rate possible

- Required Test Time: Number of cycles as specified by the OEM

- Functional Readout Times: Time zero, post thermal ship shock (minimum)

PCBAs shall be instrumented with thermocouples and cycling performed to ensure t h e h a r d w a r e

complies with the specified profile. Locations of the thermocouples on individual test samples and which

sample locations in the thermal cycle chamber should be profiled shall be agreed with the customer prior

to beginning the profiling work. The optimized profile is to be shared with and agreed to by the

customer prior to proceeding with the thermal ship shock test.

J.) Area-array Component Co-planarity

This test is useful to ensure that excessive and undesirable warping of an array-type surface-mount

component does not occur at reflow temperatures, which has the potential to result in solder joints

malformation or opens at the corner solderballs. It is applicable to packages susceptible to to warp

due to their size or type; examples include BGAs, area array connectors, etc.

Procedure:

Follow JESD22-B108A at the (ROHS-compliant/ lead free) reflow profile to confirm that the co-

planarity of the package substrate falls within the flatness specification for the component(s) under

consideration at reflow temperature. Thermal Shadow Moiré fringe analysis is recommended for

this test, per JESD22-B112.

Failure criteria for these components shall be set by their component manufacturers, from their

specified limits for maximum warp.

10. Accept/ Reject Criteria It is advised to be familiar with the latest available release of all applicable specifications and test

procedures and follow the details as described prior to start of any reliability test. Summary information for

each test is provided in the following sections for reference only. A table of criteria follows.


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11. Report Template Summary results for the qualification activity shall be recorded in an appropriate format,

such as the table provided below:

Test/ Activity

Number of Samples tested (RW and NRW)

Result: Pass/ Fail, or NA (if test is waived)

Remarks/ failure summary

Detailed report storage link/ location

Time-zero Functional test

Time Zero Visual Inspection

Time Zero Cross section

Time Zero Dye and Pry

Time Zero X-ray

Accelerated Thermal Cycling (ATC), Interim checkpoint Functional and FA

Accelerated Thermal Cycling (ATC), Post Test Functional and FA

Temperature and Humidity with Bias (THB), Interim Checkpoint Test Functional and FA

Temperature and Humidity with Bias (THB), Post Test Functional and FA

High Temperature Bake (HTB),Post Test Functional and FA

Mechanical Shock, In- and Post-Test Functional and FA

Mechanical Vibration, In- and Post-Test Functional and FA

Surface Insulation Resistance (SIR), In- and Post-Test Functional and FA

Bend Testing, In- and Post-Test Functional and FA

In Circuit Test (ICT) Fixture Verification, In- and Post-Test Functional and FA and strain gauge measurements

Thermal Ship Shock (TSS), Post-Test Functional and FA

Area Array Coplanarity Test

Detailed reports shall be linked to from the summary to an appropriate repository.


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APPENDICES

I. PTH solder joint visual inspection : post temperature cycling

II. Copper Thickness Measurements at Plated Through Hole Knee & Barrel